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rp2040: Resynchronize with upstream Klipper code and support rp2350 chips

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Synchronize with the latest Klipper code.  This pulls in the latest
lib/ files (needed to use the pico-sdk v2.0.0 version).  It updates to
latest can2040 code (needed for pico-sdk v2.0.0 support).  It
implements USB double buffering (as is now done in Klipper).  It adds
in support for additional UART pins (as is now done in Klipper).  It
adds support for rp2350 chips.

This replaces the execute in ram code previously implemented in
Katapult with the execute in ram code that is now standard in Klipper.

The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and
the build now always produces a katapult.withclear.uf2 file.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2024-11-14 12:26:06 -05:00 committed by Eric Callahan
parent 081918ad76
commit c0014efc4a
284 changed files with 148693 additions and 9081 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/.gitignore vendored
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@ -3,3 +3,4 @@ bossac/bin/
bossac/obj/
hidflash/hid-flash
hub-ctrl/hub-ctrl
rp2040_flash/rp2040_flash

29
lib/README
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@ -63,6 +63,11 @@ The stm32f4 directory contains code from:
version v1.24.1 (b5abca20c9676b04f8d2885a668a9b653ee65705). Contents
taken from the Drivers/CMSIS/Device/ST/STM32F4xx/ directory.
The stm32f7 directory contains code from:
https://github.com/STMicroelectronics/STM32CubeF7
version v1.15.0 (3600603267ebc7da619f50542e99bbdfd7e35f4a). Contents
taken from the Drivers/CMSIS/Device/ST/STM32F7xx/ directory.
The stm32g0 directory contains code from:
https://github.com/STMicroelectronics/STM32CubeG0
version v1.4.1 (5cb06333a6a43cefbe145f10a5aa98d3cc4cffee). Contents
@ -73,16 +78,23 @@ The stm32h7 directory contains code from:
version v1.9.0 (ccb11556044540590ca6e45056e6b65cdca2deb2). Contents
taken from the Drivers/CMSIS/Device/ST/STM32H7xx/ directory.
The rp2040 directory contains code from the pico sdk:
The pico-sdk directory contains code from the pico sdk:
https://github.com/raspberrypi/pico-sdk.git
version 1.2.0 (bfcbefafc5d2a210551a4d9d80b4303d4ae0adf7). It has been
version 2.0.0 (efe2103f9b28458a1615ff096054479743ade236). It has been
modified so that it can build outside of the pico sdk. See
rp2040.patch for the modifications.
pico-sdk.patch for the modifications.
The elf2uf2 directory contains code from the pico sdk:
https://github.com/raspberrypi/pico-sdk.git
version 1.2.0 (bfcbefafc5d2a210551a4d9d80b4303d4ae0adf7). Contents
taken from the tools/elf2uf2/ directory.
The rp2040_flash directory contains a light-weight bootsel flash tool.
It uses C part of the the `picoboot_connection` directory found in:
https://github.com/raspberrypi/picotool.git
version v1.1.0 (55fd880c3dc029b961fc1a0967a6cfdc0af02721).
version 2.0.0 (8a9af99ab10b20b1c6afb30cd9384e562a6647f9). Note that
Makefile and main.c are locally developed files (the remaining files
are from the picotool repo).
The hub-ctrl directory contains code from:
https://github.com/codazoda/hub-ctrl.c/
@ -98,13 +110,6 @@ version 2.2.2 (2ab7927a27b7b78ef730782ea5f9b5d2c8f34671). It has been
modified to work with Klipper - see hidflash/README for the
details. See changes.diff for the modifications.
The pru_rpmsg directory contains code from:
https://github.com/dinuxbg/pru-gcc-examples
revision 425a42d82006cf0aa24be27b483d2f6a41607489. The code is taken
from the repo's hc-sr04-range-sensor directory. It has been modified
so that the IEP definitions compile correctly. See pru_rpmsg.patch for
the modifications.
The fast-hash directory contains code from:
https://github.com/ztanml/fast-hash
revision ae3bb53c199fe75619e940b5b6a3584ede99c5fc
@ -125,4 +130,4 @@ callbacks.
The can2040 directory contains code from:
https://github.com/KevinOConnor/can2040
revision 177b0073fe6f19281ee7f7fdbe9599e32d1b4b8b.
commit 13321ce2bc046e059a47def70f977a579a984462.

113
lib/can2040/can2040.c
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@ -1,13 +1,13 @@
// Software CANbus implementation for rp2040
//
// Copyright (C) 2022 Kevin O'Connor <kevin@koconnor.net>
// Copyright (C) 2022,2023 Kevin O'Connor <kevin@koconnor.net>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
#include <stdint.h> // uint32_t
#include <string.h> // memset
#include "RP2040.h" // hw_set_bits
#include "can2040.h" // can2040_setup
#include "cmsis_gcc.h" // __DMB
#include "hardware/regs/dreq.h" // DREQ_PIO0_RX1
#include "hardware/structs/dma.h" // dma_hw
#include "hardware/structs/iobank0.h" // iobank0_hw
@ -128,7 +128,7 @@ static void
pio_sync_setup(struct can2040 *cd)
{
pio_hw_t *pio_hw = cd->pio_hw;
struct pio_sm_hw *sm = &pio_hw->sm[0];
pio_sm_hw_t *sm = &pio_hw->sm[0];
sm->execctrl = (
cd->gpio_rx << PIO_SM0_EXECCTRL_JMP_PIN_LSB
| (can2040_offset_sync_end - 1) << PIO_SM0_EXECCTRL_WRAP_TOP_LSB
@ -148,7 +148,7 @@ static void
pio_rx_setup(struct can2040 *cd)
{
pio_hw_t *pio_hw = cd->pio_hw;
struct pio_sm_hw *sm = &pio_hw->sm[1];
pio_sm_hw_t *sm = &pio_hw->sm[1];
sm->execctrl = (
(can2040_offset_shared_rx_end - 1) << PIO_SM0_EXECCTRL_WRAP_TOP_LSB
| can2040_offset_shared_rx_read << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB);
@ -165,7 +165,7 @@ static void
pio_match_setup(struct can2040 *cd)
{
pio_hw_t *pio_hw = cd->pio_hw;
struct pio_sm_hw *sm = &pio_hw->sm[2];
pio_sm_hw_t *sm = &pio_hw->sm[2];
sm->execctrl = (
(can2040_offset_match_end - 1) << PIO_SM0_EXECCTRL_WRAP_TOP_LSB
| can2040_offset_shared_rx_read << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB);
@ -173,7 +173,7 @@ pio_match_setup(struct can2040 *cd)
sm->shiftctrl = 0;
sm->instr = 0xe040; // set y, 0
sm->instr = 0xa0e2; // mov osr, y
sm->instr = 0xa02a, // mov x, !y
sm->instr = 0xa02a; // mov x, !y
sm->instr = can2040_offset_match_load_next; // jmp match_load_next
}
@ -182,7 +182,7 @@ static void
pio_tx_setup(struct can2040 *cd)
{
pio_hw_t *pio_hw = cd->pio_hw;
struct pio_sm_hw *sm = &pio_hw->sm[3];
pio_sm_hw_t *sm = &pio_hw->sm[3];
sm->execctrl = (
cd->gpio_rx << PIO_SM0_EXECCTRL_JMP_PIN_LSB
| can2040_offset_tx_conflict << PIO_SM0_EXECCTRL_WRAP_TOP_LSB
@ -255,7 +255,7 @@ pio_tx_reset(struct can2040 *cd)
| (0x08 << PIO_CTRL_SM_RESTART_LSB));
pio_hw->irq = (SI_MATCHED | SI_ACKDONE) >> 8; // clear PIO irq flags
// Clear tx fifo
struct pio_sm_hw *sm = &pio_hw->sm[3];
pio_sm_hw_t *sm = &pio_hw->sm[3];
sm->shiftctrl = 0;
sm->shiftctrl = (PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS
| PIO_SM0_SHIFTCTRL_AUTOPULL_BITS);
@ -271,7 +271,7 @@ pio_tx_send(struct can2040 *cd, uint32_t *data, uint32_t count)
uint32_t i;
for (i=0; i<count; i++)
pio_hw->txf[3] = data[i];
struct pio_sm_hw *sm = &pio_hw->sm[3];
pio_sm_hw_t *sm = &pio_hw->sm[3];
sm->instr = 0xe001; // set pins, 1
sm->instr = 0x6021; // out x, 1
sm->instr = can2040_offset_tx_write_pin; // jmp tx_write_pin
@ -287,7 +287,7 @@ pio_tx_inject_ack(struct can2040 *cd, uint32_t match_key)
pio_tx_reset(cd);
pio_hw->instr_mem[can2040_offset_tx_got_recessive] = 0xc023; // irq wait 3
pio_hw->txf[3] = 0x7fffffff;
struct pio_sm_hw *sm = &pio_hw->sm[3];
pio_sm_hw_t *sm = &pio_hw->sm[3];
sm->instr = 0xe001; // set pins, 1
sm->instr = 0x6021; // out x, 1
sm->instr = can2040_offset_tx_write_pin; // jmp tx_write_pin
@ -318,6 +318,14 @@ pio_irq_set(struct can2040 *cd, uint32_t sm_irqs)
pio_hw->inte0 = sm_irqs | SI_RX_DATA;
}
// Completely disable host irqs
static void
pio_irq_disable(struct can2040 *cd)
{
pio_hw_t *pio_hw = cd->pio_hw;
pio_hw->inte0 = 0;
}
// Return current host irq mask
static uint32_t
pio_irq_get(struct can2040 *cd)
@ -662,6 +670,7 @@ tx_schedule_transmit(struct can2040 *cd)
pio_signal_set_txpending(cd);
}
cd->tx_state = TS_QUEUED;
cd->stats.tx_attempt++;
struct can2040_transmit *qt = &cd->tx_queue[tx_qpos(cd, tx_pull_pos)];
pio_tx_send(cd, qt->stuffed_data, qt->stuffed_words);
return 0;
@ -721,6 +730,7 @@ report_callback_error(struct can2040 *cd, uint32_t error_code)
static void
report_callback_rx_msg(struct can2040 *cd)
{
cd->stats.rx_total++;
cd->rx_cb(cd, CAN2040_NOTIFY_RX, &cd->parse_msg);
}
@ -729,6 +739,7 @@ static void
report_callback_tx_msg(struct can2040 *cd)
{
writel(&cd->tx_pull_pos, cd->tx_pull_pos + 1);
cd->stats.tx_total++;
cd->rx_cb(cd, CAN2040_NOTIFY_TX, &cd->parse_msg);
}
@ -748,11 +759,11 @@ report_handle_eof(struct can2040 *cd)
pio_match_clear(cd);
}
// Check if in an rx message is being processed
// Check if message being processed is an rx message (not self feedback from tx)
static int
report_is_rx_eof_pending(struct can2040 *cd)
report_is_not_in_tx(struct can2040 *cd)
{
return cd->report_state == RS_NEED_RX_EOF;
return !(cd->report_state & RS_NEED_TX_ACK);
}
// Parser found a new message start
@ -817,7 +828,7 @@ report_note_eof_success(struct can2040 *cd)
// Parser found unexpected data on input
static void
report_note_parse_error(struct can2040 *cd)
report_note_discarding(struct can2040 *cd)
{
if (cd->report_state != RS_IDLE) {
cd->report_state = RS_IDLE;
@ -880,7 +891,7 @@ report_line_txpending(struct can2040 *cd)
return;
}
// Tx request from can2040_transmit(), report_note_eof_success(),
// or report_note_parse_error().
// or report_note_discarding().
uint32_t check_txpending = tx_schedule_transmit(cd);
pio_irq_set(cd, (pio_irqs & ~SI_TXPENDING) | check_txpending);
}
@ -896,6 +907,13 @@ enum {
MS_CRC, MS_ACK, MS_EOF0, MS_EOF1, MS_DISCARD
};
// Reset any bits in the incoming parsing state
static void
data_state_clear_bits(struct can2040 *cd)
{
cd->raw_bit_count = cd->unstuf.stuffed_bits = cd->unstuf.count_stuff = 0;
}
// Transition to the next parsing state
static void
data_state_go_next(struct can2040 *cd, uint32_t state, uint32_t num_bits)
@ -908,23 +926,35 @@ data_state_go_next(struct can2040 *cd, uint32_t state, uint32_t num_bits)
static void
data_state_go_discard(struct can2040 *cd)
{
report_note_parse_error(cd);
if (pio_rx_check_stall(cd)) {
// CPU couldn't keep up for some read data - must reset pio state
cd->raw_bit_count = cd->unstuf.count_stuff = 0;
data_state_clear_bits(cd);
pio_sm_setup(cd);
report_callback_error(cd, 0);
}
data_state_go_next(cd, MS_DISCARD, 32);
// Clear report state and update hw irqs after transition to MS_DISCARD
report_note_discarding(cd);
}
// Note a data parse error and transition to discard state
static void
data_state_go_error(struct can2040 *cd)
{
cd->stats.parse_error++;
data_state_go_discard(cd);
}
// Received six dominant bits on the line
static void
data_state_line_error(struct can2040 *cd)
{
if (cd->parse_state == MS_DISCARD)
data_state_go_discard(cd);
else
data_state_go_error(cd);
}
// Received six unexpected passive bits on the line
@ -933,7 +963,7 @@ data_state_line_passive(struct can2040 *cd)
{
if (cd->parse_state != MS_DISCARD && cd->parse_state != MS_START) {
// Bitstuff error
data_state_go_discard(cd);
data_state_go_error(cd);
return;
}
@ -941,8 +971,7 @@ data_state_line_passive(struct can2040 *cd)
uint32_t dom_bits = ~stuffed_bits;
if (!dom_bits) {
// Counter overflow in "sync" state machine - reset it
cd->unstuf.stuffed_bits = 0;
cd->raw_bit_count = cd->unstuf.count_stuff = 0;
data_state_clear_bits(cd);
pio_sm_setup(cd);
data_state_go_discard(cd);
return;
@ -972,7 +1001,7 @@ data_state_go_crc(struct can2040 *cd)
int ret = report_note_crc_start(cd);
if (ret) {
data_state_go_discard(cd);
data_state_go_error(cd);
return;
}
data_state_go_next(cd, MS_CRC, 16);
@ -1065,7 +1094,7 @@ static void
data_state_update_crc(struct can2040 *cd, uint32_t data)
{
if (((cd->parse_crc << 1) | 1) != data) {
data_state_go_discard(cd);
data_state_go_error(cd);
return;
}
@ -1083,7 +1112,7 @@ data_state_update_ack(struct can2040 *cd, uint32_t data)
// data_state_line_passive()
unstuf_restore_state(&cd->unstuf, (cd->parse_crc_bits << 2) | data);
data_state_go_discard(cd);
data_state_go_error(cd);
return;
}
report_note_ack_success(cd);
@ -1095,7 +1124,7 @@ static void
data_state_update_eof0(struct can2040 *cd, uint32_t data)
{
if (data != 0x0f || pio_rx_check_stall(cd)) {
data_state_go_discard(cd);
data_state_go_error(cd);
return;
}
unstuf_clear_state(&cd->unstuf);
@ -1106,14 +1135,17 @@ data_state_update_eof0(struct can2040 *cd, uint32_t data)
static void
data_state_update_eof1(struct can2040 *cd, uint32_t data)
{
if (data >= 0x1c || (data >= 0x18 && report_is_rx_eof_pending(cd)))
// Message is considered fully transmitted
if (data == 0x1f) {
// Success
report_note_eof_success(cd);
if (data == 0x1f)
data_state_go_next(cd, MS_START, 1);
else
} else if (data >= 0x1c || (data >= 0x18 && report_is_not_in_tx(cd))) {
// Message fully transmitted - followed by "overload frame"
report_note_eof_success(cd);
data_state_go_discard(cd);
} else {
data_state_go_error(cd);
}
}
// Handle data received while in MS_DISCARD state
@ -1310,13 +1342,28 @@ can2040_start(struct can2040 *cd, uint32_t sys_clock, uint32_t bitrate
{
cd->gpio_rx = gpio_rx;
cd->gpio_tx = gpio_tx;
data_state_clear_bits(cd);
pio_setup(cd, sys_clock, bitrate);
data_state_go_discard(cd);
}
// API function to stop and uninitialize can2040 code
// API function to stop can2040 code
void
can2040_shutdown(struct can2040 *cd)
can2040_stop(struct can2040 *cd)
{
// XXX
pio_irq_disable(cd);
pio_sm_setup(cd);
}
// API function to access can2040 statistics
void
can2040_get_statistics(struct can2040 *cd, struct can2040_stats *stats)
{
for (;;) {
memcpy(stats, &cd->stats, sizeof(*stats));
if (memcmp(stats, &cd->stats, sizeof(*stats)) == 0)
// Successfully copied data
return;
// Raced with irq handler update - retry copy
}
}

10
lib/can2040/can2040.h
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@ -26,11 +26,18 @@ struct can2040;
typedef void (*can2040_rx_cb)(struct can2040 *cd, uint32_t notify
, struct can2040_msg *msg);
struct can2040_stats {
uint32_t rx_total, tx_total;
uint32_t tx_attempt;
uint32_t parse_error;
};
void can2040_setup(struct can2040 *cd, uint32_t pio_num);
void can2040_callback_config(struct can2040 *cd, can2040_rx_cb rx_cb);
void can2040_start(struct can2040 *cd, uint32_t sys_clock, uint32_t bitrate
, uint32_t gpio_rx, uint32_t gpio_tx);
void can2040_shutdown(struct can2040 *cd);
void can2040_stop(struct can2040 *cd);
void can2040_get_statistics(struct can2040 *cd, struct can2040_stats *stats);
void can2040_pio_irq_handler(struct can2040 *cd);
int can2040_check_transmit(struct can2040 *cd);
int can2040_transmit(struct can2040 *cd, struct can2040_msg *msg);
@ -56,6 +63,7 @@ struct can2040 {
void *pio_hw;
uint32_t gpio_rx, gpio_tx;
can2040_rx_cb rx_cb;
struct can2040_stats stats;
// Bit unstuffing
struct can2040_bitunstuffer unstuf;

3264
lib/cmsis-core/core_cm33.h Normal file
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File diff suppressed because it is too large Load Diff

352
lib/cmsis-core/mpu_armv8.h Normal file
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@ -0,0 +1,352 @@
/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.2
* @date 10. February 2020
******************************************************************************/
/*
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

0
lib/rp2040/elf2uf2/elf.h → lib/elf2uf2/elf.h
View File

2
lib/rp2040/elf2uf2/main.cpp → lib/elf2uf2/main.cpp
View File

@ -60,7 +60,7 @@ struct address_range {
typedef std::vector<address_range> address_ranges;
#define MAIN_RAM_START 0x20000000u
#define MAIN_RAM_END 0x20042000u
#define MAIN_RAM_END 0x20082000u
#define FLASH_START 0x10000000u
#define FLASH_END 0x15000000u
#define XIP_SRAM_START 0x15000000u

65
lib/rp2040/boot/picoboot.h → lib/pico-sdk/boot/picoboot.h
View File

@ -16,18 +16,20 @@
#endif
/** \file picoboot.h
* \defgroup boot_picoboot boot_picoboot
* \defgroup boot_picoboot_headers boot_picoboot_headers
*
* Header file for the PICOBOOT USB interface exposed by an RP2040 in BOOTSEL mode.
* \brief Header file for the PICOBOOT USB interface exposed by an RP2xxx chip in BOOTSEL mode
*/
#include "picoboot_constants.h"
#define PICOBOOT_MAGIC 0x431fd10bu
// --------------------------------------------
// CONTROL REQUESTS FOR THE PICOBOOT INTERFACE
// --------------------------------------------
// size 0 OUT - unstall EPs and reset
// size 0 OUT - un-stall EPs and reset
#define PICOBOOT_IF_RESET 0x41
// size 16 IN - return the status of the last command
@ -47,11 +49,17 @@ enum picoboot_cmd_id {
PC_REBOOT = 0x2,
PC_FLASH_ERASE = 0x3,
PC_READ = 0x84, // either RAM or FLASH
PC_WRITE = 5, // either RAM or FLASH (does no erase)
PC_WRITE = 0x5, // either RAM or FLASH (does no erase)
PC_EXIT_XIP = 0x6,
PC_ENTER_CMD_XIP = 0x7,
PC_EXEC = 0x8,
PC_VECTORIZE_FLASH = 0x9
PC_VECTORIZE_FLASH = 0x9,
// RP2350 only below here
PC_REBOOT2 = 0xa,
PC_GET_INFO = 0x8b,
PC_OTP_READ = 0x8c,
PC_OTP_WRITE = 0xd,
//PC_EXEC2 = 0xe, // currently unused
};
enum picoboot_status {
@ -64,14 +72,32 @@ enum picoboot_status {
PICOBOOT_INTERLEAVED_WRITE = 6,
PICOBOOT_REBOOTING = 7,
PICOBOOT_UNKNOWN_ERROR = 8,
PICOBOOT_INVALID_STATE = 9,
PICOBOOT_NOT_PERMITTED = 10,
PICOBOOT_INVALID_ARG = 11,
PICOBOOT_BUFFER_TOO_SMALL = 12,
PICOBOOT_PRECONDITION_NOT_MET = 13,
PICOBOOT_MODIFIED_DATA = 14,
PICOBOOT_INVALID_DATA = 15,
PICOBOOT_NOT_FOUND = 16,
PICOBOOT_UNSUPPORTED_MODIFICATION = 17,
};
struct __packed picoboot_reboot_cmd {
uint32_t dPC; // 0 means reset into bootrom
uint32_t dPC; // 0 means reset into regular boot path
uint32_t dSP;
uint32_t dDelayMS;
};
// note this (with pc_sp) union member has the same layout as picoboot_reboot_cmd except with extra dFlags
struct __packed picoboot_reboot2_cmd {
uint32_t dFlags;
uint32_t dDelayMS;
uint32_t dParam0;
uint32_t dParam1;
};
// used for EXEC, VECTORIZE_FLASH
struct __packed picoboot_address_only_cmd {
uint32_t dAddr;
@ -83,6 +109,13 @@ struct __packed picoboot_range_cmd {
uint32_t dSize;
};
struct __packed picoboot_exec2_cmd {
uint32_t image_base;
uint32_t image_size;
uint32_t workarea_base;
uint32_t workarea_size;
};
enum picoboot_exclusive_type {
NOT_EXCLUSIVE = 0,
EXCLUSIVE,
@ -93,6 +126,20 @@ struct __packed picoboot_exclusive_cmd {
uint8_t bExclusive;
};
struct __packed picoboot_otp_cmd {
uint16_t wRow; // OTP row
uint16_t wRowCount; // number of rows to transfer
uint8_t bEcc; // use error correction (16 bit per register vs 24 (stored as 32) bit raw)
};
struct __packed picoboot_get_info_cmd {
uint8_t bType;
uint8_t bParam;
uint16_t wParam;
uint32_t dParams[3];
};
// little endian
struct __packed __aligned(4) picoboot_cmd {
uint32_t dMagic;
@ -107,9 +154,12 @@ struct __packed __aligned(4) picoboot_cmd {
struct picoboot_range_cmd range_cmd;
struct picoboot_address_only_cmd address_only_cmd;
struct picoboot_exclusive_cmd exclusive_cmd;
struct picoboot_reboot2_cmd reboot2_cmd;
struct picoboot_otp_cmd otp_cmd;
struct picoboot_get_info_cmd get_info_cmd;
struct picoboot_exec2_cmd exec2_cmd;
};
};
static_assert(32 == sizeof(struct picoboot_cmd), "picoboot_cmd must be 32 bytes big");
struct __packed __aligned(4) picoboot_cmd_status {
@ -121,4 +171,5 @@ struct __packed __aligned(4) picoboot_cmd_status {
};
static_assert(16 == sizeof(struct picoboot_cmd_status), "picoboot_cmd_status must be 16 bytes big");
#endif

42
lib/pico-sdk/boot/picoboot_constants.h Normal file
View File

@ -0,0 +1,42 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _BOOT_PICOBOOT_CONSTANTS_H
#define _BOOT_PICOBOOT_CONSTANTS_H
#define REBOOT2_TYPE_MASK 0x0f
// note these match REBOOT_TYPE in pico/bootrom_constants.h (also 0 is used for PC_SP for backwards compatibility with RP2040)
// values 0-7 are secure/non-secure
#define REBOOT2_FLAG_REBOOT_TYPE_NORMAL 0x0 // param0 = diagnostic partition
#define REBOOT2_FLAG_REBOOT_TYPE_BOOTSEL 0x2 // param0 = bootsel_flags, param1 = gpio_config
#define REBOOT2_FLAG_REBOOT_TYPE_RAM_IMAGE 0x3 // param0 = image_base, param1 = image_end
#define REBOOT2_FLAG_REBOOT_TYPE_FLASH_UPDATE 0x4 // param0 = update_base
// values 8-15 are secure only
#define REBOOT2_FLAG_REBOOT_TYPE_PC_SP 0xd
#define REBOOT2_FLAG_REBOOT_TO_ARM 0x10
#define REBOOT2_FLAG_REBOOT_TO_RISCV 0x20
#define REBOOT2_FLAG_NO_RETURN_ON_SUCCESS 0x100
#define BOOTSEL_FLAG_DISABLE_MSD_INTERFACE 0x01
#define BOOTSEL_FLAG_DISABLE_PICOBOOT_INTERFACE 0x02
#define BOOTSEL_FLAG_GPIO_PIN_ACTIVE_LOW 0x10
#define BOOTSEL_FLAG_GPIO_PIN_SPECIFIED 0x20
#define PICOBOOT_GET_INFO_SYS 1
#define PICOBOOT_GET_INFO_PARTTION_TABLE 2
#define PICOBOOT_GET_INFO_UF2_TARGET_PARTITION 3
#define PICOBOOT_GET_INFO_UF2_STATUS 4
#define UF2_STATUS_IGNORED_FAMILY 0x01
#define UF2_STATUS_ABORT_EXCLUSIVELY_LOCKED 0x10
#define UF2_STATUS_ABORT_BAD_ADDRESS 0x20
#define UF2_STATUS_ABORT_WRITE_ERROR 0x40
#define UF2_STATUS_ABORT_REBOOT_FAILED 0x80
#endif

13
lib/rp2040/boot/uf2.h → lib/pico-sdk/boot/uf2.h
View File

@ -11,9 +11,9 @@
#include <assert.h>
/** \file uf2.h
* \defgroup boot_uf2 boot_uf2
* \defgroup boot_uf2_headers boot_uf2_headers
*
* Header file for the UF2 format supported by an RP2040 in BOOTSEL mode.
* \brief Header file for the UF2 format supported by a RP2xxx chip in BOOTSEL mode
*/
#define UF2_MAGIC_START0 0x0A324655u
@ -25,7 +25,14 @@
#define UF2_FLAG_FAMILY_ID_PRESENT 0x00002000u
#define UF2_FLAG_MD5_PRESENT 0x00004000u
#define RP2040_FAMILY_ID 0xe48bff56
#define RP2040_FAMILY_ID 0xe48bff56u
#define ABSOLUTE_FAMILY_ID 0xe48bff57u
#define DATA_FAMILY_ID 0xe48bff58u
#define RP2350_ARM_S_FAMILY_ID 0xe48bff59u
#define RP2350_RISCV_FAMILY_ID 0xe48bff5au
#define RP2350_ARM_NS_FAMILY_ID 0xe48bff5bu
#define FAMILY_ID_MAX 0xe48bff5bu
struct uf2_block {
// 32 byte header

64
lib/rp2040/hardware/address_mapped.h → lib/pico-sdk/hardware/address_mapped.h
View File

@ -10,12 +10,13 @@
//#include "pico.h"
#define __force_inline inline
#define static_assert(a,b)
#define valid_params_if(a,b)
#include "hardware/regs/addressmap.h"
/** \file address_mapped.h
* \defgroup hardware_base hardware_base
*
* Low-level types and (atomic) accessors for memory-mapped hardware registers
* \brief Low-level types and (atomic) accessors for memory-mapped hardware registers
*
* `hardware_base` defines the low level types and access functions for memory mapped hardware registers. It is included
* by default by all other hardware libraries.
@ -36,7 +37,7 @@
* When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write
* 32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`.
*
* RP2040 hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within
* RP-series hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within
* a hardware register so that concurrent access by two cores is always consistent with one atomic operation
* being performed first, followed by the second.
*
@ -57,6 +58,14 @@ extern "C" {
#define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch")
#define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch")
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base
#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS
#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0
#endif
typedef volatile uint64_t io_rw_64;
typedef const volatile uint64_t io_ro_64;
typedef volatile uint64_t io_wo_64;
typedef volatile uint32_t io_rw_32;
typedef const volatile uint32_t io_ro_32;
typedef volatile uint32_t io_wo_32;
@ -70,15 +79,55 @@ typedef volatile uint8_t io_wo_8;
typedef volatile uint8_t *const ioptr;
typedef ioptr const const_ioptr;
// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated
// hardware struct headers in hardware/structs/xxx.h to the raw register definitions
// in hardware/regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset)
// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is
// included outside of a comment instead
#define _REG_(x)
// Helper method used by hw_alias macros to optionally check input validity
#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility
//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) {
// uint32_t rc = (uintptr_t)addr;
// invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types
// return rc;
//}
#if PICO_RP2040
// Helper method used by xip_alias macros to optionally check input validity
__force_inline static uint32_t xip_alias_check_addr(const void *addr) {
uint32_t rc = (uintptr_t)addr;
valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE);
return rc;
}
#else
//static __force_inline uint32_t xip_alias_check_addr(const void *addr) {
// uint32_t rc = (uintptr_t)addr;
// valid_params_if(ADDRESS_ALIAS, rc >= XIP_BASE && rc < XIP_END);
// return rc;
//}
#endif
// Untyped conversion alias pointer generation macros
#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | (uintptr_t)(addr)))
#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | (uintptr_t)(addr)))
#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | (uintptr_t)(addr)))
#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS + hw_alias_check_addr(addr)))
#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS + hw_alias_check_addr(addr)))
#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS + hw_alias_check_addr(addr)))
#if PICO_RP2040
#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr)))
#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr)))
#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr)))
#endif
// Typed conversion alias pointer generation macros
#define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p))
#define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p))
#define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p))
#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p))
#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p))
#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p))
/*! \brief Atomically set the specified bits to 1 in a HW register
* \ingroup hardware_base
@ -126,6 +175,11 @@ __force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint
hw_xor_bits(addr, (*addr ^ values) & write_mask);
}
#if !PICO_RP2040
// include this here to avoid the check in every other hardware/structs header that needs it
#include "hardware/structs/accessctrl.h"
#endif
#ifdef __cplusplus
}
#endif

221
lib/pico-sdk/hardware/flash.c Normal file
View File

@ -0,0 +1,221 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "hardware/flash.h"
#include "pico/bootrom.h"
#if PICO_RP2040
#include "hardware/structs/io_qspi.h"
#include "hardware/structs/ssi.h"
#else
#include "hardware/structs/qmi.h"
#endif
#define FLASH_BLOCK_ERASE_CMD 0xd8
// Standard RUID instruction: 4Bh command prefix, 32 dummy bits, 64 data bits.
#define FLASH_RUID_CMD 0x4b
#define FLASH_RUID_DUMMY_BYTES 4
#define FLASH_RUID_DATA_BYTES 8
#define FLASH_RUID_TOTAL_BYTES (1 + FLASH_RUID_DUMMY_BYTES + FLASH_RUID_DATA_BYTES)
//-----------------------------------------------------------------------------
// Infrastructure for reentering XIP mode after exiting for programming (take
// a copy of boot2 before XIP exit). Calling boot2 as a function works because
// it accepts a return vector in LR (and doesn't trash r4-r7). Bootrom passes
// NULL in LR, instructing boot2 to enter flash vector table's reset handler.
#if !PICO_NO_FLASH
#define BOOT2_SIZE_WORDS 64
static uint32_t boot2_copyout[BOOT2_SIZE_WORDS];
static bool boot2_copyout_valid = false;
static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {
if (boot2_copyout_valid)
return;
// todo we may want the option of boot2 just being a free function in
// user RAM, e.g. if it is larger than 256 bytes
#if PICO_RP2040
const volatile uint32_t *copy_from = (uint32_t *)XIP_BASE;
#else
const volatile uint32_t *copy_from = (uint32_t *)BOOTRAM_BASE;
#endif
for (int i = 0; i < BOOT2_SIZE_WORDS; ++i)
boot2_copyout[i] = copy_from[i];
__compiler_memory_barrier();
boot2_copyout_valid = true;
}
static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
((void (*)(void))((intptr_t)boot2_copyout+1))();
}
#else
static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {}
static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
// Set up XIP for 03h read on bus access (slow but generic)
rom_flash_enter_cmd_xip_fn flash_enter_cmd_xip_func = (rom_flash_enter_cmd_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP);
assert(flash_enter_cmd_xip_func);
flash_enter_cmd_xip_func();
}
#endif
//-----------------------------------------------------------------------------
// Actual flash programming shims (work whether or not PICO_NO_FLASH==1)
void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_t count) {
#ifdef PICO_FLASH_SIZE_BYTES
hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES);
#endif
invalid_params_if(HARDWARE_FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1));
invalid_params_if(HARDWARE_FLASH, count & (FLASH_SECTOR_SIZE - 1));
rom_connect_internal_flash_fn connect_internal_flash_func = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
rom_flash_exit_xip_fn flash_exit_xip_func = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
rom_flash_range_erase_fn flash_range_erase_func = (rom_flash_range_erase_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE);
rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
assert(connect_internal_flash_func && flash_exit_xip_func && flash_range_erase_func && flash_flush_cache_func);
flash_init_boot2_copyout();
// No flash accesses after this point
__compiler_memory_barrier();
connect_internal_flash_func();
flash_exit_xip_func();
flash_range_erase_func(flash_offs, count, FLASH_BLOCK_SIZE, FLASH_BLOCK_ERASE_CMD);
flash_flush_cache_func(); // Note this is needed to remove CSn IO force as well as cache flushing
flash_enable_xip_via_boot2();
}
void __no_inline_not_in_flash_func(flash_flush_cache)(void) {
rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
flash_flush_cache_func();
}
void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, const uint8_t *data, size_t count) {
#ifdef PICO_FLASH_SIZE_BYTES
hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES);
#endif
invalid_params_if(HARDWARE_FLASH, flash_offs & (FLASH_PAGE_SIZE - 1));
invalid_params_if(HARDWARE_FLASH, count & (FLASH_PAGE_SIZE - 1));
rom_connect_internal_flash_fn connect_internal_flash_func = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
rom_flash_exit_xip_fn flash_exit_xip_func = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
rom_flash_range_program_fn flash_range_program_func = (rom_flash_range_program_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM);
rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
assert(connect_internal_flash_func && flash_exit_xip_func && flash_range_program_func && flash_flush_cache_func);
flash_init_boot2_copyout();
__compiler_memory_barrier();
connect_internal_flash_func();
flash_exit_xip_func();
flash_range_program_func(flash_offs, data, count);
flash_flush_cache_func(); // Note this is needed to remove CSn IO force as well as cache flushing
flash_enable_xip_via_boot2();
}
//-----------------------------------------------------------------------------
// Lower-level flash access functions
#if !PICO_NO_FLASH
// Bitbanging the chip select using IO overrides, in case RAM-resident IRQs
// are still running, and the FIFO bottoms out. (the bootrom does the same)
static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) {
#if PICO_RP2040
uint32_t field_val = high ?
IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH :
IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW;
hw_write_masked(&io_qspi_hw->io[1].ctrl,
field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB,
IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS
);
#else
if (high) {
hw_clear_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_ASSERT_CS0N_BITS);
} else {
hw_set_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_ASSERT_CS0N_BITS);
}
#endif
}
void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) {
rom_connect_internal_flash_fn connect_internal_flash_func = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
rom_flash_exit_xip_fn flash_exit_xip_func = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
rom_flash_flush_cache_fn flash_flush_cache_func = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
assert(connect_internal_flash_func && flash_exit_xip_func && flash_flush_cache_func);
flash_init_boot2_copyout();
__compiler_memory_barrier();
connect_internal_flash_func();
flash_exit_xip_func();
flash_cs_force(0);
size_t tx_remaining = count;
size_t rx_remaining = count;
#if PICO_RP2040
// Synopsys SSI version
// We may be interrupted -- don't want FIFO to overflow if we're distracted.
const size_t max_in_flight = 16 - 2;
while (tx_remaining || rx_remaining) {
uint32_t flags = ssi_hw->sr;
bool can_put = flags & SSI_SR_TFNF_BITS;
bool can_get = flags & SSI_SR_RFNE_BITS;
if (can_put && tx_remaining && rx_remaining - tx_remaining < max_in_flight) {
ssi_hw->dr0 = *txbuf++;
--tx_remaining;
}
if (can_get && rx_remaining) {
*rxbuf++ = (uint8_t)ssi_hw->dr0;
--rx_remaining;
}
}
#else
// QMI version -- no need to bound FIFO contents as QMI stalls on full DIRECT_RX.
hw_set_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS);
while (tx_remaining || rx_remaining) {
uint32_t flags = qmi_hw->direct_csr;
bool can_put = !(flags & QMI_DIRECT_CSR_TXFULL_BITS);
bool can_get = !(flags & QMI_DIRECT_CSR_RXEMPTY_BITS);
if (can_put && tx_remaining) {
qmi_hw->direct_tx = *txbuf++;
--tx_remaining;
}
if (can_get && rx_remaining) {
*rxbuf++ = (uint8_t)qmi_hw->direct_rx;
--rx_remaining;
}
}
hw_clear_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS);
#endif
flash_cs_force(1);
flash_flush_cache_func();
flash_enable_xip_via_boot2();
}
#endif
// Use standard RUID command to get a unique identifier for the flash (and
// hence the board)
static_assert(FLASH_UNIQUE_ID_SIZE_BYTES == FLASH_RUID_DATA_BYTES, "");
void flash_get_unique_id(uint8_t *id_out) {
#if PICO_NO_FLASH
__unused uint8_t *ignore = id_out;
panic_unsupported();
#else
uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0};
uint8_t rxbuf[FLASH_RUID_TOTAL_BYTES] = {0};
txbuf[0] = FLASH_RUID_CMD;
flash_do_cmd(txbuf, rxbuf, FLASH_RUID_TOTAL_BYTES);
for (int i = 0; i < FLASH_RUID_DATA_BYTES; i++)
id_out[i] = rxbuf[i + 1 + FLASH_RUID_DUMMY_BYTES];
#endif
}

36
lib/rp2040/pico/flash/hw_flash.h → lib/pico-sdk/hardware/flash.h
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@ -9,19 +9,19 @@
//#include "pico.h"
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdbool.h>
/** \file flash.h
* \defgroup hardware_flash hardware_flash
*
* Low level flash programming and erase API
* \brief Low level flash programming and erase API
*
* Note these functions are *unsafe* if you have two cores concurrently
* executing from flash. In this case you must perform your own
* synchronisation to make sure no XIP accesses take place during flash
* programming.
* Note these functions are *unsafe* if you are using both cores, and the other
* is executing from flash concurrently with the operation. In this could be the
* case, you must perform your own synchronisation to make sure that no XIP
* accesses take place during flash programming. One option is to use the
* \ref multicore_lockout functions.
*
* Likewise they are *unsafe* if you have interrupt handlers or an interrupt
* vector table in flash, so you must disable interrupts before calling in
@ -37,18 +37,21 @@
* \include flash_program.c
*/
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash
#ifndef PARAM_ASSERTIONS_ENABLED_FLASH
#define PARAM_ASSERTIONS_ENABLED_FLASH 0
// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH, Enable/disable assertions in the hardware_flash module, type=bool, default=0, group=hardware_flash
#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH
#ifdef PARAM_ASSERTIONS_ENABLED_FLASH // backwards compatibility with SDK < 2.0.0
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH PARAM_ASSERTIONS_ENABLED_FLASH
#else
#define PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH 0
#endif
#endif
#define FLASH_PAGE_SIZE (1u << 8)
#define FLASH_SECTOR_SIZE (1u << 12)
#define FLASH_BLOCK_SIZE (1u << 16)
#define FLASH_UNIQUE_ID_SIZE_BYTES 8
// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, group=hardware_flash
// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, default=Usually provided via board header, group=hardware_flash
#ifdef __cplusplus
extern "C" {
@ -59,6 +62,10 @@ extern "C" {
*
* \param flash_offs Offset into flash, in bytes, to start the erase. Must be aligned to a 4096-byte flash sector.
* \param count Number of bytes to be erased. Must be a multiple of 4096 bytes (one sector).
*
* @note Erasing a flash sector sets all the bits in all the pages in that sector to one.
* You can then "program" flash pages in the sector to turn some of the bits to zero.
* Once a bit is set to zero it can only be changed back to one by erasing the whole sector again.
*/
void flash_range_erase(uint32_t flash_offs, size_t count);
@ -68,6 +75,10 @@ void flash_range_erase(uint32_t flash_offs, size_t count);
* \param flash_offs Flash address of the first byte to be programmed. Must be aligned to a 256-byte flash page.
* \param data Pointer to the data to program into flash
* \param count Number of bytes to program. Must be a multiple of 256 bytes (one page).
*
* @note: Programming a flash page effectively changes some of the bits from one to zero.
* The only way to change a zero bit back to one is to "erase" the whole sector that the page resides in.
* So you may need to make sure you have called flash_range_erase before calling flash_range_program.
*/
void flash_range_program(uint32_t flash_offs, const uint8_t *data, size_t count);
@ -109,6 +120,7 @@ void flash_get_unique_id(uint8_t *id_out);
*/
void flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count);
void flash_flush_cache(void);
#ifdef __cplusplus
}

31
lib/pico-sdk/hardware/platform_defs.h Normal file
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@ -0,0 +1,31 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_PLATFORM_DEFS_H
#define _HARDWARE_PLATFORM_DEFS_H
#define NUM_CORES 2u
#define NUM_DMA_CHANNELS 12u
#define NUM_GENERIC_TIMERS 1u
#define NUM_ALARMS 4u
#define NUM_IRQS 32u
#define NUM_SPIN_LOCKS 32u
#define XOSC_HZ 12000000u
#define NUM_SPIN_LOCKS 32u
#define NUM_BANK0_GPIOS 30
#ifndef _u
#define _u(x) x ## u
#endif
#endif

117
lib/pico-sdk/pico-sdk.patch Normal file
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@ -0,0 +1,117 @@
diff --git a/lib/pico-sdk/hardware/address_mapped.h b/lib/pico-sdk/hardware/address_mapped.h
index b384f55..635a275 100644
--- a/lib/pico-sdk/hardware/address_mapped.h
+++ b/lib/pico-sdk/hardware/address_mapped.h
@@ -7,7 +7,10 @@
#ifndef _HARDWARE_ADDRESS_MAPPED_H
#define _HARDWARE_ADDRESS_MAPPED_H
-#include "pico.h"
+//#include "pico.h"
+#define __force_inline inline
+#define static_assert(a,b)
+#define valid_params_if(a,b)
#include "hardware/regs/addressmap.h"
/** \file address_mapped.h
diff --git a/lib/pico-sdk/hardware/flash.h b/lib/pico-sdk/hardware/flash.h
index 87dafb1..0227922 100644
--- a/lib/pico-sdk/hardware/flash.h
+++ b/lib/pico-sdk/hardware/flash.h
@@ -7,7 +7,10 @@
#ifndef _HARDWARE_FLASH_H
#define _HARDWARE_FLASH_H
-#include "pico.h"
+//#include "pico.h"
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
/** \file flash.h
* \defgroup hardware_flash hardware_flash
diff --git a/lib/pico-sdk/pico/bootrom.h b/lib/pico-sdk/pico/bootrom.h
index b55e098..6506183 100644
--- a/lib/pico-sdk/pico/bootrom.h
+++ b/lib/pico-sdk/pico/bootrom.h
@@ -7,7 +7,13 @@
#ifndef _PICO_BOOTROM_H
#define _PICO_BOOTROM_H
-#include "pico.h"
+//#include "pico.h"
+#define __force_inline inline
+#define static_assert(a,b)
+#define invalid_params_if(a,b)
+#define assert(a)
+#define pico_processor_state_is_nonsecure() 0
+#define PICO_ERROR_INVALID_DATA BOOTROM_ERROR_INVALID_DATA
#include "pico/bootrom_constants.h"
/** \file bootrom.h
diff --git a/lib/pico-sdk/pico/bootrom/lock.h b/lib/pico-sdk/pico/bootrom/lock.h
index f436557..b98b7a8 100644
--- a/lib/pico-sdk/pico/bootrom/lock.h
+++ b/lib/pico-sdk/pico/bootrom/lock.h
@@ -7,7 +7,7 @@
#ifndef _PICO_BOOTROM_LOCK_H
#define _PICO_BOOTROM_LOCK_H
-#include "hardware/boot_lock.h"
+//#include "hardware/boot_lock.h"
#include "pico/bootrom_constants.h"
// PICO_CONFIG: PICO_BOOTROM_LOCKING_ENABLED, Enable/disable locking for bootrom functions that use shared reqsources. If this flag is enabled bootrom lock checking is turned on and BOOT locks are taken around the relevant bootrom functions, type=bool, default=1, group=pico_bootrom
diff --git a/lib/pico-sdk/rp2040/cmsis_include/RP2040.h b/lib/pico-sdk/rp2040/cmsis_include/RP2040.h
index 8da431f..be66139 100644
--- a/lib/pico-sdk/rp2040/cmsis_include/RP2040.h
+++ b/lib/pico-sdk/rp2040/cmsis_include/RP2040.h
@@ -2572,6 +2572,7 @@ typedef struct { /*!< RTC Structure
* @{
*/
+#if 0
#define RESETS_BASE 0x4000C000UL
#define PSM_BASE 0x40010000UL
#define CLOCKS_BASE 0x40008000UL
@@ -2608,6 +2609,7 @@ typedef struct { /*!< RTC Structure
#define TBMAN_BASE 0x4006C000UL
#define VREG_AND_CHIP_RESET_BASE 0x40064000UL
#define RTC_BASE 0x4005C000UL
+#endif
/** @} */ /* End of group Device_Peripheral_peripheralAddr */
diff --git a/lib/pico-sdk/rp2040/pico/asm_helper.S b/lib/pico-sdk/rp2040/pico/asm_helper.S
index aff1fc9..59c67db 100644
--- a/lib/pico-sdk/rp2040/pico/asm_helper.S
+++ b/lib/pico-sdk/rp2040/pico/asm_helper.S
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include "pico.h"
+//#include "pico.h"
# note we don't do this by default in this file for backwards comaptibility with user code
# that may include this file, but not use unified syntax. Note that this macro does equivalent
diff --git a/lib/pico-sdk/rp2350/cmsis_include/RP2350.h b/lib/pico-sdk/rp2350/cmsis_include/RP2350.h
index 8ae014e..94d0f17 100644
--- a/lib/pico-sdk/rp2350/cmsis_include/RP2350.h
+++ b/lib/pico-sdk/rp2350/cmsis_include/RP2350.h
@@ -5933,6 +5933,7 @@ typedef struct { /*!< USB_DPRAM Structure
* @{
*/
+#if 0
#define RESETS_BASE 0x40020000UL
#define PSM_BASE 0x40018000UL
#define CLOCKS_BASE 0x40010000UL
@@ -5986,6 +5987,7 @@ typedef struct { /*!< USB_DPRAM Structure
#define OTP_DATA_RAW_BASE 0x40134000UL
#define TBMAN_BASE 0x40160000UL
#define USB_DPRAM_BASE 0x50100000UL
+#endif
/** @} */ /* End of group Device_Peripheral_peripheralAddr */

1037
lib/pico-sdk/pico/bootrom.h Normal file
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69
lib/pico-sdk/pico/bootrom/lock.h Normal file
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@ -0,0 +1,69 @@
/*
* Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _PICO_BOOTROM_LOCK_H
#define _PICO_BOOTROM_LOCK_H
//#include "hardware/boot_lock.h"
#include "pico/bootrom_constants.h"
// PICO_CONFIG: PICO_BOOTROM_LOCKING_ENABLED, Enable/disable locking for bootrom functions that use shared reqsources. If this flag is enabled bootrom lock checking is turned on and BOOT locks are taken around the relevant bootrom functions, type=bool, default=1, group=pico_bootrom
#ifndef PICO_BOOTROM_LOCKING_ENABLED
#if NUM_BOOT_LOCKS > 0
#define PICO_BOOTROM_LOCKING_ENABLED 1
#endif
#endif
/**
* \brief Try to acquire a bootrom lock
*
* If PICO_BOOTROM_LOCKING_ENABLED is false, this method returns true immediately
*
* \param lock_num the lock numbers - BOOTROM_LOCK_SHA_256, BOOTROM_LOCK_FLASH_OP or BOOTROM_LOCK_OTP
* \return true if the lock was acquired
*/
static inline bool bootrom_try_acquire_lock(uint lock_num) {
#if PICO_BOOTROM_LOCKING_ENABLED
// unsafe as this is a long term lock (so no irq disable)
return boot_try_lock_unsafe(boot_lock_instance(lock_num));
#else
(void)lock_num;
return true;
#endif
}
/**
* \brief Acquire a bootrom lock. If the lock is unavailable, block until it is available
*
* If PICO_BOOTROM_LOCKING_ENABLED is false, this method does nothing
*
* \param lock_num the lock numbers - BOOTROM_LOCK_SHA_256, BOOTROM_LOCK_FLASH_OP or BOOTROM_LOCK_OTP
*/
static inline void bootrom_acquire_lock_blocking(uint lock_num) {
#if PICO_BOOTROM_LOCKING_ENABLED
// unsafe as this is a long term lock (so no irq disable)
boot_lock_unsafe_blocking(boot_lock_instance(lock_num));
#else
(void)lock_num;
#endif
}
/**
* \brief Release a bootrom lock
*
* If PICO_BOOTROM_LOCKING_ENABLED is false, this method does nothing
*
* \param lock_num the lock numbers - BOOTROM_LOCK_SHA_256, BOOTROM_LOCK_FLASH_OP or BOOTROM_LOCK_OTP
*/
static inline void bootrom_release_lock(uint lock_num) {
#if PICO_BOOTROM_LOCKING_ENABLED
boot_unlock_unsafe(boot_lock_instance(lock_num));
#else
(void)lock_num;
#endif
}
#endif

342
lib/pico-sdk/pico/bootrom_constants.h Normal file
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@ -0,0 +1,342 @@
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _PICO_BOOTROM_CONSTANTS_H
#define _PICO_BOOTROM_CONSTANTS_H
#ifndef NO_PICO_PLATFORM
#include "pico/platform.h"
#endif
// ROOT ADDRESSES
#define BOOTROM_MAGIC_OFFSET 0x10
#define BOOTROM_FUNC_TABLE_OFFSET 0x14
#if PICO_RP2040
#define BOOTROM_DATA_TABLE_OFFSET 0x16
#endif
#if PICO_RP2040
#define BOOTROM_VTABLE_OFFSET 0x00
#define BOOTROM_TABLE_LOOKUP_OFFSET 0x18
#else
// todo remove this (or #ifdef it for A1/A2)
#define BOOTROM_IS_A2() ((*(volatile uint8_t *)0x13) == 2)
#define BOOTROM_WELL_KNOWN_PTR_SIZE (BOOTROM_IS_A2() ? 2 : 4)
#if defined(__riscv)
#define BOOTROM_ENTRY_OFFSET 0x7dfc
#define BOOTROM_TABLE_LOOKUP_ENTRY_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE)
#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_ENTRY_OFFSET - BOOTROM_WELL_KNOWN_PTR_SIZE*2)
#else
#define BOOTROM_VTABLE_OFFSET 0x00
#define BOOTROM_TABLE_LOOKUP_OFFSET (BOOTROM_FUNC_TABLE_OFFSET + BOOTROM_WELL_KNOWN_PTR_SIZE)
#endif
#endif
#if !PICO_RP2040 || PICO_COMBINED_DOCS
#define BOOTROM_OK 0
//#define BOOTROM_ERROR_TIMEOUT (-1)
//#define BOOTROM_ERROR_GENERIC (-2)
//#define BOOTROM_ERROR_NO_DATA (-3) // E.g. read from an empty buffer/FIFO
#define BOOTROM_ERROR_NOT_PERMITTED (-4) // Permission violation e.g. write to read-only flash partition
#define BOOTROM_ERROR_INVALID_ARG (-5) // Argument is outside of range of supported values`
//#define BOOTROM_ERROR_IO (-6)
//#define BOOTROM_ERROR_BADAUTH (-7)
//#define BOOTROM_ERROR_CONNECT_FAILED (-8)
//#define BOOTROM_ERROR_INSUFFICIENT_RESOURCES (-9) // Dynamic allocation of resources failed
#define BOOTROM_ERROR_INVALID_ADDRESS (-10) // Address argument was out-of-bounds or was determined to be an address that the caller may not access
#define BOOTROM_ERROR_BAD_ALIGNMENT (-11) // Address modulo transfer chunk size was nonzero (e.g. word-aligned transfer with address % 4 != 0)
#define BOOTROM_ERROR_INVALID_STATE (-12) // Something happened or failed to happen in the past, and consequently we (currently) can't service the request
#define BOOTROM_ERROR_BUFFER_TOO_SMALL (-13) // A user-allocated buffer was too small to hold the result or working state of this function
#define BOOTROM_ERROR_PRECONDITION_NOT_MET (-14) // This call failed because another ROM function must be called first
#define BOOTROM_ERROR_MODIFIED_DATA (-15) // Cached data was determined to be inconsistent with the full version of the data it was calculated from
#define BOOTROM_ERROR_INVALID_DATA (-16) // A data structure failed to validate
#define BOOTROM_ERROR_NOT_FOUND (-17) // Attempted to access something that does not exist; or, a search failed
#define BOOTROM_ERROR_UNSUPPORTED_MODIFICATION (-18) // Write is impossible based on previous writes; e.g. attempted to clear an OTP bit
#define BOOTROM_ERROR_LOCK_REQUIRED (-19) // A required lock is not owned
#define BOOTROM_ERROR_LAST (-19)
#define RT_FLAG_FUNC_RISCV 0x0001
#define RT_FLAG_FUNC_RISCV_FAR 0x0003
#define RT_FLAG_FUNC_ARM_SEC 0x0004
// reserved for 32-bit pointer: 0x0008
#define RT_FLAG_FUNC_ARM_NONSEC 0x0010
// reserved for 32-bit pointer: 0x0020
#define RT_FLAG_DATA 0x0040
// reserved for 32-bit pointer: 0x0080
#define PARTITION_TABLE_MAX_PARTITIONS 16
// note this is deliberately > MAX_PARTITIONs is likely to be, and also -1 as a signed byte
#define PARTITION_TABLE_NO_PARTITION_INDEX 0xff
// todo these are duplicated in picoboot_constants.h
// values 0-7 are secure/non-secure
#define BOOT_TYPE_NORMAL 0
#define BOOT_TYPE_BOOTSEL 2
#define BOOT_TYPE_RAM_IMAGE 3
#define BOOT_TYPE_FLASH_UPDATE 4
// values 8-15 are secure only
#define BOOT_TYPE_PC_SP 0xd
// ORed in if a bootloader chained into the image
#define BOOT_TYPE_CHAINED_FLAG 0x80
// call from NS to S
#ifndef __riscv
#define BOOTROM_API_CALLBACK_secure_call 0
#endif
#define BOOTROM_API_CALLBACK_COUNT 1
#define BOOTROM_LOCK_SHA_256 0
#define BOOTROM_LOCK_FLASH_OP 1
#define BOOTROM_LOCK_OTP 2
#define BOOTROM_LOCK_MAX 2
#define BOOTROM_LOCK_ENABLE 7
#define BOOT_PARTITION_NONE (-1)
#define BOOT_PARTITION_SLOT0 (-2)
#define BOOT_PARTITION_SLOT1 (-3)
#define BOOT_PARTITION_WINDOW (-4)
#define BOOT_DIAGNOSTIC_WINDOW_SEARCHED 0x01
// note if both BOOT_DIAGNOSTIC_INVALID_BLOCK_LOOP and BOOT_DIAGNOSTIC_VALID_BLOCK_LOOP then the block loop was valid
// but it has a PARTITION_TABLE which while it passed the initial verification (and hash/sig) had invalid contents
// (discovered when it was later loaded)
#define BOOT_DIAGNOSTIC_INVALID_BLOCK_LOOP 0x02
#define BOOT_DIAGNOSTIC_VALID_BLOCK_LOOP 0x04
#define BOOT_DIAGNOSTIC_VALID_IMAGE_DEF 0x08
#define BOOT_DIAGNOSTIC_HAS_PARTITION_TABLE 0x10
#define BOOT_DIAGNOSTIC_CONSIDERED 0x20
#define BOOT_DIAGNOSTIC_CHOSEN 0x40
#define BOOT_DIAGNOSTIC_PARTITION_TABLE_LSB 7
#define BOOT_DIAGNOSTIC_PARTITION_TABLE_MATCHING_KEY_FOR_VERIFY 0x80
#define BOOT_DIAGNOSTIC_PARTITION_TABLE_HASH_FOR_VERIFY 0x100
#define BOOT_DIAGNOSTIC_PARTITION_TABLE_VERIFIED_OK 0x200
#define BOOT_DIAGNOSTIC_IMAGE_DEF_LSB 10
#define BOOT_DIAGNOSTIC_IMAGE_DEF_MATCHING_KEY_FOR_VERIFY 0x400
#define BOOT_DIAGNOSTIC_IMAGE_DEF_HASH_FOR_VERIFY 0x800
#define BOOT_DIAGNOSTIC_IMAGE_DEF_VERIFIED_OK 0x1000
#define BOOT_DIAGNOSTIC_LOAD_MAP_ENTRIES_LOADED 0x2000
#define BOOT_DIAGNOSTIC_IMAGE_LAUNCHED 0x4000
#define BOOT_DIAGNOSTIC_IMAGE_CONDITION_FAILURE 0x8000
#define BOOT_PARSED_BLOCK_DIAGNOSTIC_MATCHING_KEY_FOR_VERIFY 0x1 // if this is present and VERIFIED_OK isn't the sig check failed
#define BOOT_PARSED_BLOCK_DIAGNOSTIC_HASH_FOR_VERIFY 0x2 // if this is present and VERIFIED_OL isn't then hash check failed
#define BOOT_PARSED_BLOCK_DIAGNOSTIC_VERIFIED_OK 0x4
#define BOOT_TBYB_AND_UPDATE_FLAG_BUY_PENDING 0x1
#define BOOT_TBYB_AND_UPDATE_FLAG_OTP_VERSION_APPLIED 0x2
#define BOOT_TBYB_AND_UPDATE_FLAG_OTHER_ERASED 0x4
#ifndef __ASSEMBLER__
// Limited to 3 arguments in case of varm multiplex hint (trashes Arm r3)
typedef int (*bootrom_api_callback_generic_t)(uint32_t r0, uint32_t r1, uint32_t r2);
// Return negative for error, else number of bytes transferred:
//typedef int (*bootrom_api_callback_stdout_put_blocking_t)(const uint8_t *buffer, uint32_t size);
//typedef int (*bootrom_api_callback_stdin_get_t)(uint8_t *buffer, uint32_t size);
//typedef void (*bootrom_api_callback_core1_security_setup_t)(void);
#endif
#endif
/*! \brief Return a bootrom lookup code based on two ASCII characters
* \ingroup pico_bootrom
*
* These codes are uses to lookup data or function addresses in the bootrom
*
* \param c1 the first character
* \param c2 the second character
* \return the 'code' to use in rom_func_lookup() or rom_data_lookup()
*/
#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8))
// ROM FUNCTIONS
// RP2040 & RP2350
#define ROM_DATA_SOFTWARE_GIT_REVISION ROM_TABLE_CODE('G', 'R')
#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X')
#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X')
#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C')
#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F')
#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E')
#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P')
#if PICO_RP2040
// RP2040 only
#define ROM_FUNC_MEMCPY44 ROM_TABLE_CODE('C', '4')
#define ROM_DATA_COPYRIGHT ROM_TABLE_CODE('C', 'R')
#define ROM_FUNC_CLZ32 ROM_TABLE_CODE('L', '3')
#define ROM_FUNC_MEMCPY ROM_TABLE_CODE('M', 'C')
#define ROM_FUNC_MEMSET ROM_TABLE_CODE('M', 'S')
#define ROM_FUNC_POPCOUNT32 ROM_TABLE_CODE('P', '3')
#define ROM_FUNC_REVERSE32 ROM_TABLE_CODE('R', '3')
#define ROM_FUNC_MEMSET4 ROM_TABLE_CODE('S', '4')
#define ROM_FUNC_CTZ32 ROM_TABLE_CODE('T', '3')
#define ROM_FUNC_RESET_USB_BOOT ROM_TABLE_CODE('U', 'B')
#endif
#if !PICO_RP2040 || PICO_COMBINED_DOCS
// RP2350 only
#define ROM_FUNC_PICK_AB_PARTITION ROM_TABLE_CODE('A', 'B')
#define ROM_FUNC_CHAIN_IMAGE ROM_TABLE_CODE('C', 'I')
#define ROM_FUNC_EXPLICIT_BUY ROM_TABLE_CODE('E', 'B')
#define ROM_FUNC_FLASH_RUNTIME_TO_STORAGE_ADDR ROM_TABLE_CODE('F', 'A')
#define ROM_DATA_FLASH_DEVINFO16_PTR ROM_TABLE_CODE('F', 'D')
#define ROM_FUNC_FLASH_OP ROM_TABLE_CODE('F', 'O')
#define ROM_FUNC_GET_B_PARTITION ROM_TABLE_CODE('G', 'B')
#define ROM_FUNC_GET_PARTITION_TABLE_INFO ROM_TABLE_CODE('G', 'P')
#define ROM_FUNC_GET_SYS_INFO ROM_TABLE_CODE('G', 'S')
#define ROM_FUNC_GET_UF2_TARGET_PARTITION ROM_TABLE_CODE('G', 'U')
#define ROM_FUNC_LOAD_PARTITION_TABLE ROM_TABLE_CODE('L', 'P')
#define ROM_FUNC_OTP_ACCESS ROM_TABLE_CODE('O', 'A')
#define ROM_DATA_PARTITION_TABLE_PTR ROM_TABLE_CODE('P', 'T')
#define ROM_FUNC_FLASH_RESET_ADDRESS_TRANS ROM_TABLE_CODE('R', 'A')
#define ROM_FUNC_REBOOT ROM_TABLE_CODE('R', 'B')
#define ROM_FUNC_SET_ROM_CALLBACK ROM_TABLE_CODE('R', 'C')
#define ROM_FUNC_SECURE_CALL ROM_TABLE_CODE('S', 'C')
#define ROM_FUNC_SET_NS_API_PERMISSION ROM_TABLE_CODE('S', 'P')
#define ROM_FUNC_BOOTROM_STATE_RESET ROM_TABLE_CODE('S', 'R')
#define ROM_FUNC_SET_BOOTROM_STACK ROM_TABLE_CODE('S', 'S')
#define ROM_DATA_SAVED_XIP_SETUP_FUNC_PTR ROM_TABLE_CODE('X', 'F')
#define ROM_FUNC_FLASH_SELECT_XIP_READ_MODE ROM_TABLE_CODE('X', 'M')
#define ROM_FUNC_VALIDATE_NS_BUFFER ROM_TABLE_CODE('V', 'B')
#endif
// these form a bit set
#define BOOTROM_STATE_RESET_CURRENT_CORE 0x01
#define BOOTROM_STATE_RESET_OTHER_CORE 0x02
#define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04 // reset any global state (e.g. permissions)
// partition level stuff is returned first (note PT_INFO flags is only 16 bits)
// 3 words: pt_count, unpartitioned_perm_loc, unpartioned_perm_flags
#define PT_INFO_PT_INFO 0x0001
#define PT_INFO_SINGLE_PARTITION 0x8000 // marker to just include a single partition in the results)
// then in order per partition selected
// 2 words: unpartitioned_perm_loc, unpartioned_perm_flags
#define PT_INFO_PARTITION_LOCATION_AND_FLAGS 0x0010
// 2 words: id lsb first
#define PT_INFO_PARTITION_ID 0x0020
// n+1 words: n, family_id...
#define PT_INFO_PARTITION_FAMILY_IDS 0x0040
// (n+3)/4 words... bytes are: n (len), c0, c1, ... cn-1 padded to word boundary with zeroes
#define PT_INFO_PARTITION_NAME 0x0080
// items are returned in order
// 3 words package_id, device_id, wafer_id
#define SYS_INFO_CHIP_INFO 0x0001
// 1 word: chip specific critical bits
#define SYS_INFO_CRITICAL 0x0002
// 1 word: bytes: cpu_type, supported_cpu_type_bitfield
#define SYS_INFO_CPU_INFO 0x0004
// 1 word: same as FLASH_DEVINFO row in OTP
#define SYS_INFO_FLASH_DEV_INFO 0x0008
// 4 words
#define SYS_INFO_BOOT_RANDOM 0x0010
// 2 words lsb first
#define SYS_INFO_NONCE 0x0020
// 4 words boot_info, boot_diagnostic, boot_param0, boot_param1
#define SYS_INFO_BOOT_INFO 0x0040
#define BOOTROM_NS_API_get_sys_info 0
#define BOOTROM_NS_API_checked_flash_op 1
#define BOOTROM_NS_API_flash_runtime_to_storage_addr 2
#define BOOTROM_NS_API_get_partition_table_info 3
#define BOOTROM_NS_API_secure_call 4
#define BOOTROM_NS_API_otp_access 5
#define BOOTROM_NS_API_reboot 6
#define BOOTROM_NS_API_get_b_partition 7
#define BOOTROM_NS_API_COUNT 8
#ifndef __ASSEMBLER__
typedef struct {
uint32_t permissions_and_location;
uint32_t permissions_and_flags;
} resident_partition_t;
static_assert(sizeof(resident_partition_t) == 8, "");
#define OTP_CMD_ROW_BITS 0x0000ffffu
#define OTP_CMD_ROW_LSB 0u
#define OTP_CMD_WRITE_BITS 0x00010000u
#define OTP_CMD_ECC_BITS 0x00020000u
typedef struct otp_cmd {
uint32_t flags;
} otp_cmd_t;
typedef enum {
BOOTROM_XIP_MODE_03H_SERIAL = 0,
BOOTROM_XIP_MODE_0BH_SERIAL,
BOOTROM_XIP_MODE_BBH_DUAL,
BOOTROM_XIP_MODE_EBH_QUAD,
BOOTROM_XIP_MODE_N_MODES
} bootrom_xip_mode_t;
// The checked flash API wraps the low-level flash routines from generic_flash, adding bounds
// checking, permission checking against the resident partition table, and simple address
// translation. The low-level API deals with flash offsets (i.e. distance from the start of the
// first flash device, measured in bytes) but the checked flash API accepts one of two types of
// address:
//
// - Flash runtime addresses: the address of some flash-resident data or code in the currently
// running image. The flash addresses your binary is "linked at" by the linker.
// - Flash storage addresses: a flash offset, plus the address base where QSPI hardware is first
// mapped on the system bus (XIP_BASE constant from addressmap.h)
//
// These addresses are one and the same *if* the currently running program is stored at the
// beginning of flash. They are different if the start of your image has been "rolled" by the flash
// boot path to make it appear at the address it was linked at even though it is stored at a
// different location in flash, which is necessary when you have A/B images for example.
//
// The address translation between flash runtime and flash storage addresses is configured in
// hardware by the QMI_ATRANSx registers, and this API assumes those registers contain a valid
// address mapping which it can use to translate runtime to storage addresses.
typedef struct cflash_flags {
uint32_t flags;
} cflash_flags_t;
// Bits which are permitted to be set in a flags variable -- any other bits being set is an error
#define CFLASH_FLAGS_BITS 0x00070301u
// Used to tell checked flash API which space a given address belongs to
#define CFLASH_ASPACE_BITS 0x00000001u
#define CFLASH_ASPACE_LSB 0u
#define CFLASH_ASPACE_VALUE_STORAGE 0u
#define CFLASH_ASPACE_VALUE_RUNTIME 1u
// Used to tell checked flash APIs the effective security level of a flash access (may be forced to
// one of these values for the NonSecure-exported version of this API)
#define CFLASH_SECLEVEL_BITS 0x00000300u
#define CFLASH_SECLEVEL_LSB 8u
// Zero is not a valid security level:
#define CFLASH_SECLEVEL_VALUE_SECURE 1u
#define CFLASH_SECLEVEL_VALUE_NONSECURE 2u
#define CFLASH_SECLEVEL_VALUE_BOOTLOADER 3u
#define CFLASH_OP_BITS 0x00070000u
#define CFLASH_OP_LSB 16u
// Erase size_bytes bytes of flash, starting at address addr. Both addr and size_bytes must be a
// multiple of 4096 bytes (one flash sector).
#define CFLASH_OP_VALUE_ERASE 0u
// Program size_bytes bytes of flash, starting at address addr. Both addr and size_bytes must be a
// multiple of 256 bytes (one flash page).
#define CFLASH_OP_VALUE_PROGRAM 1u
// Read size_bytes bytes of flash, starting at address addr. There are no alignment restrictions on
// addr or size_bytes.
#define CFLASH_OP_VALUE_READ 2u
#define CFLASH_OP_MAX 2u
#endif
#endif

26
lib/rp2040/pico/platform.h → lib/pico-sdk/pico/platform.h
View File

@ -4,10 +4,11 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _PICO_PLATFORM_H_
#define _PICO_PLATFORM_H_
#ifndef _PICO_PLATFORM_H
#define _PICO_PLATFORM_H
#include "hardware/platform_defs.h"
#include <stdint.h>
#include <stddef.h>
#ifdef __unix__
@ -20,15 +21,21 @@
extern "C" {
#endif
#define __not_in_flash(grup)
#define __not_in_flash(group)
#define __not_in_flash_func(func) func
#define __no_inline_not_in_flash_func(func)
#define __no_inline_not_in_flash_func(func) func
#define __in_flash(group)
#define __scratch_x(group)
#define __scratch_y(group)
#define __packed_aligned
#ifndef _MSC_VER
#define __packed __attribute__((packed))
#define __packed_aligned __packed __attribute((aligned))
#else
// MSVC requires #pragma pack which isn't compatible with a single attribute style define
#define __packed
#define __packed_aligned
#endif
#define __time_critical_func(x) x
#define __after_data(group)
@ -60,6 +67,9 @@ extern void tight_loop_contents();
#define PICO_WEAK_FUNCTION_DEF(x) _Pragma(__STRING(weak x))
#define PICO_WEAK_FUNCTION_IMPL_NAME(x) x
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#else
#ifndef __noreturn
#define __noreturn __declspec(noreturn)
@ -133,6 +143,12 @@ static inline int32_t __mul_instruction(int32_t a,int32_t b)
static inline void __compiler_memory_barrier(void) {
}
uint get_core_num();
static inline uint __get_current_exception(void) {
return 0;
}
#ifdef __cplusplus
}
#endif

146
lib/pico-sdk/rp2040/boot_stage2/BUILD.bazel Normal file
View File

@ -0,0 +1,146 @@
# Always include these libraries through //src/rp2_common:*!
# This ensures that you'll get the right headers for the MCU you're targeting.
load("@bazel_skylib//rules:copy_file.bzl", "copy_file")
load("@bazel_skylib//rules:run_binary.bzl", "run_binary")
load("@rules_python//python:defs.bzl", "py_binary")
load("//bazel/toolchain:objcopy.bzl", "objcopy_to_bin")
load("//bazel/util:multiple_choice_flag.bzl", "declare_flag_choices", "flag_choice")
load("//bazel/util:transition.bzl", "rp2040_bootloader_binary")
# There's a lot of implementation details in here that shouldn't be considered
# stable, so allowlist visibility to just the public-facing pieces.
package(default_visibility = ["//visibility:private"])
# Known choices for boot2:
BOOT2_CHOICES = [
"boot2_at25sf128a",
"boot2_generic_03h",
"boot2_is25lp080",
"boot2_usb_blinky",
"boot2_w25q080",
"boot2_w25x10cl",
"compile_time_choice",
]
BOOT2_CHOICE_FILES = [c + ".S" for c in BOOT2_CHOICES]
BOOT2_CHOICE_FILE_MAP = {c: [c + ".S"] for c in BOOT2_CHOICES}
BOOT2_CHOICE_DEFINE_MAP = {c: ['PICO_BUILD_BOOT_STAGE2_NAME=\\"{}\\"'.format(c)] for c in BOOT2_CHOICES}
# Define shouldn't be set for compile_time_choice.
BOOT2_CHOICE_DEFINE_MAP["compile_time_choice"] = []
cc_library(
name = "config",
hdrs = [
"asminclude/boot2_helpers/exit_from_boot2.S",
"asminclude/boot2_helpers/read_flash_sreg.S",
"asminclude/boot2_helpers/wait_ssi_ready.S",
"include/boot_stage2/config.h",
] + BOOT2_CHOICE_FILES,
defines = select(flag_choice(
"//bazel/config:PICO_DEFAULT_BOOT_STAGE2",
":__pkg__",
BOOT2_CHOICE_DEFINE_MAP,
)),
includes = [
"asminclude",
"include",
],
target_compatible_with = ["//bazel/constraint:rp2040"],
visibility = ["//visibility:public"],
)
# Creates a config_setting for each known boot2 option with the name:
# PICO_DEFAULT_BOOT_STAGE2_[choice]
declare_flag_choices(
"//bazel/config:PICO_DEFAULT_BOOT_STAGE2",
BOOT2_CHOICES,
)
filegroup(
name = "build_selected_boot2",
srcs = select(flag_choice(
"//bazel/config:PICO_DEFAULT_BOOT_STAGE2",
":__pkg__",
BOOT2_CHOICE_FILE_MAP,
)),
visibility = ["//src/rp2_common:__pkg__"],
)
cc_binary(
name = "boot_stage2_elf_actual",
srcs = ["//bazel/config:PICO_DEFAULT_BOOT_STAGE2_FILE"],
copts = ["-fPIC"],
# Incompatible with section garbage collection.
features = ["-gc_sections"],
linkopts = [
"-Wl,--no-gc-sections",
"-nostartfiles",
"-Wl,--entry=_stage2_boot",
"-T$(location boot_stage2.ld)",
],
# this does nothing if someone passes --custom_malloc, so the
# rp2040_bootloader_binary transition forcibly clobbers --custom_malloc.
malloc = "//bazel:empty_cc_lib",
tags = ["manual"], # Only build as an explicit dependency.
target_compatible_with = ["//bazel/constraint:rp2040"],
deps = [
"boot_stage2.ld",
":config",
"//src/common/pico_base_headers",
"//src/rp2_common:pico_platform_internal",
],
)
# Always build the bootloader with the bootloader-specific platform.
rp2040_bootloader_binary(
name = "boot_stage2_elf",
src = "boot_stage2_elf_actual",
)
objcopy_to_bin(
name = "boot_stage2_bin",
src = ":boot_stage2_elf",
out = "boot_stage2.bin",
target_compatible_with = ["//bazel/constraint:rp2040"],
)
# WORKAROUND: Python rules always require a .py extension.
copy_file(
name = "copy_tool_to_py",
src = "pad_checksum",
out = "pad_checksum_tool.py",
target_compatible_with = ["//bazel/constraint:host"],
)
py_binary(
name = "pad_checksum_tool",
srcs = ["pad_checksum_tool.py"],
target_compatible_with = ["//bazel/constraint:host"],
)
run_binary(
name = "boot_stage2_padded",
srcs = [":boot_stage2_bin"],
outs = ["boot_stage2.S"],
args = [
"-s 0xffffffff",
"$(location boot_stage2_bin)",
"$(location boot_stage2.S)",
],
target_compatible_with = ["//bazel/constraint:rp2040"],
tool = ":pad_checksum_tool",
)
cc_library(
name = "boot_stage2",
srcs = [":boot_stage2_padded"],
target_compatible_with = ["//bazel/constraint:rp2040"],
visibility = ["//src/rp2_common:__pkg__"],
# This isn't referenced as a symbol, so alwayslink is required to ensure
# it doesn't get dropped before the linker script can find it.
alwayslink = True,
)

24
lib/rp2040/boot_stage2/CMakeLists.txt → lib/pico-sdk/rp2040/boot_stage2/CMakeLists.txt
View File

@ -1,10 +1,10 @@
# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default boot stage 2 file to use unless overridden by pico_set_boot_stage2 on the TARGET; this setting is useful when explicitly setting the default build from a per board CMake file, group=build
# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the file is src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, default=compile_time_choice, group=build
# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2_FILE, Default boot stage 2 file to use unless overridden by pico_set_boot_stage2 on the TARGET; this setting is useful when explicitly setting the default build from a per board CMake file, type=string, group=build
# PICO_CMAKE_CONFIG: PICO_DEFAULT_BOOT_STAGE2, Simpler alternative to specifying PICO_DEFAULT_BOOT_STAGE2_FILE where the latter is set to src/rp2_common/boot_stage2/{PICO_DEFAULT_BOOT_STAGE2}.S, type=string, default=compile_time_choice, group=build
if (DEFINED ENV{PICO_DEFAULT_BOOT_STAGE2_FILE})
set(PICO_DEFAULT_BOOT_STAGE2_FILE $ENV{PICO_DEFAULT_BOOT_STAGE2_FILE})
message("Using PICO_DEFAULT_BOOT_STAGE2_FILE from environment ('${PICO_DEFAULT_BOOT_STAGE2_FILE}')")
elif (PICO_DEFAULT_BOOT_STAGE2_FILE)
elseif (PICO_DEFAULT_BOOT_STAGE2_FILE)
# explicitly set, so cache it
set(PICO_DEFAULT_BOOT_STAGE2_FILE "${PICO_DEFAULT_BOOT_STAGE2_FILE}" CACHE STRING "boot stage 2 source file" FORCE)
endif()
@ -25,12 +25,13 @@ endif()
if (NOT EXISTS ${PICO_DEFAULT_BOOT_STAGE2_FILE})
message(FATAL_ERROR "Specified boot stage 2 source '${PICO_DEFAULT_BOOT_STAGE2_FILE}' does not exist.")
endif()
pico_register_common_scope_var(PICO_DEFAULT_BOOT_STAGE2_FILE)
# needed by function below
set(PICO_BOOT_STAGE2_DIR "${CMAKE_CURRENT_LIST_DIR}" CACHE INTERNAL "")
add_library(boot_stage2_headers INTERFACE)
target_include_directories(boot_stage2_headers INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
target_include_directories(boot_stage2_headers SYSTEM INTERFACE ${CMAKE_CURRENT_LIST_DIR}/include)
# by convention the first source file name without extension is used for the binary info name
function(pico_define_boot_stage2 NAME SOURCES)
@ -39,9 +40,9 @@ function(pico_define_boot_stage2 NAME SOURCES)
)
# todo bit of an abstraction failure - revisit for Clang support anyway
if (CMAKE_C_COMPILER_ID STREQUAL "Clang")
if (PICO_C_COMPILER_IS_CLANG)
target_link_options(${NAME} PRIVATE "-nostdlib")
else ()
elseif (PICO_C_COMPILER_IS_GNU)
target_link_options(${NAME} PRIVATE "--specs=nosys.specs")
target_link_options(${NAME} PRIVATE "-nostartfiles")
endif ()
@ -62,12 +63,13 @@ function(pico_define_boot_stage2 NAME SOURCES)
find_package (Python3 REQUIRED COMPONENTS Interpreter)
add_custom_target(${NAME}_bin DEPENDS ${ORIGINAL_BIN})
add_custom_command(OUTPUT ${ORIGINAL_BIN} DEPENDS ${NAME} COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${NAME}> ${ORIGINAL_BIN})
add_custom_command(OUTPUT ${ORIGINAL_BIN} DEPENDS ${NAME} COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${NAME}> ${ORIGINAL_BIN}
VERBATIM)
add_custom_target(${NAME}_padded_checksummed_asm DEPENDS ${PADDED_CHECKSUMMED_ASM})
add_custom_command(OUTPUT ${PADDED_CHECKSUMMED_ASM} DEPENDS ${ORIGINAL_BIN}
COMMAND ${Python3_EXECUTABLE} ${PICO_BOOT_STAGE2_DIR}/pad_checksum -s 0xffffffff ${ORIGINAL_BIN} ${PADDED_CHECKSUMMED_ASM}
)
VERBATIM)
add_library(${NAME}_library INTERFACE)
add_dependencies(${NAME}_library ${NAME}_padded_checksummed_asm)
@ -98,3 +100,9 @@ endmacro()
pico_define_boot_stage2(bs2_default ${PICO_DEFAULT_BOOT_STAGE2_FILE})
# Create a new boot stage 2 target using the default implementation for the current build (PICO_BOARD derived)
function(pico_clone_default_boot_stage2 NAME)
pico_define_boot_stage2(${NAME} ${PICO_DEFAULT_BOOT_STAGE2_FILE})
endfunction()
pico_promote_common_scope_vars()

0
lib/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S → lib/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/exit_from_boot2.S
View File

0
lib/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S → lib/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/read_flash_sreg.S
View File

0
lib/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S → lib/pico-sdk/rp2040/boot_stage2/asminclude/boot2_helpers/wait_ssi_ready.S
View File

21
lib/rp2040/boot_stage2/boot2_at25sf128a.S → lib/pico-sdk/rp2040/boot_stage2/boot2_at25sf128a.S
View File

@ -86,21 +86,18 @@
// Start of 2nd Stage Boot Code
// ----------------------------------------------------------------------------
.syntax unified
.cpu cortex-m0plus
.thumb
pico_default_asm_setup
.section .text
// The exit point is passed in lr. If entered from bootrom, this will be the
// flash address immediately following this second stage (0x10000100).
// Otherwise it will be a return address -- second stage being called as a
// function by user code, after copying out of XIP region. r3 holds SSI base,
// r0...2 used as temporaries. Other GPRs not used.
.global _stage2_boot
.type _stage2_boot,%function
.thumb_func
_stage2_boot:
// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
// to continue into the binary via the vector table at 0x10000100.
//
// lr will be non-zero on entry if this code has been copied into RAM by user code and called
// from there, and the boot_stage2 should just return normally.
//
// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
regular_func _stage2_boot
push {lr}
// Set pad configuration:

27
lib/rp2040/boot_stage2/boot2_generic_03h.S → lib/pico-sdk/rp2040/boot_stage2/boot2_generic_03h.S
View File

@ -16,10 +16,12 @@
// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
// ----------------------------------------------------------------------------
//#include "pico/asm_helper.S"
#include "pico/asm_helper.S"
#include "hardware/regs/addressmap.h"
#include "hardware/regs/ssi.h"
pico_default_asm_setup
// ----------------------------------------------------------------------------
// Config section
// ----------------------------------------------------------------------------
@ -53,25 +55,26 @@
// Start of 2nd Stage Boot Code
// ----------------------------------------------------------------------------
.cpu cortex-m0
.thumb
.section .text
.global _stage2_boot
.type _stage2_boot,%function
.thumb_func
_stage2_boot:
// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
// to continue into the binary via the vector table at 0x10000100.
//
// lr will be non-zero on entry if this code has been copied into RAM by user code and called
// from there, and the boot_stage2 should just return normally.
//
// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
regular_func _stage2_boot
push {lr}
ldr r3, =XIP_SSI_BASE // Use as base address where possible
// Disable SSI to allow further config
mov r1, #0
movs r1, #0
str r1, [r3, #SSI_SSIENR_OFFSET]
// Set baud rate
mov r1, #PICO_FLASH_SPI_CLKDIV
movs r1, #PICO_FLASH_SPI_CLKDIV
str r1, [r3, #SSI_BAUDR_OFFSET]
ldr r1, =(CTRLR0_XIP)
@ -82,11 +85,11 @@ _stage2_boot:
str r1, [r0]
// NDF=0 (single 32b read)
mov r1, #0x0
movs r1, #0x0
str r1, [r3, #SSI_CTRLR1_OFFSET]
// Re-enable SSI
mov r1, #1
movs r1, #1
str r1, [r3, #SSI_SSIENR_OFFSET]
// We are now in XIP mode. Any bus accesses to the XIP address window will be

44
lib/rp2040/boot_stage2/boot2_is25lp080.S → lib/pico-sdk/rp2040/boot_stage2/boot2_is25lp080.S
View File

@ -80,25 +80,27 @@
// Start of 2nd Stage Boot Code
// ----------------------------------------------------------------------------
.cpu cortex-m0
.thumb
pico_default_asm_setup
.section .text
.global _stage2_boot
.type _stage2_boot,%function
.thumb_func
_stage2_boot:
// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
// to continue into the binary via the vector table at 0x10000100.
//
// lr will be non-zero on entry if this code has been copied into RAM by user code and called
// from there, and the boot_stage2 should just return normally.
//
// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
regular_func _stage2_boot
push {lr}
ldr r3, =XIP_SSI_BASE // Use as base address where possible
// Disable SSI to allow further config
mov r1, #0
movs r1, #0
str r1, [r3, #SSI_SSIENR_OFFSET]
// Set baud rate
mov r1, #PICO_FLASH_SPI_CLKDIV
movs r1, #PICO_FLASH_SPI_CLKDIV
str r1, [r3, #SSI_BAUDR_OFFSET]
// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
@ -113,7 +115,7 @@ program_sregs:
str r1, [r3, #SSI_CTRLR0_OFFSET]
// Enable SSI and select slave 0
mov r1, #1
movs r1, #1
str r1, [r3, #SSI_SSIENR_OFFSET]
// Check whether SR needs updating
@ -124,7 +126,7 @@ program_sregs:
beq skip_sreg_programming
// Send write enable command
mov r1, #CMD_WRITE_ENABLE
movs r1, #CMD_WRITE_ENABLE
str r1, [r3, #SSI_DR0_OFFSET]
// Poll for completion and discard RX
@ -132,9 +134,9 @@ program_sregs:
ldr r1, [r3, #SSI_DR0_OFFSET]
// Send status write command followed by data bytes
mov r1, #CMD_WRITE_STATUS
movs r1, #CMD_WRITE_STATUS
str r1, [r3, #SSI_DR0_OFFSET]
mov r0, #0
movs r0, #0
str r2, [r3, #SSI_DR0_OFFSET]
bl wait_ssi_ready
@ -145,7 +147,7 @@ program_sregs:
1:
ldr r0, =CMD_READ_STATUS
bl read_flash_sreg
mov r1, #1
movs r1, #1
tst r0, r1
bne 1b
@ -157,7 +159,7 @@ skip_sreg_programming:
// bl wait_ssi_ready
// Disable SSI again so that it can be reconfigured
mov r1, #0
movs r1, #0
str r1, [r3, #SSI_SSIENR_OFFSET]
#endif
@ -182,7 +184,7 @@ dummy_read:
ldr r1, =(CTRLR0_ENTER_XIP)
str r1, [r3, #SSI_CTRLR0_OFFSET]
mov r1, #0x0 // NDF=0 (single 32b read)
movs r1, #0x0 // NDF=0 (single 32b read)
str r1, [r3, #SSI_CTRLR1_OFFSET]
#define SPI_CTRLR0_ENTER_XIP \
@ -197,12 +199,12 @@ dummy_read:
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
str r1, [r0]
mov r1, #1 // Re-enable SSI
movs r1, #1 // Re-enable SSI
str r1, [r3, #SSI_SSIENR_OFFSET]
mov r1, #CMD_READ
movs r1, #CMD_READ
str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
mov r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
// Poll for completion
@ -218,7 +220,7 @@ dummy_read:
// to APM mode and generate a 28-bit address phase with the extra nibble set
// to 4'b0000).
mov r1, #0
movs r1, #0
str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
// Note that the INST_L field is used to select what XIP data gets pushed into
@ -240,7 +242,7 @@ configure_ssi:
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
str r1, [r0]
mov r1, #1
movs r1, #1
str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
// We are now in XIP mode, with all transactions using Dual I/O and only

15
lib/rp2040/boot_stage2/boot2_usb_blinky.S → lib/pico-sdk/rp2040/boot_stage2/boot2_usb_blinky.S
View File

@ -4,6 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "pico/asm_helper.S"
// Stub second stage which calls into USB bootcode, with parameters.
// USB boot takes two parameters:
// - A GPIO mask for activity LED -- if mask is 0, don't touch GPIOs at all
@ -19,17 +21,12 @@
#define ACTIVITY_LED 0
#define BOOT_MODE USB_BOOT_MSD_AND_PICOBOOT
.cpu cortex-m0
.thumb
pico_default_asm_setup
.section .text
.global _stage2_boot
.type _stage2_boot,%function
.thumb_func
_stage2_boot:
mov r7, #0x14 // Pointer to _well_known pointer table in ROM
regular_func _stage2_boot
movs r7, #0x14 // Pointer to _well_known pointer table in ROM
ldrh r0, [r7, #0] // Offset 0 is 16 bit pointer to function table
ldrh r7, [r7, #4] // Offset 4 is 16 bit pointer to table lookup routine
ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot
@ -39,7 +36,7 @@ _stage2_boot:
mov r7, r0
ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use
mov r1, #BOOT_MODE
movs r1, #BOOT_MODE
blx r7
dead:

23
lib/rp2040/boot_stage2/boot2_w25q080.S → lib/pico-sdk/rp2040/boot_stage2/boot2_w25q080.S
View File

@ -26,7 +26,7 @@
// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
// ----------------------------------------------------------------------------
//#include "pico/asm_helper.S"
#include "pico/asm_helper.S"
#include "hardware/regs/addressmap.h"
#include "hardware/regs/ssi.h"
#include "hardware/regs/pads_qspi.h"
@ -86,21 +86,18 @@
// Start of 2nd Stage Boot Code
// ----------------------------------------------------------------------------
.syntax unified
.cpu cortex-m0plus
.thumb
pico_default_asm_setup
.section .text
// The exit point is passed in lr. If entered from bootrom, this will be the
// flash address immediately following this second stage (0x10000100).
// Otherwise it will be a return address -- second stage being called as a
// function by user code, after copying out of XIP region. r3 holds SSI base,
// r0...2 used as temporaries. Other GPRs not used.
.global _stage2_boot
.type _stage2_boot,%function
.thumb_func
_stage2_boot:
// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
// to continue into the binary via the vector table at 0x10000100.
//
// lr will be non-zero on entry if this code has been copied into RAM by user code and called
// from there, and the boot_stage2 should just return normally.
//
// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
regular_func _stage2_boot
push {lr}
// Set pad configuration:

37
lib/rp2040/boot_stage2/boot2_w25x10cl.S → lib/pico-sdk/rp2040/boot_stage2/boot2_w25x10cl.S
View File

@ -40,6 +40,8 @@
#define PICO_FLASH_SPI_CLKDIV 4
#endif
pico_default_asm_setup
// ----------------------------------------------------------------------------
// The "System Control Block" is a set of internal Cortex-M0+ control registers
// that are memory mapped and accessed like any other H/W register. They have
@ -69,31 +71,30 @@
// Start of 2nd Stage Boot Code
// ----------------------------------------------------------------------------
.cpu cortex-m0
.thumb
.org 0
.section .text
// This code will get copied to 0x20000000 and then executed
.global _stage2_boot
.type _stage2_boot,%function
.thumb_func
_stage2_boot:
// lr will be zero on entry if entered from the bootrom, and the boot_stage2 is expected
// to continue into the binary via the vector table at 0x10000100.
//
// lr will be non-zero on entry if this code has been copied into RAM by user code and called
// from there, and the boot_stage2 should just return normally.
//
// r3 holds SSI base, r0...2 used as temporaries. Other GPRs not used.
regular_func _stage2_boot
push {lr}
ldr r3, =XIP_SSI_BASE // Use as base address where possible
// We are primarily interested in setting up Flash for DSPI XIP w/ continuous read
mov r1, #0
movs r1, #0
str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config
// The Boot ROM sets a very conservative SPI clock frequency to be sure it can
// read the initial 256 bytes from any device. Here we can be more aggressive.
mov r1, #PICO_FLASH_SPI_CLKDIV
movs r1, #PICO_FLASH_SPI_CLKDIV
str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock
// First we need to send the initial command to get us in to Fast Read Dual I/O
@ -116,7 +117,7 @@ _stage2_boot:
ldr r1, =(CTRLR0_ENTER_XIP)
str r1, [r3, #SSI_CTRLR0_OFFSET]
mov r1, #0x0 // NDF=0 (single 32b read)
movs r1, #0x0 // NDF=0 (single 32b read)
str r1, [r3, #SSI_CTRLR1_OFFSET]
#define SPI_CTRLR0_ENTER_XIP \
@ -131,18 +132,18 @@ _stage2_boot:
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
str r1, [r0]
mov r1, #1 // Re-enable SSI
movs r1, #1 // Re-enable SSI
str r1, [r3, #SSI_SSIENR_OFFSET]
mov r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO // 8b command = 0xBB
movs r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO // 8b command = 0xBB
str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
mov r1, #0x0000002 // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10
movs r1, #0x0000002 // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10
str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
// Now we wait for the read transaction to complete by monitoring the SSI
// status register and checking for the "RX FIFO Not Empty" flag to assert.
mov r1, #SSI_SR_RFNE_BITS
movs r1, #SSI_SR_RFNE_BITS
00:
ldr r0, [r3, #SSI_SR_OFFSET] // Read status register
tst r0, r1 // RFNE status flag set?
@ -158,7 +159,7 @@ _stage2_boot:
// to APM mode and generate a 28-bit address phase with the extra nibble set
// to 4'b0000).
mov r1, #0
movs r1, #0
str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
// Note that the INST_L field is used to select what XIP data gets pushed into
@ -180,7 +181,7 @@ _stage2_boot:
ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
str r1, [r0]
mov r1, #1
movs r1, #1
str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
// We are now in XIP mode, with all transactions using Dual I/O and only

0
lib/rp2040/boot_stage2/boot_stage2.ld → lib/pico-sdk/rp2040/boot_stage2/boot_stage2.ld
View File

0
lib/rp2040/boot_stage2/compile_time_choice.S → lib/pico-sdk/rp2040/boot_stage2/compile_time_choice.S
View File

0
lib/rp2040/boot_stage2/doc.h → lib/pico-sdk/rp2040/boot_stage2/doc.h
View File

13
lib/rp2040/boot_stage2/include/boot_stage2/config.h → lib/pico-sdk/rp2040/boot_stage2/include/boot_stage2/config.h
View File

@ -4,12 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _BOOT_STAGE2_CONFIG_H_
#define _BOOT_STAGE2_CONFIG_H_
#ifndef _BOOT_STAGE2_CONFIG_H
#define _BOOT_STAGE2_CONFIG_H
// NOTE THIS HEADER IS INCLUDED FROM ASSEMBLY
#include "pico/config.h"
#include "pico.h"
// PICO_CONFIG: PICO_BUILD_BOOT_STAGE2_NAME, The name of the boot stage 2 if selected by the build, group=boot_stage2
#ifdef PICO_BUILD_BOOT_STAGE2_NAME
@ -85,10 +85,7 @@
#error no boot stage 2 is defined by PICO_BOOT_STAGE2_CHOOSE_ macro
#endif
// we can't include cdefs in assembly, so define our own, but avoid conflict with real ones for c inclusion
#define _PICO__STRING(x) #x
#define _PICO__XSTRING(x) _PICO__STRING(x)
#define _PICO__CONCAT1(x, y) x ## y
#define PICO_BOOT_STAGE2_NAME _PICO__XSTRING(_BOOT_STAGE2)
#define PICO_BOOT_STAGE2_ASM _PICO__XSTRING(_PICO__CONCAT1(_BOOT_STAGE2,.S))
#define PICO_BOOT_STAGE2_NAME __PICO_XSTRING(_BOOT_STAGE2)
#define PICO_BOOT_STAGE2_ASM __PICO_XSTRING(__PICO_CONCAT1(_BOOT_STAGE2,.S))
#endif
#endif

2
lib/rp2040/boot_stage2/pad_checksum → lib/pico-sdk/rp2040/boot_stage2/pad_checksum
View File

@ -31,7 +31,7 @@ try:
except:
sys.exit("Could not open input file '{}'".format(args.ifile))
if len(idata) >= args.pad - 4:
if len(idata) > args.pad - 4:
sys.exit("Input file size ({} bytes) too large for final size ({} bytes)".format(len(idata), args.pad))
idata_padded = idata + bytes(args.pad - 4 - len(idata))

2675
lib/pico-sdk/rp2040/cmsis_include/RP2040.h Normal file
View File

File diff suppressed because it is too large Load Diff

0
lib/rp2040/cmsis_include/system_RP2040.h → lib/pico-sdk/rp2040/cmsis_include/system_RP2040.h
View File

119
lib/pico-sdk/rp2040/hardware/platform_defs.h Normal file
View File

@ -0,0 +1,119 @@
/*
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_PLATFORM_DEFS_H
#define _HARDWARE_PLATFORM_DEFS_H
// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__
#ifndef _u
#ifdef __ASSEMBLER__
#define _u(x) x
#else
#define _u(x) x ## u
#endif
#endif
#define NUM_CORES _u(2)
#define NUM_DMA_CHANNELS _u(12)
#define NUM_DMA_TIMERS _u(4)
#define NUM_DMA_IRQS _u(2)
#define NUM_IRQS _u(32)
#define NUM_USER_IRQS _u(6)
#define NUM_PIOS _u(2)
#define NUM_PIO_STATE_MACHINES _u(4)
#define NUM_PIO_IRQS _u(2)
#define NUM_PWM_SLICES _u(8)
#define NUM_PWM_IRQS _u(1)
#define NUM_SPIN_LOCKS _u(32)
#define NUM_UARTS _u(2)
#define NUM_I2CS _u(2)
#define NUM_SPIS _u(2)
#define NUM_GENERIC_TIMERS _u(1)
#define NUM_ALARMS _u(4)
#define ADC_BASE_PIN _u(26)
#define NUM_ADC_CHANNELS _u(5)
#define NUM_RESETS _u(24)
#define NUM_BANK0_GPIOS _u(30)
#define NUM_QSPI_GPIOS _u(6)
#define PIO_INSTRUCTION_COUNT _u(32)
#define USBCTRL_DPRAM_SIZE _u(4096)
#define HAS_SIO_DIVIDER 1
#define HAS_RP2040_RTC 1
// PICO_CONFIG: XOSC_HZ, Crystal oscillator frequency in Hz, type=int, default=12000000, advanced=true, group=hardware_base
// NOTE: The system and USB clocks are generated from the frequency using two PLLs.
// If you override this define, or SYS_CLK_HZ/USB_CLK_HZ below, you will *also* need to add your own adjusted PLL set-up defines to
// override the defaults which live in src/rp2_common/hardware_clocks/include/hardware/clocks.h
// Please see the comments there about calculating the new PLL setting values.
#ifndef XOSC_HZ
#ifdef XOSC_KHZ
#define XOSC_HZ ((XOSC_KHZ) * _u(1000))
#elif defined(XOSC_MHZ)
#define XOSC_HZ ((XOSC_MHZ) * _u(1000000))
#else
#define XOSC_HZ _u(12000000)
#endif
#endif
// PICO_CONFIG: SYS_CLK_HZ, System operating frequency in Hz, type=int, default=125000000, advanced=true, group=hardware_base
#ifndef SYS_CLK_HZ
#ifdef SYS_CLK_KHZ
#define SYS_CLK_HZ ((SYS_CLK_KHZ) * _u(1000))
#elif defined(SYS_CLK_MHZ)
#define SYS_CLK_HZ ((SYS_CLK_MHZ) * _u(1000000))
#else
#define SYS_CLK_HZ _u(125000000)
#endif
#endif
// PICO_CONFIG: USB_CLK_HZ, USB clock frequency. Must be 48MHz for the USB interface to operate correctly, type=int, default=48000000, advanced=true, group=hardware_base
#ifndef USB_CLK_HZ
#ifdef USB_CLK_KHZ
#define USB_CLK_HZ ((USB_CLK_KHZ) * _u(1000))
#elif defined(USB_CLK_MHZ)
#define USB_CLK_HZ ((USB_CLK_MHZ) * _u(1000000))
#else
#define USB_CLK_HZ _u(48000000)
#endif
#endif
// For backwards compatibility define XOSC_KHZ if the frequency is indeed an integer number of Khz.
#if defined(XOSC_HZ) && !defined(XOSC_KHZ) && (XOSC_HZ % 1000 == 0)
#define XOSC_KHZ (XOSC_HZ / 1000)
#endif
// For backwards compatibility define XOSC_MHZ if the frequency is indeed an integer number of Mhz.
#if defined(XOSC_KHZ) && !defined(XOSC_MHZ) && (XOSC_KHZ % 1000 == 0)
#define XOSC_MHZ (XOSC_KHZ / 1000)
#endif
// For backwards compatibility define SYS_CLK_KHZ if the frequency is indeed an integer number of Khz.
#if defined(SYS_CLK_HZ) && !defined(SYS_CLK_KHZ) && (SYS_CLK_HZ % 1000 == 0)
#define SYS_CLK_KHZ (SYS_CLK_HZ / 1000)
#endif
// For backwards compatibility define SYS_CLK_MHZ if the frequency is indeed an integer number of Mhz.
#if defined(SYS_CLK_KHZ) && !defined(SYS_CLK_MHZ) && (SYS_CLK_KHZ % 1000 == 0)
#define SYS_CLK_MHZ (SYS_CLK_KHZ / 1000)
#endif
// For backwards compatibility define USB_CLK_KHZ if the frequency is indeed an integer number of Khz.
#if defined(USB_CLK_HZ) && !defined(USB_CLK_KHZ) && (USB_CLK_HZ % 1000 == 0)
#define USB_CLK_KHZ (USB_CLK_HZ / 1000)
#endif
// For backwards compatibility define USB_CLK_MHZ if the frequency is indeed an integer number of Mhz.
#if defined(USB_CLK_KHZ) && !defined(USB_CLK_MHZ) && (USB_CLK_KHZ % 1000 == 0)
#define USB_CLK_MHZ (USB_CLK_KHZ / 1000)
#endif
#define FIRST_USER_IRQ (NUM_IRQS - NUM_USER_IRQS)
#define VTABLE_FIRST_IRQ 16
#endif

18
lib/rp2040/hardware/regs/adc.h → lib/pico-sdk/rp2040/hardware/regs/adc.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,8 +11,8 @@
// Bus type : apb
// Description : Control and data interface to SAR ADC
// =============================================================================
#ifndef HARDWARE_REGS_ADC_DEFINED
#define HARDWARE_REGS_ADC_DEFINED
#ifndef _HARDWARE_REGS_ADC_H
#define _HARDWARE_REGS_ADC_H
// =============================================================================
// Register : ADC_CS
// Description : ADC Control and Status
@ -25,8 +27,8 @@
// round-robin fashion.
// The first channel to be sampled will be the one currently
// indicated by AINSEL.
// AINSEL will be updated after each conversion with the
// newly-selected channel.
// AINSEL will be updated after each conversion with the newly-
// selected channel.
#define ADC_CS_RROBIN_RESET _u(0x00)
#define ADC_CS_RROBIN_BITS _u(0x001f0000)
#define ADC_CS_RROBIN_MSB _u(20)
@ -153,7 +155,6 @@
#define ADC_FCS_UNDER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_FULL
// Description : None
#define ADC_FCS_FULL_RESET _u(0x0)
#define ADC_FCS_FULL_BITS _u(0x00000200)
#define ADC_FCS_FULL_MSB _u(9)
@ -161,7 +162,6 @@
#define ADC_FCS_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EMPTY
// Description : None
#define ADC_FCS_EMPTY_RESET _u(0x0)
#define ADC_FCS_EMPTY_BITS _u(0x00000100)
#define ADC_FCS_EMPTY_MSB _u(8)
@ -218,7 +218,6 @@
#define ADC_FIFO_ERR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_VAL
// Description : None
#define ADC_FIFO_VAL_RESET "-"
#define ADC_FIFO_VAL_BITS _u(0x00000fff)
#define ADC_FIFO_VAL_MSB _u(11)
@ -311,4 +310,5 @@
#define ADC_INTS_FIFO_LSB _u(0)
#define ADC_INTS_FIFO_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_ADC_DEFINED
#endif // _HARDWARE_REGS_ADC_H

23
lib/rp2040/hardware/regs/addressmap.h → lib/pico-sdk/rp2040/hardware/regs/addressmap.h
View File

@ -1,18 +1,24 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _ADDRESSMAP_H_
#define _ADDRESSMAP_H_
#ifndef _ADDRESSMAP_H
#define _ADDRESSMAP_H
/**
* \file rp2040/addressmap.h
*/
#include "hardware/platform_defs.h"
// Register address offsets for atomic RMW aliases
#define REG_ALIAS_RW_BITS (0x0u << 12u)
#define REG_ALIAS_XOR_BITS (0x1u << 12u)
#define REG_ALIAS_SET_BITS (0x2u << 12u)
#define REG_ALIAS_CLR_BITS (0x3u << 12u)
#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12))
#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12))
#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12))
#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12))
#define ROM_BASE _u(0x00000000)
#define XIP_BASE _u(0x10000000)
@ -71,4 +77,5 @@
#define SIO_BASE _u(0xd0000000)
#define PPB_BASE _u(0xe0000000)
#endif // _ADDRESSMAP_H_
#endif // _ADDRESSMAP_H

11
lib/rp2040/hardware/regs/busctrl.h → lib/pico-sdk/rp2040/hardware/regs/busctrl.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,8 +12,8 @@
// Description : Register block for busfabric control signals and performance
// counters
// =============================================================================
#ifndef HARDWARE_REGS_BUSCTRL_DEFINED
#define HARDWARE_REGS_BUSCTRL_DEFINED
#ifndef _HARDWARE_REGS_BUSCTRL_H
#define _HARDWARE_REGS_BUSCTRL_H
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY
// Description : Set the priority of each master for bus arbitration.
@ -321,4 +323,5 @@
#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13)
// =============================================================================
#endif // HARDWARE_REGS_BUSCTRL_DEFINED
#endif // _HARDWARE_REGS_BUSCTRL_H

169
lib/rp2040/hardware/regs/clocks.h → lib/pico-sdk/rp2040/hardware/regs/clocks.h
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File diff suppressed because it is too large Load Diff

512
lib/rp2040/hardware/regs/dma.h → lib/pico-sdk/rp2040/hardware/regs/dma.h
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File diff suppressed because it is too large Load Diff

117
lib/pico-sdk/rp2040/hardware/regs/dreq.h Normal file
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@ -0,0 +1,117 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _DREQ_H
#define _DREQ_H
/**
* \file rp2040/dreq.h
*/
#ifdef __ASSEMBLER__
#define DREQ_PIO0_TX0 0
#define DREQ_PIO0_TX1 1
#define DREQ_PIO0_TX2 2
#define DREQ_PIO0_TX3 3
#define DREQ_PIO0_RX0 4
#define DREQ_PIO0_RX1 5
#define DREQ_PIO0_RX2 6
#define DREQ_PIO0_RX3 7
#define DREQ_PIO1_TX0 8
#define DREQ_PIO1_TX1 9
#define DREQ_PIO1_TX2 10
#define DREQ_PIO1_TX3 11
#define DREQ_PIO1_RX0 12
#define DREQ_PIO1_RX1 13
#define DREQ_PIO1_RX2 14
#define DREQ_PIO1_RX3 15
#define DREQ_SPI0_TX 16
#define DREQ_SPI0_RX 17
#define DREQ_SPI1_TX 18
#define DREQ_SPI1_RX 19
#define DREQ_UART0_TX 20
#define DREQ_UART0_RX 21
#define DREQ_UART1_TX 22
#define DREQ_UART1_RX 23
#define DREQ_PWM_WRAP0 24
#define DREQ_PWM_WRAP1 25
#define DREQ_PWM_WRAP2 26
#define DREQ_PWM_WRAP3 27
#define DREQ_PWM_WRAP4 28
#define DREQ_PWM_WRAP5 29
#define DREQ_PWM_WRAP6 30
#define DREQ_PWM_WRAP7 31
#define DREQ_I2C0_TX 32
#define DREQ_I2C0_RX 33
#define DREQ_I2C1_TX 34
#define DREQ_I2C1_RX 35
#define DREQ_ADC 36
#define DREQ_XIP_STREAM 37
#define DREQ_XIP_SSITX 38
#define DREQ_XIP_SSIRX 39
#define DREQ_DMA_TIMER0 59
#define DREQ_DMA_TIMER1 60
#define DREQ_DMA_TIMER2 61
#define DREQ_DMA_TIMER3 62
#define DREQ_FORCE 63
#else
/**
* \brief DREQ numbers for DMA pacing on RP2040 (used as typedef \ref dreq_num_t)
* \ingroup hardware_dma
*/
typedef enum dreq_num_rp2040 {
DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ
DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ
DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ
DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ
DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ
DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ
DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ
DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ
DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ
DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ
DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ
DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ
DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ
DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ
DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ
DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ
DREQ_SPI0_TX = 16, ///< Select SPI0's TX FIFO as DREQ
DREQ_SPI0_RX = 17, ///< Select SPI0's RX FIFO as DREQ
DREQ_SPI1_TX = 18, ///< Select SPI1's TX FIFO as DREQ
DREQ_SPI1_RX = 19, ///< Select SPI1's RX FIFO as DREQ
DREQ_UART0_TX = 20, ///< Select UART0's TX FIFO as DREQ
DREQ_UART0_RX = 21, ///< Select UART0's RX FIFO as DREQ
DREQ_UART1_TX = 22, ///< Select UART1's TX FIFO as DREQ
DREQ_UART1_RX = 23, ///< Select UART1's RX FIFO as DREQ
DREQ_PWM_WRAP0 = 24, ///< Select PWM Counter 0's Wrap Value as DREQ
DREQ_PWM_WRAP1 = 25, ///< Select PWM Counter 1's Wrap Value as DREQ
DREQ_PWM_WRAP2 = 26, ///< Select PWM Counter 2's Wrap Value as DREQ
DREQ_PWM_WRAP3 = 27, ///< Select PWM Counter 3's Wrap Value as DREQ
DREQ_PWM_WRAP4 = 28, ///< Select PWM Counter 4's Wrap Value as DREQ
DREQ_PWM_WRAP5 = 29, ///< Select PWM Counter 5's Wrap Value as DREQ
DREQ_PWM_WRAP6 = 30, ///< Select PWM Counter 6's Wrap Value as DREQ
DREQ_PWM_WRAP7 = 31, ///< Select PWM Counter 7's Wrap Value as DREQ
DREQ_I2C0_TX = 32, ///< Select I2C0's TX FIFO as DREQ
DREQ_I2C0_RX = 33, ///< Select I2C0's RX FIFO as DREQ
DREQ_I2C1_TX = 34, ///< Select I2C1's TX FIFO as DREQ
DREQ_I2C1_RX = 35, ///< Select I2C1's RX FIFO as DREQ
DREQ_ADC = 36, ///< Select the ADC as DREQ
DREQ_XIP_STREAM = 37, ///< Select the XIP Streaming FIFO as DREQ
DREQ_XIP_SSITX = 38, ///< Select the XIP SSI TX FIFO as DREQ
DREQ_XIP_SSIRX = 39, ///< Select the XIP SSI RX FIFO as DREQ
DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ
DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ
DREQ_FORCE = 63, ///< Select FORCE as DREQ
DREQ_COUNT
} dreq_num_t;
#endif
#endif // _DREQ_H

177
lib/rp2040/hardware/regs/i2c.h → lib/pico-sdk/rp2040/hardware/regs/i2c.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -8,9 +10,83 @@
// Version : 1
// Bus type : apb
// Description : DW_apb_i2c address block
//
// List of configuration constants for the Synopsys I2C
// hardware (you may see references to these in I2C register
// header; these are *fixed* values, set at hardware design
// time):
//
// IC_ULTRA_FAST_MODE ................ 0x0
// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
// IC_UFM_SCL_LOW_COUNT .............. 0x0008
// IC_UFM_SCL_HIGH_COUNT ............. 0x0006
// IC_TX_TL .......................... 0x0
// IC_TX_CMD_BLOCK ................... 0x1
// IC_HAS_DMA ........................ 0x1
// IC_HAS_ASYNC_FIFO ................. 0x0
// IC_SMBUS_ARP ...................... 0x0
// IC_FIRST_DATA_BYTE_STATUS ......... 0x1
// IC_INTR_IO ........................ 0x1
// IC_MASTER_MODE .................... 0x1
// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
// IC_INTR_POL ....................... 0x1
// IC_OPTIONAL_SAR ................... 0x0
// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
// IC_DEFAULT_SLAVE_ADDR ............. 0x055
// IC_DEFAULT_HS_SPKLEN .............. 0x1
// IC_FS_SCL_HIGH_COUNT .............. 0x0006
// IC_HS_SCL_LOW_COUNT ............... 0x0008
// IC_DEVICE_ID_VALUE ................ 0x0
// IC_10BITADDR_MASTER ............... 0x0
// IC_CLK_FREQ_OPTIMIZATION .......... 0x0
// IC_DEFAULT_FS_SPKLEN .............. 0x7
// IC_ADD_ENCODED_PARAMS ............. 0x0
// IC_DEFAULT_SDA_HOLD ............... 0x000001
// IC_DEFAULT_SDA_SETUP .............. 0x64
// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
// IC_CLOCK_PERIOD ................... 100
// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
// IC_RESTART_EN ..................... 0x1
// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
// IC_BUS_CLEAR_FEATURE .............. 0x0
// IC_CAP_LOADING .................... 100
// IC_FS_SCL_LOW_COUNT ............... 0x000d
// APB_DATA_WIDTH .................... 32
// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
// IC_SLV_DATA_NACK_ONLY ............. 0x1
// IC_10BITADDR_SLAVE ................ 0x0
// IC_CLK_TYPE ....................... 0x0
// IC_SMBUS_UDID_MSB ................. 0x0
// IC_SMBUS_SUSPEND_ALERT ............ 0x0
// IC_HS_SCL_HIGH_COUNT .............. 0x0006
// IC_SLV_RESTART_DET_EN ............. 0x1
// IC_SMBUS .......................... 0x0
// IC_OPTIONAL_SAR_DEFAULT ........... 0x0
// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
// IC_USE_COUNTS ..................... 0x0
// IC_RX_BUFFER_DEPTH ................ 16
// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
// IC_RX_FULL_HLD_BUS_EN ............. 0x1
// IC_SLAVE_DISABLE .................. 0x1
// IC_RX_TL .......................... 0x0
// IC_DEVICE_ID ...................... 0x0
// IC_HC_COUNT_VALUES ................ 0x0
// I2C_DYNAMIC_TAR_UPDATE ............ 0
// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
// IC_HS_MASTER_CODE ................. 0x1
// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
// IC_SS_SCL_HIGH_COUNT .............. 0x0028
// IC_SS_SCL_LOW_COUNT ............... 0x002f
// IC_MAX_SPEED_MODE ................. 0x2
// IC_STAT_FOR_CLK_STRETCH ........... 0x0
// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
// IC_DEFAULT_UFM_SPKLEN ............. 0x1
// IC_TX_BUFFER_DEPTH ................ 16
// =============================================================================
#ifndef HARDWARE_REGS_I2C_DEFINED
#define HARDWARE_REGS_I2C_DEFINED
#ifndef _HARDWARE_REGS_I2C_H
#define _HARDWARE_REGS_I2C_H
// =============================================================================
// Register : I2C_IC_CON
// Description : I2C Control Register. This register can be written only when
@ -112,14 +188,14 @@
// conditions; however, RESTART conditions are used in several
// DW_apb_i2c operations. When RESTART is disabled, the master is
// prohibited from performing the following functions: - Sending a
// START BYTE - Performing any high-speed mode operation -
// High-speed mode operation - Performing direction changes in
// combined format mode - Performing a read operation with a
// 10-bit address By replacing RESTART condition followed by a
// STOP and a subsequent START condition, split operations are
// broken down into multiple DW_apb_i2c transfers. If the above
// operations are performed, it will result in setting bit 6
// (TX_ABRT) of the IC_RAW_INTR_STAT register.
// START BYTE - Performing any high-speed mode operation - High-
// speed mode operation - Performing direction changes in combined
// format mode - Performing a read operation with a 10-bit address
// By replacing RESTART condition followed by a STOP and a
// subsequent START condition, split operations are broken down
// into multiple DW_apb_i2c transfers. If the above operations are
// performed, it will result in setting bit 6 (TX_ABRT) of the
// IC_RAW_INTR_STAT register.
//
// Reset value: ENABLED
// 0x0 -> Master restart disabled
@ -233,10 +309,8 @@
// GC_OR_START and use IC_TAR normally - 1: perform special I2C
// command as specified in Device_ID or GC_OR_START bit Reset
// value: 0x0
// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE
// transmission
// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE
// transmission
// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE transmission
// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE transmission
#define I2C_IC_TAR_SPECIAL_RESET _u(0x0)
#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800)
#define I2C_IC_TAR_SPECIAL_MSB _u(11)
@ -552,9 +626,9 @@
// Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT
// Description : This register must be set before any I2C bus transaction can
// take place to ensure proper I/O timing. This register sets the
// SCL clock low period count for fast speed. It is used in
// high-speed mode to send the Master Code and START BYTE or
// General CALL. For more information, refer to 'IC_CLK Frequency
// SCL clock low period count for fast speed. It is used in high-
// speed mode to send the Master Code and START BYTE or General
// CALL. For more information, refer to 'IC_CLK Frequency
// Configuration'.
//
// This register goes away and becomes read-only returning 0s if
@ -1886,8 +1960,7 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Slave-Transmitter
// 0x0 -> Slave trying to transmit to remote master in read mode-
// scenario not present
// 0x0 -> Slave trying to transmit to remote master in read mode- scenario not present
// 0x1 -> Slave trying to transmit to remote master in read mode
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000)
@ -1910,8 +1983,7 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Slave-Transmitter
// 0x0 -> Slave lost arbitration to remote master- scenario not
// present
// 0x0 -> Slave lost arbitration to remote master- scenario not present
// 0x1 -> Slave lost arbitration to remote master
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000)
@ -1929,10 +2001,8 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Slave-Transmitter
// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read
// command- scenario not present
// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read
// command
// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read command- scenario not present
// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read command
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13)
@ -1949,8 +2019,7 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario
// not present
// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario not present
// 0x1 -> Master or Slave-Transmitter lost arbitration
#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000)
@ -1967,8 +2036,7 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
// 0x0 -> User initiating master operation when MASTER disabled-
// scenario not present
// 0x0 -> User initiating master operation when MASTER disabled- scenario not present
// 0x1 -> User initiating master operation when MASTER disabled
#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800)
@ -1986,10 +2054,8 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Receiver
// 0x0 -> Master not trying to read in 10Bit addressing mode when
// RESTART disabled
// 0x1 -> Master trying to read in 10Bit addressing mode when
// RESTART disabled
// 0x0 -> Master not trying to read in 10Bit addressing mode when RESTART disabled
// 0x1 -> Master trying to read in 10Bit addressing mode when RESTART disabled
#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10)
@ -2014,8 +2080,7 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master
// 0x0 -> User trying to send START byte when RESTART disabled-
// scenario not present
// 0x0 -> User trying to send START byte when RESTART disabled- scenario not present
// 0x1 -> User trying to send START byte when RESTART disabled
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200)
@ -2033,10 +2098,8 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
// 0x0 -> User trying to switch Master to HS mode when RESTART
// disabled- scenario not present
// 0x1 -> User trying to switch Master to HS mode when RESTART
// disabled
// 0x0 -> User trying to switch Master to HS mode when RESTART disabled- scenario not present
// 0x1 -> User trying to switch Master to HS mode when RESTART disabled
#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8)
@ -2125,8 +2188,7 @@
// Reset value: 0x0
//
// Role of DW_apb_i2c: Master-Transmitter
// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario
// not present
// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario not present
// 0x1 -> Transmitted data not ACKed by addressed slave
#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008)
@ -2180,8 +2242,7 @@
//
// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
// 0x0 -> This abort is not generated
// 0x1 -> This abort is generated because of NOACK for 7-bit
// address
// 0x1 -> This abort is generated because of NOACK for 7-bit address
#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001)
#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0)
@ -2389,14 +2450,14 @@
#define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST
// Description : Slave Received Data Lost. This bit indicates if a
// Slave-Receiver operation has been aborted with at least one
// data byte received from an I2C transfer due to the setting bit
// 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is
// deemed to have been actively engaged in an aborted I2C transfer
// (with matching address) and the data phase of the I2C transfer
// has been entered, even though a data byte has been responded
// with a NACK.
// Description : Slave Received Data Lost. This bit indicates if a Slave-
// Receiver operation has been aborted with at least one data byte
// received from an I2C transfer due to the setting bit 0 of
// IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to
// have been actively engaged in an aborted I2C transfer (with
// matching address) and the data phase of the I2C transfer has
// been entered, even though a data byte has been responded with a
// NACK.
//
// Note: If the remote I2C master terminates the transfer with a
// STOP condition before the DW_apb_i2c has a chance to NACK a
@ -2404,8 +2465,8 @@
// also set to 1.
//
// When read as 0, DW_apb_i2c is deemed to have been disabled
// without being actively involved in the data phase of a
// Slave-Receiver transfer.
// without being actively involved in the data phase of a Slave-
// Receiver transfer.
//
// Note: The CPU can safely read this bit when IC_EN (bit 0) is
// read as 0.
@ -2428,8 +2489,8 @@
// 1 to 0. This bit is set when the CPU writes a 0 to the
// IC_ENABLE register while:
//
// (a) DW_apb_i2c is receiving the address byte of the
// Slave-Transmitter operation from a remote master;
// (a) DW_apb_i2c is receiving the address byte of the Slave-
// Transmitter operation from a remote master;
//
// OR,
//
@ -2613,7 +2674,6 @@
#define I2C_IC_COMP_VERSION_RESET _u(0x3230312a)
// -----------------------------------------------------------------------------
// Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION
// Description : None
#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a)
#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff)
#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31)
@ -2636,4 +2696,5 @@
#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0)
#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_I2C_DEFINED
#endif // _HARDWARE_REGS_I2C_H

106
lib/pico-sdk/rp2040/hardware/regs/intctrl.h Normal file
View File

@ -0,0 +1,106 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _INTCTRL_H
#define _INTCTRL_H
/**
* \file rp2040/intctrl.h
*/
#ifdef __ASSEMBLER__
#define TIMER_IRQ_0 0
#define TIMER_IRQ_1 1
#define TIMER_IRQ_2 2
#define TIMER_IRQ_3 3
#define PWM_IRQ_WRAP 4
#define USBCTRL_IRQ 5
#define XIP_IRQ 6
#define PIO0_IRQ_0 7
#define PIO0_IRQ_1 8
#define PIO1_IRQ_0 9
#define PIO1_IRQ_1 10
#define DMA_IRQ_0 11
#define DMA_IRQ_1 12
#define IO_IRQ_BANK0 13
#define IO_IRQ_QSPI 14
#define SIO_IRQ_PROC0 15
#define SIO_IRQ_PROC1 16
#define CLOCKS_IRQ 17
#define SPI0_IRQ 18
#define SPI1_IRQ 19
#define UART0_IRQ 20
#define UART1_IRQ 21
#define ADC_IRQ_FIFO 22
#define I2C0_IRQ 23
#define I2C1_IRQ 24
#define RTC_IRQ 25
#else
/**
* \brief Interrupt numbers on RP2040 (used as typedef \ref irq_num_t)
* \ingroup hardware_irq
*/
typedef enum irq_num_rp2040 {
TIMER_IRQ_0 = 0, ///< Select TIMER's IRQ 0 output
TIMER_IRQ_1 = 1, ///< Select TIMER's IRQ 1 output
TIMER_IRQ_2 = 2, ///< Select TIMER's IRQ 2 output
TIMER_IRQ_3 = 3, ///< Select TIMER's IRQ 3 output
PWM_IRQ_WRAP = 4, ///< Select PWM's IRQ_WRAP output
USBCTRL_IRQ = 5, ///< Select USBCTRL's IRQ output
XIP_IRQ = 6, ///< Select XIP's IRQ output
PIO0_IRQ_0 = 7, ///< Select PIO0's IRQ 0 output
PIO0_IRQ_1 = 8, ///< Select PIO0's IRQ 1 output
PIO1_IRQ_0 = 9, ///< Select PIO1's IRQ 0 output
PIO1_IRQ_1 = 10, ///< Select PIO1's IRQ 1 output
DMA_IRQ_0 = 11, ///< Select DMA's IRQ 0 output
DMA_IRQ_1 = 12, ///< Select DMA's IRQ 1 output
IO_IRQ_BANK0 = 13, ///< Select IO_BANK0's IRQ output
IO_IRQ_QSPI = 14, ///< Select IO_QSPI's IRQ output
SIO_IRQ_PROC0 = 15, ///< Select SIO_PROC0's IRQ output
SIO_IRQ_PROC1 = 16, ///< Select SIO_PROC1's IRQ output
CLOCKS_IRQ = 17, ///< Select CLOCKS's IRQ output
SPI0_IRQ = 18, ///< Select SPI0's IRQ output
SPI1_IRQ = 19, ///< Select SPI1's IRQ output
UART0_IRQ = 20, ///< Select UART0's IRQ output
UART1_IRQ = 21, ///< Select UART1's IRQ output
ADC_IRQ_FIFO = 22, ///< Select ADC's IRQ_FIFO output
I2C0_IRQ = 23, ///< Select I2C0's IRQ output
I2C1_IRQ = 24, ///< Select I2C1's IRQ output
RTC_IRQ = 25, ///< Select RTC's IRQ output
IRQ_COUNT
} irq_num_t;
#endif
#define isr_timer_0 isr_irq0
#define isr_timer_1 isr_irq1
#define isr_timer_2 isr_irq2
#define isr_timer_3 isr_irq3
#define isr_pwm_wrap isr_irq4
#define isr_usbctrl isr_irq5
#define isr_xip isr_irq6
#define isr_pio0_0 isr_irq7
#define isr_pio0_1 isr_irq8
#define isr_pio1_0 isr_irq9
#define isr_pio1_1 isr_irq10
#define isr_dma_0 isr_irq11
#define isr_dma_1 isr_irq12
#define isr_io_bank0 isr_irq13
#define isr_io_qspi isr_irq14
#define isr_sio_proc0 isr_irq15
#define isr_sio_proc1 isr_irq16
#define isr_clocks isr_irq17
#define isr_spi0 isr_irq18
#define isr_spi1 isr_irq19
#define isr_uart0 isr_irq20
#define isr_uart1 isr_irq21
#define isr_adc_fifo isr_irq22
#define isr_i2c0 isr_irq23
#define isr_i2c1 isr_irq24
#define isr_rtc isr_irq25
#endif // _INTCTRL_H

1662
lib/rp2040/hardware/regs/io_bank0.h → lib/pico-sdk/rp2040/hardware/regs/io_bank0.h
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File diff suppressed because it is too large Load Diff

342
lib/rp2040/hardware/regs/io_qspi.h → lib/pico-sdk/rp2040/hardware/regs/io_qspi.h
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File diff suppressed because it is too large Load Diff

22
lib/rp2040/hardware/regs/m0plus.h → lib/pico-sdk/rp2040/hardware/regs/m0plus.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : M0PLUS
// Version : 1
// Bus type : ahbl
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_M0PLUS_DEFINED
#define HARDWARE_REGS_M0PLUS_DEFINED
#ifndef _HARDWARE_REGS_M0PLUS_H
#define _HARDWARE_REGS_M0PLUS_H
// =============================================================================
// Register : M0PLUS_SYST_CSR
// Description : Use the SysTick Control and Status Register to enable the
@ -610,11 +611,11 @@
#define M0PLUS_CPUID_REVISION_ACCESS "RO"
// =============================================================================
// Register : M0PLUS_ICSR
// Description : Use the Interrupt Control State Register to set a pending
// Non-Maskable Interrupt (NMI), set or clear a pending PendSV,
// set or clear a pending SysTick, check for pending exceptions,
// check the vector number of the highest priority pended
// exception, check the vector number of the active exception.
// Description : Use the Interrupt Control State Register to set a pending Non-
// Maskable Interrupt (NMI), set or clear a pending PendSV, set or
// clear a pending SysTick, check for pending exceptions, check
// the vector number of the highest priority pended exception,
// check the vector number of the active exception.
#define M0PLUS_ICSR_OFFSET _u(0x0000ed04)
#define M0PLUS_ICSR_BITS _u(0x9edff1ff)
#define M0PLUS_ICSR_RESET _u(0x00000000)
@ -1146,4 +1147,5 @@
#define M0PLUS_MPU_RASR_ENABLE_LSB _u(0)
#define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_M0PLUS_DEFINED
#endif // _HARDWARE_REGS_M0PLUS_H

12
lib/rp2040/hardware/regs/pads_bank0.h → lib/pico-sdk/rp2040/hardware/regs/pads_bank0.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : PADS_BANK0
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_PADS_BANK0_DEFINED
#define HARDWARE_REGS_PADS_BANK0_DEFINED
#ifndef _HARDWARE_REGS_PADS_BANK0_H
#define _HARDWARE_REGS_PADS_BANK0_H
// =============================================================================
// Register : PADS_BANK0_VOLTAGE_SELECT
// Description : Voltage select. Per bank control
@ -2297,4 +2298,5 @@
#define PADS_BANK0_SWD_SLEWFAST_LSB _u(0)
#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PADS_BANK0_DEFINED
#endif // _HARDWARE_REGS_PADS_BANK0_H

12
lib/rp2040/hardware/regs/pads_qspi.h → lib/pico-sdk/rp2040/hardware/regs/pads_qspi.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : PADS_QSPI
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_PADS_QSPI_DEFINED
#define HARDWARE_REGS_PADS_QSPI_DEFINED
#ifndef _HARDWARE_REGS_PADS_QSPI_H
#define _HARDWARE_REGS_PADS_QSPI_H
// =============================================================================
// Register : PADS_QSPI_VOLTAGE_SELECT
// Description : Voltage select. Per bank control
@ -451,4 +452,5 @@
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PADS_QSPI_DEFINED
#endif // _HARDWARE_REGS_PADS_QSPI_H

144
lib/rp2040/hardware/regs/pio.h → lib/pico-sdk/rp2040/hardware/regs/pio.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,8 +11,8 @@
// Bus type : ahbl
// Description : Programmable IO block
// =============================================================================
#ifndef HARDWARE_REGS_PIO_DEFINED
#define HARDWARE_REGS_PIO_DEFINED
#ifndef _HARDWARE_REGS_PIO_H
#define _HARDWARE_REGS_PIO_H
// =============================================================================
// Register : PIO_CTRL
// Description : PIO control register
@ -52,6 +54,9 @@
// counter; the waiting-on-IRQ state; any stalled instruction
// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left
// asserted due to OUT_STICKY.
//
// The program counter, the contents of the output shift register
// and the X/Y scratch registers are not affected.
#define PIO_CTRL_SM_RESTART_RESET _u(0x0)
#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0)
#define PIO_CTRL_SM_RESTART_MSB _u(7)
@ -166,7 +171,6 @@
#define PIO_FLEVEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_RX3
// Description : None
#define PIO_FLEVEL_RX3_RESET _u(0x0)
#define PIO_FLEVEL_RX3_BITS _u(0xf0000000)
#define PIO_FLEVEL_RX3_MSB _u(31)
@ -174,7 +178,6 @@
#define PIO_FLEVEL_RX3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_TX3
// Description : None
#define PIO_FLEVEL_TX3_RESET _u(0x0)
#define PIO_FLEVEL_TX3_BITS _u(0x0f000000)
#define PIO_FLEVEL_TX3_MSB _u(27)
@ -182,7 +185,6 @@
#define PIO_FLEVEL_TX3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_RX2
// Description : None
#define PIO_FLEVEL_RX2_RESET _u(0x0)
#define PIO_FLEVEL_RX2_BITS _u(0x00f00000)
#define PIO_FLEVEL_RX2_MSB _u(23)
@ -190,7 +192,6 @@
#define PIO_FLEVEL_RX2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_TX2
// Description : None
#define PIO_FLEVEL_TX2_RESET _u(0x0)
#define PIO_FLEVEL_TX2_BITS _u(0x000f0000)
#define PIO_FLEVEL_TX2_MSB _u(19)
@ -198,7 +199,6 @@
#define PIO_FLEVEL_TX2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_RX1
// Description : None
#define PIO_FLEVEL_RX1_RESET _u(0x0)
#define PIO_FLEVEL_RX1_BITS _u(0x0000f000)
#define PIO_FLEVEL_RX1_MSB _u(15)
@ -206,7 +206,6 @@
#define PIO_FLEVEL_RX1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_TX1
// Description : None
#define PIO_FLEVEL_TX1_RESET _u(0x0)
#define PIO_FLEVEL_TX1_BITS _u(0x00000f00)
#define PIO_FLEVEL_TX1_MSB _u(11)
@ -214,7 +213,6 @@
#define PIO_FLEVEL_TX1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_RX0
// Description : None
#define PIO_FLEVEL_RX0_RESET _u(0x0)
#define PIO_FLEVEL_RX0_BITS _u(0x000000f0)
#define PIO_FLEVEL_RX0_MSB _u(7)
@ -222,7 +220,6 @@
#define PIO_FLEVEL_RX0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_FLEVEL_TX0
// Description : None
#define PIO_FLEVEL_TX0_RESET _u(0x0)
#define PIO_FLEVEL_TX0_BITS _u(0x0000000f)
#define PIO_FLEVEL_TX0_MSB _u(3)
@ -378,7 +375,8 @@
// =============================================================================
// Register : PIO_DBG_PADOUT
// Description : Read to sample the pad output values PIO is currently driving
// to the GPIOs.
// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most
// significant bits are hardwired to 0.
#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c)
#define PIO_DBG_PADOUT_BITS _u(0xffffffff)
#define PIO_DBG_PADOUT_RESET _u(0x00000000)
@ -388,7 +386,8 @@
// =============================================================================
// Register : PIO_DBG_PADOE
// Description : Read to sample the pad output enables (direction) PIO is
// currently driving to the GPIOs.
// currently driving to the GPIOs. On RP2040 there are 30 GPIOs,
// so the two most significant bits are hardwired to 0.
#define PIO_DBG_PADOE_OFFSET _u(0x00000040)
#define PIO_DBG_PADOE_BITS _u(0xffffffff)
#define PIO_DBG_PADOE_RESET _u(0x00000000)
@ -1021,10 +1020,10 @@
// Description : The lowest-numbered pin that will be affected by a side-set
// operation. The MSBs of an instruction's side-set/delay field
// (up to 5, determined by SIDESET_COUNT) are used for side-set
// data, with the remaining LSBs used for delay. The
// least-significant bit of the side-set portion is the bit
// written to this pin, with more-significant bits written to
// higher-numbered pins.
// data, with the remaining LSBs used for delay. The least-
// significant bit of the side-set portion is the bit written to
// this pin, with more-significant bits written to higher-numbered
// pins.
#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00)
#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14)
@ -1352,10 +1351,10 @@
// Description : The lowest-numbered pin that will be affected by a side-set
// operation. The MSBs of an instruction's side-set/delay field
// (up to 5, determined by SIDESET_COUNT) are used for side-set
// data, with the remaining LSBs used for delay. The
// least-significant bit of the side-set portion is the bit
// written to this pin, with more-significant bits written to
// higher-numbered pins.
// data, with the remaining LSBs used for delay. The least-
// significant bit of the side-set portion is the bit written to
// this pin, with more-significant bits written to higher-numbered
// pins.
#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00)
#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14)
@ -1683,10 +1682,10 @@
// Description : The lowest-numbered pin that will be affected by a side-set
// operation. The MSBs of an instruction's side-set/delay field
// (up to 5, determined by SIDESET_COUNT) are used for side-set
// data, with the remaining LSBs used for delay. The
// least-significant bit of the side-set portion is the bit
// written to this pin, with more-significant bits written to
// higher-numbered pins.
// data, with the remaining LSBs used for delay. The least-
// significant bit of the side-set portion is the bit written to
// this pin, with more-significant bits written to higher-numbered
// pins.
#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00)
#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14)
@ -2014,10 +2013,10 @@
// Description : The lowest-numbered pin that will be affected by a side-set
// operation. The MSBs of an instruction's side-set/delay field
// (up to 5, determined by SIDESET_COUNT) are used for side-set
// data, with the remaining LSBs used for delay. The
// least-significant bit of the side-set portion is the bit
// written to this pin, with more-significant bits written to
// higher-numbered pins.
// data, with the remaining LSBs used for delay. The least-
// significant bit of the side-set portion is the bit written to
// this pin, with more-significant bits written to higher-numbered
// pins.
#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00)
#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14)
@ -2052,7 +2051,6 @@
#define PIO_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM3
// Description : None
#define PIO_INTR_SM3_RESET _u(0x0)
#define PIO_INTR_SM3_BITS _u(0x00000800)
#define PIO_INTR_SM3_MSB _u(11)
@ -2060,7 +2058,6 @@
#define PIO_INTR_SM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM2
// Description : None
#define PIO_INTR_SM2_RESET _u(0x0)
#define PIO_INTR_SM2_BITS _u(0x00000400)
#define PIO_INTR_SM2_MSB _u(10)
@ -2068,7 +2065,6 @@
#define PIO_INTR_SM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM1
// Description : None
#define PIO_INTR_SM1_RESET _u(0x0)
#define PIO_INTR_SM1_BITS _u(0x00000200)
#define PIO_INTR_SM1_MSB _u(9)
@ -2076,7 +2072,6 @@
#define PIO_INTR_SM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM0
// Description : None
#define PIO_INTR_SM0_RESET _u(0x0)
#define PIO_INTR_SM0_BITS _u(0x00000100)
#define PIO_INTR_SM0_MSB _u(8)
@ -2084,7 +2079,6 @@
#define PIO_INTR_SM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM3_TXNFULL
// Description : None
#define PIO_INTR_SM3_TXNFULL_RESET _u(0x0)
#define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080)
#define PIO_INTR_SM3_TXNFULL_MSB _u(7)
@ -2092,7 +2086,6 @@
#define PIO_INTR_SM3_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM2_TXNFULL
// Description : None
#define PIO_INTR_SM2_TXNFULL_RESET _u(0x0)
#define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040)
#define PIO_INTR_SM2_TXNFULL_MSB _u(6)
@ -2100,7 +2093,6 @@
#define PIO_INTR_SM2_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM1_TXNFULL
// Description : None
#define PIO_INTR_SM1_TXNFULL_RESET _u(0x0)
#define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020)
#define PIO_INTR_SM1_TXNFULL_MSB _u(5)
@ -2108,7 +2100,6 @@
#define PIO_INTR_SM1_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM0_TXNFULL
// Description : None
#define PIO_INTR_SM0_TXNFULL_RESET _u(0x0)
#define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010)
#define PIO_INTR_SM0_TXNFULL_MSB _u(4)
@ -2116,7 +2107,6 @@
#define PIO_INTR_SM0_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM3_RXNEMPTY
// Description : None
#define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0)
#define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008)
#define PIO_INTR_SM3_RXNEMPTY_MSB _u(3)
@ -2124,7 +2114,6 @@
#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM2_RXNEMPTY
// Description : None
#define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0)
#define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004)
#define PIO_INTR_SM2_RXNEMPTY_MSB _u(2)
@ -2132,7 +2121,6 @@
#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM1_RXNEMPTY
// Description : None
#define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0)
#define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002)
#define PIO_INTR_SM1_RXNEMPTY_MSB _u(1)
@ -2140,7 +2128,6 @@
#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_INTR_SM0_RXNEMPTY
// Description : None
#define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0)
#define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001)
#define PIO_INTR_SM0_RXNEMPTY_MSB _u(0)
@ -2154,7 +2141,6 @@
#define PIO_IRQ0_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM3
// Description : None
#define PIO_IRQ0_INTE_SM3_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800)
#define PIO_IRQ0_INTE_SM3_MSB _u(11)
@ -2162,7 +2148,6 @@
#define PIO_IRQ0_INTE_SM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM2
// Description : None
#define PIO_IRQ0_INTE_SM2_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400)
#define PIO_IRQ0_INTE_SM2_MSB _u(10)
@ -2170,7 +2155,6 @@
#define PIO_IRQ0_INTE_SM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM1
// Description : None
#define PIO_IRQ0_INTE_SM1_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200)
#define PIO_IRQ0_INTE_SM1_MSB _u(9)
@ -2178,7 +2162,6 @@
#define PIO_IRQ0_INTE_SM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM0
// Description : None
#define PIO_IRQ0_INTE_SM0_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100)
#define PIO_IRQ0_INTE_SM0_MSB _u(8)
@ -2186,7 +2169,6 @@
#define PIO_IRQ0_INTE_SM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM3_TXNFULL
// Description : None
#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080)
#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7)
@ -2194,7 +2176,6 @@
#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM2_TXNFULL
// Description : None
#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040)
#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6)
@ -2202,7 +2183,6 @@
#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM1_TXNFULL
// Description : None
#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020)
#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5)
@ -2210,7 +2190,6 @@
#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM0_TXNFULL
// Description : None
#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010)
#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4)
@ -2218,7 +2197,6 @@
#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM3_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008)
#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3)
@ -2226,7 +2204,6 @@
#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM2_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004)
#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2)
@ -2234,7 +2211,6 @@
#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM1_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002)
#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1)
@ -2242,7 +2218,6 @@
#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTE_SM0_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001)
#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0)
@ -2256,7 +2231,6 @@
#define PIO_IRQ0_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM3
// Description : None
#define PIO_IRQ0_INTF_SM3_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800)
#define PIO_IRQ0_INTF_SM3_MSB _u(11)
@ -2264,7 +2238,6 @@
#define PIO_IRQ0_INTF_SM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM2
// Description : None
#define PIO_IRQ0_INTF_SM2_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400)
#define PIO_IRQ0_INTF_SM2_MSB _u(10)
@ -2272,7 +2245,6 @@
#define PIO_IRQ0_INTF_SM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM1
// Description : None
#define PIO_IRQ0_INTF_SM1_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200)
#define PIO_IRQ0_INTF_SM1_MSB _u(9)
@ -2280,7 +2252,6 @@
#define PIO_IRQ0_INTF_SM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM0
// Description : None
#define PIO_IRQ0_INTF_SM0_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100)
#define PIO_IRQ0_INTF_SM0_MSB _u(8)
@ -2288,7 +2259,6 @@
#define PIO_IRQ0_INTF_SM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM3_TXNFULL
// Description : None
#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080)
#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7)
@ -2296,7 +2266,6 @@
#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM2_TXNFULL
// Description : None
#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040)
#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6)
@ -2304,7 +2273,6 @@
#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM1_TXNFULL
// Description : None
#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020)
#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5)
@ -2312,7 +2280,6 @@
#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM0_TXNFULL
// Description : None
#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010)
#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4)
@ -2320,7 +2287,6 @@
#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM3_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008)
#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3)
@ -2328,7 +2294,6 @@
#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM2_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004)
#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2)
@ -2336,7 +2301,6 @@
#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM1_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002)
#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1)
@ -2344,7 +2308,6 @@
#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTF_SM0_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001)
#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0)
@ -2358,7 +2321,6 @@
#define PIO_IRQ0_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM3
// Description : None
#define PIO_IRQ0_INTS_SM3_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800)
#define PIO_IRQ0_INTS_SM3_MSB _u(11)
@ -2366,7 +2328,6 @@
#define PIO_IRQ0_INTS_SM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM2
// Description : None
#define PIO_IRQ0_INTS_SM2_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400)
#define PIO_IRQ0_INTS_SM2_MSB _u(10)
@ -2374,7 +2335,6 @@
#define PIO_IRQ0_INTS_SM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM1
// Description : None
#define PIO_IRQ0_INTS_SM1_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200)
#define PIO_IRQ0_INTS_SM1_MSB _u(9)
@ -2382,7 +2342,6 @@
#define PIO_IRQ0_INTS_SM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM0
// Description : None
#define PIO_IRQ0_INTS_SM0_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100)
#define PIO_IRQ0_INTS_SM0_MSB _u(8)
@ -2390,7 +2349,6 @@
#define PIO_IRQ0_INTS_SM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM3_TXNFULL
// Description : None
#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080)
#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7)
@ -2398,7 +2356,6 @@
#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM2_TXNFULL
// Description : None
#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040)
#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6)
@ -2406,7 +2363,6 @@
#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM1_TXNFULL
// Description : None
#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020)
#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5)
@ -2414,7 +2370,6 @@
#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM0_TXNFULL
// Description : None
#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010)
#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4)
@ -2422,7 +2377,6 @@
#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM3_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008)
#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3)
@ -2430,7 +2384,6 @@
#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM2_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004)
#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2)
@ -2438,7 +2391,6 @@
#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM1_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002)
#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1)
@ -2446,7 +2398,6 @@
#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ0_INTS_SM0_RXNEMPTY
// Description : None
#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001)
#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0)
@ -2460,7 +2411,6 @@
#define PIO_IRQ1_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM3
// Description : None
#define PIO_IRQ1_INTE_SM3_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800)
#define PIO_IRQ1_INTE_SM3_MSB _u(11)
@ -2468,7 +2418,6 @@
#define PIO_IRQ1_INTE_SM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM2
// Description : None
#define PIO_IRQ1_INTE_SM2_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400)
#define PIO_IRQ1_INTE_SM2_MSB _u(10)
@ -2476,7 +2425,6 @@
#define PIO_IRQ1_INTE_SM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM1
// Description : None
#define PIO_IRQ1_INTE_SM1_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200)
#define PIO_IRQ1_INTE_SM1_MSB _u(9)
@ -2484,7 +2432,6 @@
#define PIO_IRQ1_INTE_SM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM0
// Description : None
#define PIO_IRQ1_INTE_SM0_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100)
#define PIO_IRQ1_INTE_SM0_MSB _u(8)
@ -2492,7 +2439,6 @@
#define PIO_IRQ1_INTE_SM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM3_TXNFULL
// Description : None
#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080)
#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7)
@ -2500,7 +2446,6 @@
#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM2_TXNFULL
// Description : None
#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040)
#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6)
@ -2508,7 +2453,6 @@
#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM1_TXNFULL
// Description : None
#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020)
#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5)
@ -2516,7 +2460,6 @@
#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM0_TXNFULL
// Description : None
#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010)
#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4)
@ -2524,7 +2467,6 @@
#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM3_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008)
#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3)
@ -2532,7 +2474,6 @@
#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM2_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004)
#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2)
@ -2540,7 +2481,6 @@
#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM1_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002)
#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1)
@ -2548,7 +2488,6 @@
#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTE_SM0_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001)
#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0)
@ -2562,7 +2501,6 @@
#define PIO_IRQ1_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM3
// Description : None
#define PIO_IRQ1_INTF_SM3_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800)
#define PIO_IRQ1_INTF_SM3_MSB _u(11)
@ -2570,7 +2508,6 @@
#define PIO_IRQ1_INTF_SM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM2
// Description : None
#define PIO_IRQ1_INTF_SM2_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400)
#define PIO_IRQ1_INTF_SM2_MSB _u(10)
@ -2578,7 +2515,6 @@
#define PIO_IRQ1_INTF_SM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM1
// Description : None
#define PIO_IRQ1_INTF_SM1_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200)
#define PIO_IRQ1_INTF_SM1_MSB _u(9)
@ -2586,7 +2522,6 @@
#define PIO_IRQ1_INTF_SM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM0
// Description : None
#define PIO_IRQ1_INTF_SM0_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100)
#define PIO_IRQ1_INTF_SM0_MSB _u(8)
@ -2594,7 +2529,6 @@
#define PIO_IRQ1_INTF_SM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM3_TXNFULL
// Description : None
#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080)
#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7)
@ -2602,7 +2536,6 @@
#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM2_TXNFULL
// Description : None
#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040)
#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6)
@ -2610,7 +2543,6 @@
#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM1_TXNFULL
// Description : None
#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020)
#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5)
@ -2618,7 +2550,6 @@
#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM0_TXNFULL
// Description : None
#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010)
#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4)
@ -2626,7 +2557,6 @@
#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM3_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008)
#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3)
@ -2634,7 +2564,6 @@
#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM2_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004)
#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2)
@ -2642,7 +2571,6 @@
#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM1_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002)
#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1)
@ -2650,7 +2578,6 @@
#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTF_SM0_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001)
#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0)
@ -2664,7 +2591,6 @@
#define PIO_IRQ1_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM3
// Description : None
#define PIO_IRQ1_INTS_SM3_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800)
#define PIO_IRQ1_INTS_SM3_MSB _u(11)
@ -2672,7 +2598,6 @@
#define PIO_IRQ1_INTS_SM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM2
// Description : None
#define PIO_IRQ1_INTS_SM2_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400)
#define PIO_IRQ1_INTS_SM2_MSB _u(10)
@ -2680,7 +2605,6 @@
#define PIO_IRQ1_INTS_SM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM1
// Description : None
#define PIO_IRQ1_INTS_SM1_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200)
#define PIO_IRQ1_INTS_SM1_MSB _u(9)
@ -2688,7 +2612,6 @@
#define PIO_IRQ1_INTS_SM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM0
// Description : None
#define PIO_IRQ1_INTS_SM0_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100)
#define PIO_IRQ1_INTS_SM0_MSB _u(8)
@ -2696,7 +2619,6 @@
#define PIO_IRQ1_INTS_SM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM3_TXNFULL
// Description : None
#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080)
#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7)
@ -2704,7 +2626,6 @@
#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM2_TXNFULL
// Description : None
#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040)
#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6)
@ -2712,7 +2633,6 @@
#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM1_TXNFULL
// Description : None
#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020)
#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5)
@ -2720,7 +2640,6 @@
#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM0_TXNFULL
// Description : None
#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010)
#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4)
@ -2728,7 +2647,6 @@
#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM3_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008)
#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3)
@ -2736,7 +2654,6 @@
#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM2_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004)
#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2)
@ -2744,7 +2661,6 @@
#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM1_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002)
#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1)
@ -2752,11 +2668,11 @@
#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PIO_IRQ1_INTS_SM0_RXNEMPTY
// Description : None
#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0)
#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001)
#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0)
#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0)
#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_PIO_DEFINED
#endif // _HARDWARE_REGS_PIO_H

14
lib/rp2040/hardware/regs/pll.h → lib/pico-sdk/rp2040/hardware/regs/pll.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,17 +9,16 @@
// Register block : PLL
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_PLL_DEFINED
#define HARDWARE_REGS_PLL_DEFINED
#ifndef _HARDWARE_REGS_PLL_H
#define _HARDWARE_REGS_PLL_H
// =============================================================================
// Register : PLL_CS
// Description : Control and Status
// GENERAL CONSTRAINTS:
// Reference clock frequency min=5MHz, max=800MHz
// Feedback divider min=16, max=320
// VCO frequency min=400MHz, max=1600MHz
// VCO frequency min=750MHz, max=1600MHz
#define PLL_CS_OFFSET _u(0x00000000)
#define PLL_CS_BITS _u(0x8000013f)
#define PLL_CS_RESET _u(0x00000001)
@ -132,4 +133,5 @@
#define PLL_PRIM_POSTDIV2_LSB _u(12)
#define PLL_PRIM_POSTDIV2_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_PLL_DEFINED
#endif // _HARDWARE_REGS_PLL_H

80
lib/rp2040/hardware/regs/psm.h → lib/pico-sdk/rp2040/hardware/regs/psm.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : PSM
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_PSM_DEFINED
#define HARDWARE_REGS_PSM_DEFINED
#ifndef _HARDWARE_REGS_PSM_H
#define _HARDWARE_REGS_PSM_H
// =============================================================================
// Register : PSM_FRCE_ON
// Description : Force block out of reset (i.e. power it on)
@ -19,7 +20,6 @@
#define PSM_FRCE_ON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC1
// Description : None
#define PSM_FRCE_ON_PROC1_RESET _u(0x0)
#define PSM_FRCE_ON_PROC1_BITS _u(0x00010000)
#define PSM_FRCE_ON_PROC1_MSB _u(16)
@ -27,7 +27,6 @@
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC0
// Description : None
#define PSM_FRCE_ON_PROC0_RESET _u(0x0)
#define PSM_FRCE_ON_PROC0_BITS _u(0x00008000)
#define PSM_FRCE_ON_PROC0_MSB _u(15)
@ -35,7 +34,6 @@
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SIO
// Description : None
#define PSM_FRCE_ON_SIO_RESET _u(0x0)
#define PSM_FRCE_ON_SIO_BITS _u(0x00004000)
#define PSM_FRCE_ON_SIO_MSB _u(14)
@ -43,7 +41,6 @@
#define PSM_FRCE_ON_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET
// Description : None
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13)
@ -51,7 +48,6 @@
#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XIP
// Description : None
#define PSM_FRCE_ON_XIP_RESET _u(0x0)
#define PSM_FRCE_ON_XIP_BITS _u(0x00001000)
#define PSM_FRCE_ON_XIP_MSB _u(12)
@ -59,7 +55,6 @@
#define PSM_FRCE_ON_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM5
// Description : None
#define PSM_FRCE_ON_SRAM5_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800)
#define PSM_FRCE_ON_SRAM5_MSB _u(11)
@ -67,7 +62,6 @@
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM4
// Description : None
#define PSM_FRCE_ON_SRAM4_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400)
#define PSM_FRCE_ON_SRAM4_MSB _u(10)
@ -75,7 +69,6 @@
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM3
// Description : None
#define PSM_FRCE_ON_SRAM3_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200)
#define PSM_FRCE_ON_SRAM3_MSB _u(9)
@ -83,7 +76,6 @@
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM2
// Description : None
#define PSM_FRCE_ON_SRAM2_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100)
#define PSM_FRCE_ON_SRAM2_MSB _u(8)
@ -91,7 +83,6 @@
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM1
// Description : None
#define PSM_FRCE_ON_SRAM1_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080)
#define PSM_FRCE_ON_SRAM1_MSB _u(7)
@ -99,7 +90,6 @@
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM0
// Description : None
#define PSM_FRCE_ON_SRAM0_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040)
#define PSM_FRCE_ON_SRAM0_MSB _u(6)
@ -107,7 +97,6 @@
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROM
// Description : None
#define PSM_FRCE_ON_ROM_RESET _u(0x0)
#define PSM_FRCE_ON_ROM_BITS _u(0x00000020)
#define PSM_FRCE_ON_ROM_MSB _u(5)
@ -115,7 +104,6 @@
#define PSM_FRCE_ON_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BUSFABRIC
// Description : None
#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010)
#define PSM_FRCE_ON_BUSFABRIC_MSB _u(4)
@ -123,7 +111,6 @@
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_RESETS
// Description : None
#define PSM_FRCE_ON_RESETS_RESET _u(0x0)
#define PSM_FRCE_ON_RESETS_BITS _u(0x00000008)
#define PSM_FRCE_ON_RESETS_MSB _u(3)
@ -131,7 +118,6 @@
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_CLOCKS
// Description : None
#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004)
#define PSM_FRCE_ON_CLOCKS_MSB _u(2)
@ -139,7 +125,6 @@
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XOSC
// Description : None
#define PSM_FRCE_ON_XOSC_RESET _u(0x0)
#define PSM_FRCE_ON_XOSC_BITS _u(0x00000002)
#define PSM_FRCE_ON_XOSC_MSB _u(1)
@ -147,7 +132,6 @@
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROSC
// Description : None
#define PSM_FRCE_ON_ROSC_RESET _u(0x0)
#define PSM_FRCE_ON_ROSC_BITS _u(0x00000001)
#define PSM_FRCE_ON_ROSC_MSB _u(0)
@ -161,7 +145,6 @@
#define PSM_FRCE_OFF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC1
// Description : None
#define PSM_FRCE_OFF_PROC1_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000)
#define PSM_FRCE_OFF_PROC1_MSB _u(16)
@ -169,7 +152,6 @@
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC0
// Description : None
#define PSM_FRCE_OFF_PROC0_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000)
#define PSM_FRCE_OFF_PROC0_MSB _u(15)
@ -177,7 +159,6 @@
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SIO
// Description : None
#define PSM_FRCE_OFF_SIO_RESET _u(0x0)
#define PSM_FRCE_OFF_SIO_BITS _u(0x00004000)
#define PSM_FRCE_OFF_SIO_MSB _u(14)
@ -185,7 +166,6 @@
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
// Description : None
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13)
@ -193,7 +173,6 @@
#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XIP
// Description : None
#define PSM_FRCE_OFF_XIP_RESET _u(0x0)
#define PSM_FRCE_OFF_XIP_BITS _u(0x00001000)
#define PSM_FRCE_OFF_XIP_MSB _u(12)
@ -201,7 +180,6 @@
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM5
// Description : None
#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800)
#define PSM_FRCE_OFF_SRAM5_MSB _u(11)
@ -209,7 +187,6 @@
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM4
// Description : None
#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400)
#define PSM_FRCE_OFF_SRAM4_MSB _u(10)
@ -217,7 +194,6 @@
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM3
// Description : None
#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200)
#define PSM_FRCE_OFF_SRAM3_MSB _u(9)
@ -225,7 +201,6 @@
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM2
// Description : None
#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100)
#define PSM_FRCE_OFF_SRAM2_MSB _u(8)
@ -233,7 +208,6 @@
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM1
// Description : None
#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080)
#define PSM_FRCE_OFF_SRAM1_MSB _u(7)
@ -241,7 +215,6 @@
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM0
// Description : None
#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040)
#define PSM_FRCE_OFF_SRAM0_MSB _u(6)
@ -249,7 +222,6 @@
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROM
// Description : None
#define PSM_FRCE_OFF_ROM_RESET _u(0x0)
#define PSM_FRCE_OFF_ROM_BITS _u(0x00000020)
#define PSM_FRCE_OFF_ROM_MSB _u(5)
@ -257,7 +229,6 @@
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BUSFABRIC
// Description : None
#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010)
#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4)
@ -265,7 +236,6 @@
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_RESETS
// Description : None
#define PSM_FRCE_OFF_RESETS_RESET _u(0x0)
#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008)
#define PSM_FRCE_OFF_RESETS_MSB _u(3)
@ -273,7 +243,6 @@
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_CLOCKS
// Description : None
#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004)
#define PSM_FRCE_OFF_CLOCKS_MSB _u(2)
@ -281,7 +250,6 @@
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XOSC
// Description : None
#define PSM_FRCE_OFF_XOSC_RESET _u(0x0)
#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002)
#define PSM_FRCE_OFF_XOSC_MSB _u(1)
@ -289,7 +257,6 @@
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROSC
// Description : None
#define PSM_FRCE_OFF_ROSC_RESET _u(0x0)
#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001)
#define PSM_FRCE_OFF_ROSC_MSB _u(0)
@ -304,7 +271,6 @@
#define PSM_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC1
// Description : None
#define PSM_WDSEL_PROC1_RESET _u(0x0)
#define PSM_WDSEL_PROC1_BITS _u(0x00010000)
#define PSM_WDSEL_PROC1_MSB _u(16)
@ -312,7 +278,6 @@
#define PSM_WDSEL_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC0
// Description : None
#define PSM_WDSEL_PROC0_RESET _u(0x0)
#define PSM_WDSEL_PROC0_BITS _u(0x00008000)
#define PSM_WDSEL_PROC0_MSB _u(15)
@ -320,7 +285,6 @@
#define PSM_WDSEL_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SIO
// Description : None
#define PSM_WDSEL_SIO_RESET _u(0x0)
#define PSM_WDSEL_SIO_BITS _u(0x00004000)
#define PSM_WDSEL_SIO_MSB _u(14)
@ -328,7 +292,6 @@
#define PSM_WDSEL_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_VREG_AND_CHIP_RESET
// Description : None
#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13)
@ -336,7 +299,6 @@
#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XIP
// Description : None
#define PSM_WDSEL_XIP_RESET _u(0x0)
#define PSM_WDSEL_XIP_BITS _u(0x00001000)
#define PSM_WDSEL_XIP_MSB _u(12)
@ -344,7 +306,6 @@
#define PSM_WDSEL_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM5
// Description : None
#define PSM_WDSEL_SRAM5_RESET _u(0x0)
#define PSM_WDSEL_SRAM5_BITS _u(0x00000800)
#define PSM_WDSEL_SRAM5_MSB _u(11)
@ -352,7 +313,6 @@
#define PSM_WDSEL_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM4
// Description : None
#define PSM_WDSEL_SRAM4_RESET _u(0x0)
#define PSM_WDSEL_SRAM4_BITS _u(0x00000400)
#define PSM_WDSEL_SRAM4_MSB _u(10)
@ -360,7 +320,6 @@
#define PSM_WDSEL_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM3
// Description : None
#define PSM_WDSEL_SRAM3_RESET _u(0x0)
#define PSM_WDSEL_SRAM3_BITS _u(0x00000200)
#define PSM_WDSEL_SRAM3_MSB _u(9)
@ -368,7 +327,6 @@
#define PSM_WDSEL_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM2
// Description : None
#define PSM_WDSEL_SRAM2_RESET _u(0x0)
#define PSM_WDSEL_SRAM2_BITS _u(0x00000100)
#define PSM_WDSEL_SRAM2_MSB _u(8)
@ -376,7 +334,6 @@
#define PSM_WDSEL_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM1
// Description : None
#define PSM_WDSEL_SRAM1_RESET _u(0x0)
#define PSM_WDSEL_SRAM1_BITS _u(0x00000080)
#define PSM_WDSEL_SRAM1_MSB _u(7)
@ -384,7 +341,6 @@
#define PSM_WDSEL_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM0
// Description : None
#define PSM_WDSEL_SRAM0_RESET _u(0x0)
#define PSM_WDSEL_SRAM0_BITS _u(0x00000040)
#define PSM_WDSEL_SRAM0_MSB _u(6)
@ -392,7 +348,6 @@
#define PSM_WDSEL_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROM
// Description : None
#define PSM_WDSEL_ROM_RESET _u(0x0)
#define PSM_WDSEL_ROM_BITS _u(0x00000020)
#define PSM_WDSEL_ROM_MSB _u(5)
@ -400,7 +355,6 @@
#define PSM_WDSEL_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BUSFABRIC
// Description : None
#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0)
#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010)
#define PSM_WDSEL_BUSFABRIC_MSB _u(4)
@ -408,7 +362,6 @@
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_RESETS
// Description : None
#define PSM_WDSEL_RESETS_RESET _u(0x0)
#define PSM_WDSEL_RESETS_BITS _u(0x00000008)
#define PSM_WDSEL_RESETS_MSB _u(3)
@ -416,7 +369,6 @@
#define PSM_WDSEL_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_CLOCKS
// Description : None
#define PSM_WDSEL_CLOCKS_RESET _u(0x0)
#define PSM_WDSEL_CLOCKS_BITS _u(0x00000004)
#define PSM_WDSEL_CLOCKS_MSB _u(2)
@ -424,7 +376,6 @@
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XOSC
// Description : None
#define PSM_WDSEL_XOSC_RESET _u(0x0)
#define PSM_WDSEL_XOSC_BITS _u(0x00000002)
#define PSM_WDSEL_XOSC_MSB _u(1)
@ -432,7 +383,6 @@
#define PSM_WDSEL_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROSC
// Description : None
#define PSM_WDSEL_ROSC_RESET _u(0x0)
#define PSM_WDSEL_ROSC_BITS _u(0x00000001)
#define PSM_WDSEL_ROSC_MSB _u(0)
@ -446,7 +396,6 @@
#define PSM_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC1
// Description : None
#define PSM_DONE_PROC1_RESET _u(0x0)
#define PSM_DONE_PROC1_BITS _u(0x00010000)
#define PSM_DONE_PROC1_MSB _u(16)
@ -454,7 +403,6 @@
#define PSM_DONE_PROC1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC0
// Description : None
#define PSM_DONE_PROC0_RESET _u(0x0)
#define PSM_DONE_PROC0_BITS _u(0x00008000)
#define PSM_DONE_PROC0_MSB _u(15)
@ -462,7 +410,6 @@
#define PSM_DONE_PROC0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SIO
// Description : None
#define PSM_DONE_SIO_RESET _u(0x0)
#define PSM_DONE_SIO_BITS _u(0x00004000)
#define PSM_DONE_SIO_MSB _u(14)
@ -470,7 +417,6 @@
#define PSM_DONE_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_VREG_AND_CHIP_RESET
// Description : None
#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0)
#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13)
@ -478,7 +424,6 @@
#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XIP
// Description : None
#define PSM_DONE_XIP_RESET _u(0x0)
#define PSM_DONE_XIP_BITS _u(0x00001000)
#define PSM_DONE_XIP_MSB _u(12)
@ -486,7 +431,6 @@
#define PSM_DONE_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM5
// Description : None
#define PSM_DONE_SRAM5_RESET _u(0x0)
#define PSM_DONE_SRAM5_BITS _u(0x00000800)
#define PSM_DONE_SRAM5_MSB _u(11)
@ -494,7 +438,6 @@
#define PSM_DONE_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM4
// Description : None
#define PSM_DONE_SRAM4_RESET _u(0x0)
#define PSM_DONE_SRAM4_BITS _u(0x00000400)
#define PSM_DONE_SRAM4_MSB _u(10)
@ -502,7 +445,6 @@
#define PSM_DONE_SRAM4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM3
// Description : None
#define PSM_DONE_SRAM3_RESET _u(0x0)
#define PSM_DONE_SRAM3_BITS _u(0x00000200)
#define PSM_DONE_SRAM3_MSB _u(9)
@ -510,7 +452,6 @@
#define PSM_DONE_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM2
// Description : None
#define PSM_DONE_SRAM2_RESET _u(0x0)
#define PSM_DONE_SRAM2_BITS _u(0x00000100)
#define PSM_DONE_SRAM2_MSB _u(8)
@ -518,7 +459,6 @@
#define PSM_DONE_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM1
// Description : None
#define PSM_DONE_SRAM1_RESET _u(0x0)
#define PSM_DONE_SRAM1_BITS _u(0x00000080)
#define PSM_DONE_SRAM1_MSB _u(7)
@ -526,7 +466,6 @@
#define PSM_DONE_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM0
// Description : None
#define PSM_DONE_SRAM0_RESET _u(0x0)
#define PSM_DONE_SRAM0_BITS _u(0x00000040)
#define PSM_DONE_SRAM0_MSB _u(6)
@ -534,7 +473,6 @@
#define PSM_DONE_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROM
// Description : None
#define PSM_DONE_ROM_RESET _u(0x0)
#define PSM_DONE_ROM_BITS _u(0x00000020)
#define PSM_DONE_ROM_MSB _u(5)
@ -542,7 +480,6 @@
#define PSM_DONE_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BUSFABRIC
// Description : None
#define PSM_DONE_BUSFABRIC_RESET _u(0x0)
#define PSM_DONE_BUSFABRIC_BITS _u(0x00000010)
#define PSM_DONE_BUSFABRIC_MSB _u(4)
@ -550,7 +487,6 @@
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_RESETS
// Description : None
#define PSM_DONE_RESETS_RESET _u(0x0)
#define PSM_DONE_RESETS_BITS _u(0x00000008)
#define PSM_DONE_RESETS_MSB _u(3)
@ -558,7 +494,6 @@
#define PSM_DONE_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_CLOCKS
// Description : None
#define PSM_DONE_CLOCKS_RESET _u(0x0)
#define PSM_DONE_CLOCKS_BITS _u(0x00000004)
#define PSM_DONE_CLOCKS_MSB _u(2)
@ -566,7 +501,6 @@
#define PSM_DONE_CLOCKS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XOSC
// Description : None
#define PSM_DONE_XOSC_RESET _u(0x0)
#define PSM_DONE_XOSC_BITS _u(0x00000002)
#define PSM_DONE_XOSC_MSB _u(1)
@ -574,11 +508,11 @@
#define PSM_DONE_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROSC
// Description : None
#define PSM_DONE_ROSC_RESET _u(0x0)
#define PSM_DONE_ROSC_BITS _u(0x00000001)
#define PSM_DONE_ROSC_MSB _u(0)
#define PSM_DONE_ROSC_LSB _u(0)
#define PSM_DONE_ROSC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_PSM_DEFINED
#endif // _HARDWARE_REGS_PSM_H

131
lib/rp2040/hardware/regs/pwm.h → lib/pico-sdk/rp2040/hardware/regs/pwm.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,8 +11,8 @@
// Bus type : apb
// Description : Simple PWM
// =============================================================================
#ifndef HARDWARE_REGS_PWM_DEFINED
#define HARDWARE_REGS_PWM_DEFINED
#ifndef _HARDWARE_REGS_PWM_H
#define _HARDWARE_REGS_PWM_H
// =============================================================================
// Register : PWM_CH0_CSR
// Description : Control and status register
@ -42,12 +44,10 @@
#define PWM_CH0_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CSR_DIVMODE
// Description : 0x0 -> Free-running counting at rate dictated by fractional
// divider
// 0x0 -> Free-running counting at rate dictated by fractional divider
// 0x1 -> Fractional divider operation is gated by the PWM B pin.
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
// 0x3 -> Counter advances with each falling edge of the PWM B pin.
#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0)
#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030)
#define PWM_CH0_CSR_DIVMODE_MSB _u(5)
@ -99,7 +99,6 @@
#define PWM_CH0_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH0_DIV_INT
// Description : None
#define PWM_CH0_DIV_INT_RESET _u(0x01)
#define PWM_CH0_DIV_INT_BITS _u(0x00000ff0)
#define PWM_CH0_DIV_INT_MSB _u(11)
@ -107,7 +106,6 @@
#define PWM_CH0_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_DIV_FRAC
// Description : None
#define PWM_CH0_DIV_FRAC_RESET _u(0x0)
#define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f)
#define PWM_CH0_DIV_FRAC_MSB _u(3)
@ -130,7 +128,6 @@
#define PWM_CH0_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CC_B
// Description : None
#define PWM_CH0_CC_B_RESET _u(0x0000)
#define PWM_CH0_CC_B_BITS _u(0xffff0000)
#define PWM_CH0_CC_B_MSB _u(31)
@ -138,7 +135,6 @@
#define PWM_CH0_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH0_CC_A
// Description : None
#define PWM_CH0_CC_A_RESET _u(0x0000)
#define PWM_CH0_CC_A_BITS _u(0x0000ffff)
#define PWM_CH0_CC_A_MSB _u(15)
@ -184,12 +180,10 @@
#define PWM_CH1_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CSR_DIVMODE
// Description : 0x0 -> Free-running counting at rate dictated by fractional
// divider
// 0x0 -> Free-running counting at rate dictated by fractional divider
// 0x1 -> Fractional divider operation is gated by the PWM B pin.
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
// 0x3 -> Counter advances with each falling edge of the PWM B pin.
#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0)
#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030)
#define PWM_CH1_CSR_DIVMODE_MSB _u(5)
@ -241,7 +235,6 @@
#define PWM_CH1_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH1_DIV_INT
// Description : None
#define PWM_CH1_DIV_INT_RESET _u(0x01)
#define PWM_CH1_DIV_INT_BITS _u(0x00000ff0)
#define PWM_CH1_DIV_INT_MSB _u(11)
@ -249,7 +242,6 @@
#define PWM_CH1_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_DIV_FRAC
// Description : None
#define PWM_CH1_DIV_FRAC_RESET _u(0x0)
#define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f)
#define PWM_CH1_DIV_FRAC_MSB _u(3)
@ -272,7 +264,6 @@
#define PWM_CH1_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CC_B
// Description : None
#define PWM_CH1_CC_B_RESET _u(0x0000)
#define PWM_CH1_CC_B_BITS _u(0xffff0000)
#define PWM_CH1_CC_B_MSB _u(31)
@ -280,7 +271,6 @@
#define PWM_CH1_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH1_CC_A
// Description : None
#define PWM_CH1_CC_A_RESET _u(0x0000)
#define PWM_CH1_CC_A_BITS _u(0x0000ffff)
#define PWM_CH1_CC_A_MSB _u(15)
@ -326,12 +316,10 @@
#define PWM_CH2_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CSR_DIVMODE
// Description : 0x0 -> Free-running counting at rate dictated by fractional
// divider
// 0x0 -> Free-running counting at rate dictated by fractional divider
// 0x1 -> Fractional divider operation is gated by the PWM B pin.
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
// 0x3 -> Counter advances with each falling edge of the PWM B pin.
#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0)
#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030)
#define PWM_CH2_CSR_DIVMODE_MSB _u(5)
@ -383,7 +371,6 @@
#define PWM_CH2_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH2_DIV_INT
// Description : None
#define PWM_CH2_DIV_INT_RESET _u(0x01)
#define PWM_CH2_DIV_INT_BITS _u(0x00000ff0)
#define PWM_CH2_DIV_INT_MSB _u(11)
@ -391,7 +378,6 @@
#define PWM_CH2_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_DIV_FRAC
// Description : None
#define PWM_CH2_DIV_FRAC_RESET _u(0x0)
#define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f)
#define PWM_CH2_DIV_FRAC_MSB _u(3)
@ -414,7 +400,6 @@
#define PWM_CH2_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CC_B
// Description : None
#define PWM_CH2_CC_B_RESET _u(0x0000)
#define PWM_CH2_CC_B_BITS _u(0xffff0000)
#define PWM_CH2_CC_B_MSB _u(31)
@ -422,7 +407,6 @@
#define PWM_CH2_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH2_CC_A
// Description : None
#define PWM_CH2_CC_A_RESET _u(0x0000)
#define PWM_CH2_CC_A_BITS _u(0x0000ffff)
#define PWM_CH2_CC_A_MSB _u(15)
@ -468,12 +452,10 @@
#define PWM_CH3_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CSR_DIVMODE
// Description : 0x0 -> Free-running counting at rate dictated by fractional
// divider
// 0x0 -> Free-running counting at rate dictated by fractional divider
// 0x1 -> Fractional divider operation is gated by the PWM B pin.
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
// 0x3 -> Counter advances with each falling edge of the PWM B pin.
#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0)
#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030)
#define PWM_CH3_CSR_DIVMODE_MSB _u(5)
@ -525,7 +507,6 @@
#define PWM_CH3_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH3_DIV_INT
// Description : None
#define PWM_CH3_DIV_INT_RESET _u(0x01)
#define PWM_CH3_DIV_INT_BITS _u(0x00000ff0)
#define PWM_CH3_DIV_INT_MSB _u(11)
@ -533,7 +514,6 @@
#define PWM_CH3_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_DIV_FRAC
// Description : None
#define PWM_CH3_DIV_FRAC_RESET _u(0x0)
#define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f)
#define PWM_CH3_DIV_FRAC_MSB _u(3)
@ -556,7 +536,6 @@
#define PWM_CH3_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CC_B
// Description : None
#define PWM_CH3_CC_B_RESET _u(0x0000)
#define PWM_CH3_CC_B_BITS _u(0xffff0000)
#define PWM_CH3_CC_B_MSB _u(31)
@ -564,7 +543,6 @@
#define PWM_CH3_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH3_CC_A
// Description : None
#define PWM_CH3_CC_A_RESET _u(0x0000)
#define PWM_CH3_CC_A_BITS _u(0x0000ffff)
#define PWM_CH3_CC_A_MSB _u(15)
@ -610,12 +588,10 @@
#define PWM_CH4_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CSR_DIVMODE
// Description : 0x0 -> Free-running counting at rate dictated by fractional
// divider
// 0x0 -> Free-running counting at rate dictated by fractional divider
// 0x1 -> Fractional divider operation is gated by the PWM B pin.
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
// 0x3 -> Counter advances with each falling edge of the PWM B pin.
#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0)
#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030)
#define PWM_CH4_CSR_DIVMODE_MSB _u(5)
@ -667,7 +643,6 @@
#define PWM_CH4_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH4_DIV_INT
// Description : None
#define PWM_CH4_DIV_INT_RESET _u(0x01)
#define PWM_CH4_DIV_INT_BITS _u(0x00000ff0)
#define PWM_CH4_DIV_INT_MSB _u(11)
@ -675,7 +650,6 @@
#define PWM_CH4_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_DIV_FRAC
// Description : None
#define PWM_CH4_DIV_FRAC_RESET _u(0x0)
#define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f)
#define PWM_CH4_DIV_FRAC_MSB _u(3)
@ -698,7 +672,6 @@
#define PWM_CH4_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CC_B
// Description : None
#define PWM_CH4_CC_B_RESET _u(0x0000)
#define PWM_CH4_CC_B_BITS _u(0xffff0000)
#define PWM_CH4_CC_B_MSB _u(31)
@ -706,7 +679,6 @@
#define PWM_CH4_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH4_CC_A
// Description : None
#define PWM_CH4_CC_A_RESET _u(0x0000)
#define PWM_CH4_CC_A_BITS _u(0x0000ffff)
#define PWM_CH4_CC_A_MSB _u(15)
@ -752,12 +724,10 @@
#define PWM_CH5_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CSR_DIVMODE
// Description : 0x0 -> Free-running counting at rate dictated by fractional
// divider
// 0x0 -> Free-running counting at rate dictated by fractional divider
// 0x1 -> Fractional divider operation is gated by the PWM B pin.
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
// 0x3 -> Counter advances with each falling edge of the PWM B pin.
#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0)
#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030)
#define PWM_CH5_CSR_DIVMODE_MSB _u(5)
@ -809,7 +779,6 @@
#define PWM_CH5_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH5_DIV_INT
// Description : None
#define PWM_CH5_DIV_INT_RESET _u(0x01)
#define PWM_CH5_DIV_INT_BITS _u(0x00000ff0)
#define PWM_CH5_DIV_INT_MSB _u(11)
@ -817,7 +786,6 @@
#define PWM_CH5_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_DIV_FRAC
// Description : None
#define PWM_CH5_DIV_FRAC_RESET _u(0x0)
#define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f)
#define PWM_CH5_DIV_FRAC_MSB _u(3)
@ -840,7 +808,6 @@
#define PWM_CH5_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CC_B
// Description : None
#define PWM_CH5_CC_B_RESET _u(0x0000)
#define PWM_CH5_CC_B_BITS _u(0xffff0000)
#define PWM_CH5_CC_B_MSB _u(31)
@ -848,7 +815,6 @@
#define PWM_CH5_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH5_CC_A
// Description : None
#define PWM_CH5_CC_A_RESET _u(0x0000)
#define PWM_CH5_CC_A_BITS _u(0x0000ffff)
#define PWM_CH5_CC_A_MSB _u(15)
@ -894,12 +860,10 @@
#define PWM_CH6_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CSR_DIVMODE
// Description : 0x0 -> Free-running counting at rate dictated by fractional
// divider
// 0x0 -> Free-running counting at rate dictated by fractional divider
// 0x1 -> Fractional divider operation is gated by the PWM B pin.
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
// 0x3 -> Counter advances with each falling edge of the PWM B pin.
#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0)
#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030)
#define PWM_CH6_CSR_DIVMODE_MSB _u(5)
@ -951,7 +915,6 @@
#define PWM_CH6_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH6_DIV_INT
// Description : None
#define PWM_CH6_DIV_INT_RESET _u(0x01)
#define PWM_CH6_DIV_INT_BITS _u(0x00000ff0)
#define PWM_CH6_DIV_INT_MSB _u(11)
@ -959,7 +922,6 @@
#define PWM_CH6_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_DIV_FRAC
// Description : None
#define PWM_CH6_DIV_FRAC_RESET _u(0x0)
#define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f)
#define PWM_CH6_DIV_FRAC_MSB _u(3)
@ -982,7 +944,6 @@
#define PWM_CH6_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CC_B
// Description : None
#define PWM_CH6_CC_B_RESET _u(0x0000)
#define PWM_CH6_CC_B_BITS _u(0xffff0000)
#define PWM_CH6_CC_B_MSB _u(31)
@ -990,7 +951,6 @@
#define PWM_CH6_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH6_CC_A
// Description : None
#define PWM_CH6_CC_A_RESET _u(0x0000)
#define PWM_CH6_CC_A_BITS _u(0x0000ffff)
#define PWM_CH6_CC_A_MSB _u(15)
@ -1036,12 +996,10 @@
#define PWM_CH7_CSR_PH_RET_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CSR_DIVMODE
// Description : 0x0 -> Free-running counting at rate dictated by fractional
// divider
// 0x0 -> Free-running counting at rate dictated by fractional divider
// 0x1 -> Fractional divider operation is gated by the PWM B pin.
// 0x2 -> Counter advances with each rising edge of the PWM B pin.
// 0x3 -> Counter advances with each falling edge of the PWM B
// pin.
// 0x3 -> Counter advances with each falling edge of the PWM B pin.
#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0)
#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030)
#define PWM_CH7_CSR_DIVMODE_MSB _u(5)
@ -1093,7 +1051,6 @@
#define PWM_CH7_DIV_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : PWM_CH7_DIV_INT
// Description : None
#define PWM_CH7_DIV_INT_RESET _u(0x01)
#define PWM_CH7_DIV_INT_BITS _u(0x00000ff0)
#define PWM_CH7_DIV_INT_MSB _u(11)
@ -1101,7 +1058,6 @@
#define PWM_CH7_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_DIV_FRAC
// Description : None
#define PWM_CH7_DIV_FRAC_RESET _u(0x0)
#define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f)
#define PWM_CH7_DIV_FRAC_MSB _u(3)
@ -1124,7 +1080,6 @@
#define PWM_CH7_CC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CC_B
// Description : None
#define PWM_CH7_CC_B_RESET _u(0x0000)
#define PWM_CH7_CC_B_BITS _u(0xffff0000)
#define PWM_CH7_CC_B_MSB _u(31)
@ -1132,7 +1087,6 @@
#define PWM_CH7_CC_B_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_CH7_CC_A
// Description : None
#define PWM_CH7_CC_A_RESET _u(0x0000)
#define PWM_CH7_CC_A_BITS _u(0x0000ffff)
#define PWM_CH7_CC_A_MSB _u(15)
@ -1159,7 +1113,6 @@
#define PWM_EN_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH7
// Description : None
#define PWM_EN_CH7_RESET _u(0x0)
#define PWM_EN_CH7_BITS _u(0x00000080)
#define PWM_EN_CH7_MSB _u(7)
@ -1167,7 +1120,6 @@
#define PWM_EN_CH7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH6
// Description : None
#define PWM_EN_CH6_RESET _u(0x0)
#define PWM_EN_CH6_BITS _u(0x00000040)
#define PWM_EN_CH6_MSB _u(6)
@ -1175,7 +1127,6 @@
#define PWM_EN_CH6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH5
// Description : None
#define PWM_EN_CH5_RESET _u(0x0)
#define PWM_EN_CH5_BITS _u(0x00000020)
#define PWM_EN_CH5_MSB _u(5)
@ -1183,7 +1134,6 @@
#define PWM_EN_CH5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH4
// Description : None
#define PWM_EN_CH4_RESET _u(0x0)
#define PWM_EN_CH4_BITS _u(0x00000010)
#define PWM_EN_CH4_MSB _u(4)
@ -1191,7 +1141,6 @@
#define PWM_EN_CH4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH3
// Description : None
#define PWM_EN_CH3_RESET _u(0x0)
#define PWM_EN_CH3_BITS _u(0x00000008)
#define PWM_EN_CH3_MSB _u(3)
@ -1199,7 +1148,6 @@
#define PWM_EN_CH3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH2
// Description : None
#define PWM_EN_CH2_RESET _u(0x0)
#define PWM_EN_CH2_BITS _u(0x00000004)
#define PWM_EN_CH2_MSB _u(2)
@ -1207,7 +1155,6 @@
#define PWM_EN_CH2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH1
// Description : None
#define PWM_EN_CH1_RESET _u(0x0)
#define PWM_EN_CH1_BITS _u(0x00000002)
#define PWM_EN_CH1_MSB _u(1)
@ -1215,7 +1162,6 @@
#define PWM_EN_CH1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_EN_CH0
// Description : None
#define PWM_EN_CH0_RESET _u(0x0)
#define PWM_EN_CH0_BITS _u(0x00000001)
#define PWM_EN_CH0_MSB _u(0)
@ -1229,7 +1175,6 @@
#define PWM_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH7
// Description : None
#define PWM_INTR_CH7_RESET _u(0x0)
#define PWM_INTR_CH7_BITS _u(0x00000080)
#define PWM_INTR_CH7_MSB _u(7)
@ -1237,7 +1182,6 @@
#define PWM_INTR_CH7_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH6
// Description : None
#define PWM_INTR_CH6_RESET _u(0x0)
#define PWM_INTR_CH6_BITS _u(0x00000040)
#define PWM_INTR_CH6_MSB _u(6)
@ -1245,7 +1189,6 @@
#define PWM_INTR_CH6_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH5
// Description : None
#define PWM_INTR_CH5_RESET _u(0x0)
#define PWM_INTR_CH5_BITS _u(0x00000020)
#define PWM_INTR_CH5_MSB _u(5)
@ -1253,7 +1196,6 @@
#define PWM_INTR_CH5_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH4
// Description : None
#define PWM_INTR_CH4_RESET _u(0x0)
#define PWM_INTR_CH4_BITS _u(0x00000010)
#define PWM_INTR_CH4_MSB _u(4)
@ -1261,7 +1203,6 @@
#define PWM_INTR_CH4_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH3
// Description : None
#define PWM_INTR_CH3_RESET _u(0x0)
#define PWM_INTR_CH3_BITS _u(0x00000008)
#define PWM_INTR_CH3_MSB _u(3)
@ -1269,7 +1210,6 @@
#define PWM_INTR_CH3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH2
// Description : None
#define PWM_INTR_CH2_RESET _u(0x0)
#define PWM_INTR_CH2_BITS _u(0x00000004)
#define PWM_INTR_CH2_MSB _u(2)
@ -1277,7 +1217,6 @@
#define PWM_INTR_CH2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH1
// Description : None
#define PWM_INTR_CH1_RESET _u(0x0)
#define PWM_INTR_CH1_BITS _u(0x00000002)
#define PWM_INTR_CH1_MSB _u(1)
@ -1285,7 +1224,6 @@
#define PWM_INTR_CH1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PWM_INTR_CH0
// Description : None
#define PWM_INTR_CH0_RESET _u(0x0)
#define PWM_INTR_CH0_BITS _u(0x00000001)
#define PWM_INTR_CH0_MSB _u(0)
@ -1299,7 +1237,6 @@
#define PWM_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH7
// Description : None
#define PWM_INTE_CH7_RESET _u(0x0)
#define PWM_INTE_CH7_BITS _u(0x00000080)
#define PWM_INTE_CH7_MSB _u(7)
@ -1307,7 +1244,6 @@
#define PWM_INTE_CH7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH6
// Description : None
#define PWM_INTE_CH6_RESET _u(0x0)
#define PWM_INTE_CH6_BITS _u(0x00000040)
#define PWM_INTE_CH6_MSB _u(6)
@ -1315,7 +1251,6 @@
#define PWM_INTE_CH6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH5
// Description : None
#define PWM_INTE_CH5_RESET _u(0x0)
#define PWM_INTE_CH5_BITS _u(0x00000020)
#define PWM_INTE_CH5_MSB _u(5)
@ -1323,7 +1258,6 @@
#define PWM_INTE_CH5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH4
// Description : None
#define PWM_INTE_CH4_RESET _u(0x0)
#define PWM_INTE_CH4_BITS _u(0x00000010)
#define PWM_INTE_CH4_MSB _u(4)
@ -1331,7 +1265,6 @@
#define PWM_INTE_CH4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH3
// Description : None
#define PWM_INTE_CH3_RESET _u(0x0)
#define PWM_INTE_CH3_BITS _u(0x00000008)
#define PWM_INTE_CH3_MSB _u(3)
@ -1339,7 +1272,6 @@
#define PWM_INTE_CH3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH2
// Description : None
#define PWM_INTE_CH2_RESET _u(0x0)
#define PWM_INTE_CH2_BITS _u(0x00000004)
#define PWM_INTE_CH2_MSB _u(2)
@ -1347,7 +1279,6 @@
#define PWM_INTE_CH2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH1
// Description : None
#define PWM_INTE_CH1_RESET _u(0x0)
#define PWM_INTE_CH1_BITS _u(0x00000002)
#define PWM_INTE_CH1_MSB _u(1)
@ -1355,7 +1286,6 @@
#define PWM_INTE_CH1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTE_CH0
// Description : None
#define PWM_INTE_CH0_RESET _u(0x0)
#define PWM_INTE_CH0_BITS _u(0x00000001)
#define PWM_INTE_CH0_MSB _u(0)
@ -1369,7 +1299,6 @@
#define PWM_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH7
// Description : None
#define PWM_INTF_CH7_RESET _u(0x0)
#define PWM_INTF_CH7_BITS _u(0x00000080)
#define PWM_INTF_CH7_MSB _u(7)
@ -1377,7 +1306,6 @@
#define PWM_INTF_CH7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH6
// Description : None
#define PWM_INTF_CH6_RESET _u(0x0)
#define PWM_INTF_CH6_BITS _u(0x00000040)
#define PWM_INTF_CH6_MSB _u(6)
@ -1385,7 +1313,6 @@
#define PWM_INTF_CH6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH5
// Description : None
#define PWM_INTF_CH5_RESET _u(0x0)
#define PWM_INTF_CH5_BITS _u(0x00000020)
#define PWM_INTF_CH5_MSB _u(5)
@ -1393,7 +1320,6 @@
#define PWM_INTF_CH5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH4
// Description : None
#define PWM_INTF_CH4_RESET _u(0x0)
#define PWM_INTF_CH4_BITS _u(0x00000010)
#define PWM_INTF_CH4_MSB _u(4)
@ -1401,7 +1327,6 @@
#define PWM_INTF_CH4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH3
// Description : None
#define PWM_INTF_CH3_RESET _u(0x0)
#define PWM_INTF_CH3_BITS _u(0x00000008)
#define PWM_INTF_CH3_MSB _u(3)
@ -1409,7 +1334,6 @@
#define PWM_INTF_CH3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH2
// Description : None
#define PWM_INTF_CH2_RESET _u(0x0)
#define PWM_INTF_CH2_BITS _u(0x00000004)
#define PWM_INTF_CH2_MSB _u(2)
@ -1417,7 +1341,6 @@
#define PWM_INTF_CH2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH1
// Description : None
#define PWM_INTF_CH1_RESET _u(0x0)
#define PWM_INTF_CH1_BITS _u(0x00000002)
#define PWM_INTF_CH1_MSB _u(1)
@ -1425,7 +1348,6 @@
#define PWM_INTF_CH1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PWM_INTF_CH0
// Description : None
#define PWM_INTF_CH0_RESET _u(0x0)
#define PWM_INTF_CH0_BITS _u(0x00000001)
#define PWM_INTF_CH0_MSB _u(0)
@ -1439,7 +1361,6 @@
#define PWM_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH7
// Description : None
#define PWM_INTS_CH7_RESET _u(0x0)
#define PWM_INTS_CH7_BITS _u(0x00000080)
#define PWM_INTS_CH7_MSB _u(7)
@ -1447,7 +1368,6 @@
#define PWM_INTS_CH7_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH6
// Description : None
#define PWM_INTS_CH6_RESET _u(0x0)
#define PWM_INTS_CH6_BITS _u(0x00000040)
#define PWM_INTS_CH6_MSB _u(6)
@ -1455,7 +1375,6 @@
#define PWM_INTS_CH6_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH5
// Description : None
#define PWM_INTS_CH5_RESET _u(0x0)
#define PWM_INTS_CH5_BITS _u(0x00000020)
#define PWM_INTS_CH5_MSB _u(5)
@ -1463,7 +1382,6 @@
#define PWM_INTS_CH5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH4
// Description : None
#define PWM_INTS_CH4_RESET _u(0x0)
#define PWM_INTS_CH4_BITS _u(0x00000010)
#define PWM_INTS_CH4_MSB _u(4)
@ -1471,7 +1389,6 @@
#define PWM_INTS_CH4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH3
// Description : None
#define PWM_INTS_CH3_RESET _u(0x0)
#define PWM_INTS_CH3_BITS _u(0x00000008)
#define PWM_INTS_CH3_MSB _u(3)
@ -1479,7 +1396,6 @@
#define PWM_INTS_CH3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH2
// Description : None
#define PWM_INTS_CH2_RESET _u(0x0)
#define PWM_INTS_CH2_BITS _u(0x00000004)
#define PWM_INTS_CH2_MSB _u(2)
@ -1487,7 +1403,6 @@
#define PWM_INTS_CH2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH1
// Description : None
#define PWM_INTS_CH1_RESET _u(0x0)
#define PWM_INTS_CH1_BITS _u(0x00000002)
#define PWM_INTS_CH1_MSB _u(1)
@ -1495,11 +1410,11 @@
#define PWM_INTS_CH1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PWM_INTS_CH0
// Description : None
#define PWM_INTS_CH0_RESET _u(0x0)
#define PWM_INTS_CH0_BITS _u(0x00000001)
#define PWM_INTS_CH0_MSB _u(0)
#define PWM_INTS_CH0_LSB _u(0)
#define PWM_INTS_CH0_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_PWM_DEFINED
#endif // _HARDWARE_REGS_PWM_H

87
lib/rp2040/hardware/regs/resets.h → lib/pico-sdk/rp2040/hardware/regs/resets.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : RESETS
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_RESETS_DEFINED
#define HARDWARE_REGS_RESETS_DEFINED
#ifndef _HARDWARE_REGS_RESETS_H
#define _HARDWARE_REGS_RESETS_H
// =============================================================================
// Register : RESETS_RESET
// Description : Reset control. If a bit is set it means the peripheral is in
@ -20,7 +21,6 @@
#define RESETS_RESET_RESET _u(0x01ffffff)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_USBCTRL
// Description : None
#define RESETS_RESET_USBCTRL_RESET _u(0x1)
#define RESETS_RESET_USBCTRL_BITS _u(0x01000000)
#define RESETS_RESET_USBCTRL_MSB _u(24)
@ -28,7 +28,6 @@
#define RESETS_RESET_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART1
// Description : None
#define RESETS_RESET_UART1_RESET _u(0x1)
#define RESETS_RESET_UART1_BITS _u(0x00800000)
#define RESETS_RESET_UART1_MSB _u(23)
@ -36,7 +35,6 @@
#define RESETS_RESET_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART0
// Description : None
#define RESETS_RESET_UART0_RESET _u(0x1)
#define RESETS_RESET_UART0_BITS _u(0x00400000)
#define RESETS_RESET_UART0_MSB _u(22)
@ -44,7 +42,6 @@
#define RESETS_RESET_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER
// Description : None
#define RESETS_RESET_TIMER_RESET _u(0x1)
#define RESETS_RESET_TIMER_BITS _u(0x00200000)
#define RESETS_RESET_TIMER_MSB _u(21)
@ -52,7 +49,6 @@
#define RESETS_RESET_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TBMAN
// Description : None
#define RESETS_RESET_TBMAN_RESET _u(0x1)
#define RESETS_RESET_TBMAN_BITS _u(0x00100000)
#define RESETS_RESET_TBMAN_MSB _u(20)
@ -60,7 +56,6 @@
#define RESETS_RESET_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSINFO
// Description : None
#define RESETS_RESET_SYSINFO_RESET _u(0x1)
#define RESETS_RESET_SYSINFO_BITS _u(0x00080000)
#define RESETS_RESET_SYSINFO_MSB _u(19)
@ -68,7 +63,6 @@
#define RESETS_RESET_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSCFG
// Description : None
#define RESETS_RESET_SYSCFG_RESET _u(0x1)
#define RESETS_RESET_SYSCFG_BITS _u(0x00040000)
#define RESETS_RESET_SYSCFG_MSB _u(18)
@ -76,7 +70,6 @@
#define RESETS_RESET_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI1
// Description : None
#define RESETS_RESET_SPI1_RESET _u(0x1)
#define RESETS_RESET_SPI1_BITS _u(0x00020000)
#define RESETS_RESET_SPI1_MSB _u(17)
@ -84,7 +77,6 @@
#define RESETS_RESET_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI0
// Description : None
#define RESETS_RESET_SPI0_RESET _u(0x1)
#define RESETS_RESET_SPI0_BITS _u(0x00010000)
#define RESETS_RESET_SPI0_MSB _u(16)
@ -92,7 +84,6 @@
#define RESETS_RESET_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_RTC
// Description : None
#define RESETS_RESET_RTC_RESET _u(0x1)
#define RESETS_RESET_RTC_BITS _u(0x00008000)
#define RESETS_RESET_RTC_MSB _u(15)
@ -100,7 +91,6 @@
#define RESETS_RESET_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PWM
// Description : None
#define RESETS_RESET_PWM_RESET _u(0x1)
#define RESETS_RESET_PWM_BITS _u(0x00004000)
#define RESETS_RESET_PWM_MSB _u(14)
@ -108,7 +98,6 @@
#define RESETS_RESET_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_USB
// Description : None
#define RESETS_RESET_PLL_USB_RESET _u(0x1)
#define RESETS_RESET_PLL_USB_BITS _u(0x00002000)
#define RESETS_RESET_PLL_USB_MSB _u(13)
@ -116,7 +105,6 @@
#define RESETS_RESET_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_SYS
// Description : None
#define RESETS_RESET_PLL_SYS_RESET _u(0x1)
#define RESETS_RESET_PLL_SYS_BITS _u(0x00001000)
#define RESETS_RESET_PLL_SYS_MSB _u(12)
@ -124,7 +112,6 @@
#define RESETS_RESET_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO1
// Description : None
#define RESETS_RESET_PIO1_RESET _u(0x1)
#define RESETS_RESET_PIO1_BITS _u(0x00000800)
#define RESETS_RESET_PIO1_MSB _u(11)
@ -132,7 +119,6 @@
#define RESETS_RESET_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO0
// Description : None
#define RESETS_RESET_PIO0_RESET _u(0x1)
#define RESETS_RESET_PIO0_BITS _u(0x00000400)
#define RESETS_RESET_PIO0_MSB _u(10)
@ -140,7 +126,6 @@
#define RESETS_RESET_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_QSPI
// Description : None
#define RESETS_RESET_PADS_QSPI_RESET _u(0x1)
#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200)
#define RESETS_RESET_PADS_QSPI_MSB _u(9)
@ -148,7 +133,6 @@
#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_BANK0
// Description : None
#define RESETS_RESET_PADS_BANK0_RESET _u(0x1)
#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100)
#define RESETS_RESET_PADS_BANK0_MSB _u(8)
@ -156,7 +140,6 @@
#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_JTAG
// Description : None
#define RESETS_RESET_JTAG_RESET _u(0x1)
#define RESETS_RESET_JTAG_BITS _u(0x00000080)
#define RESETS_RESET_JTAG_MSB _u(7)
@ -164,7 +147,6 @@
#define RESETS_RESET_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_QSPI
// Description : None
#define RESETS_RESET_IO_QSPI_RESET _u(0x1)
#define RESETS_RESET_IO_QSPI_BITS _u(0x00000040)
#define RESETS_RESET_IO_QSPI_MSB _u(6)
@ -172,7 +154,6 @@
#define RESETS_RESET_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_BANK0
// Description : None
#define RESETS_RESET_IO_BANK0_RESET _u(0x1)
#define RESETS_RESET_IO_BANK0_BITS _u(0x00000020)
#define RESETS_RESET_IO_BANK0_MSB _u(5)
@ -180,7 +161,6 @@
#define RESETS_RESET_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C1
// Description : None
#define RESETS_RESET_I2C1_RESET _u(0x1)
#define RESETS_RESET_I2C1_BITS _u(0x00000010)
#define RESETS_RESET_I2C1_MSB _u(4)
@ -188,7 +168,6 @@
#define RESETS_RESET_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C0
// Description : None
#define RESETS_RESET_I2C0_RESET _u(0x1)
#define RESETS_RESET_I2C0_BITS _u(0x00000008)
#define RESETS_RESET_I2C0_MSB _u(3)
@ -196,7 +175,6 @@
#define RESETS_RESET_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DMA
// Description : None
#define RESETS_RESET_DMA_RESET _u(0x1)
#define RESETS_RESET_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DMA_MSB _u(2)
@ -204,7 +182,6 @@
#define RESETS_RESET_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_BUSCTRL
// Description : None
#define RESETS_RESET_BUSCTRL_RESET _u(0x1)
#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_BUSCTRL_MSB _u(1)
@ -212,7 +189,6 @@
#define RESETS_RESET_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_ADC
// Description : None
#define RESETS_RESET_ADC_RESET _u(0x1)
#define RESETS_RESET_ADC_BITS _u(0x00000001)
#define RESETS_RESET_ADC_MSB _u(0)
@ -227,7 +203,6 @@
#define RESETS_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_USBCTRL
// Description : None
#define RESETS_WDSEL_USBCTRL_RESET _u(0x0)
#define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000)
#define RESETS_WDSEL_USBCTRL_MSB _u(24)
@ -235,7 +210,6 @@
#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART1
// Description : None
#define RESETS_WDSEL_UART1_RESET _u(0x0)
#define RESETS_WDSEL_UART1_BITS _u(0x00800000)
#define RESETS_WDSEL_UART1_MSB _u(23)
@ -243,7 +217,6 @@
#define RESETS_WDSEL_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART0
// Description : None
#define RESETS_WDSEL_UART0_RESET _u(0x0)
#define RESETS_WDSEL_UART0_BITS _u(0x00400000)
#define RESETS_WDSEL_UART0_MSB _u(22)
@ -251,7 +224,6 @@
#define RESETS_WDSEL_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER
// Description : None
#define RESETS_WDSEL_TIMER_RESET _u(0x0)
#define RESETS_WDSEL_TIMER_BITS _u(0x00200000)
#define RESETS_WDSEL_TIMER_MSB _u(21)
@ -259,7 +231,6 @@
#define RESETS_WDSEL_TIMER_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TBMAN
// Description : None
#define RESETS_WDSEL_TBMAN_RESET _u(0x0)
#define RESETS_WDSEL_TBMAN_BITS _u(0x00100000)
#define RESETS_WDSEL_TBMAN_MSB _u(20)
@ -267,7 +238,6 @@
#define RESETS_WDSEL_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSINFO
// Description : None
#define RESETS_WDSEL_SYSINFO_RESET _u(0x0)
#define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000)
#define RESETS_WDSEL_SYSINFO_MSB _u(19)
@ -275,7 +245,6 @@
#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSCFG
// Description : None
#define RESETS_WDSEL_SYSCFG_RESET _u(0x0)
#define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000)
#define RESETS_WDSEL_SYSCFG_MSB _u(18)
@ -283,7 +252,6 @@
#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI1
// Description : None
#define RESETS_WDSEL_SPI1_RESET _u(0x0)
#define RESETS_WDSEL_SPI1_BITS _u(0x00020000)
#define RESETS_WDSEL_SPI1_MSB _u(17)
@ -291,7 +259,6 @@
#define RESETS_WDSEL_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI0
// Description : None
#define RESETS_WDSEL_SPI0_RESET _u(0x0)
#define RESETS_WDSEL_SPI0_BITS _u(0x00010000)
#define RESETS_WDSEL_SPI0_MSB _u(16)
@ -299,7 +266,6 @@
#define RESETS_WDSEL_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_RTC
// Description : None
#define RESETS_WDSEL_RTC_RESET _u(0x0)
#define RESETS_WDSEL_RTC_BITS _u(0x00008000)
#define RESETS_WDSEL_RTC_MSB _u(15)
@ -307,7 +273,6 @@
#define RESETS_WDSEL_RTC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PWM
// Description : None
#define RESETS_WDSEL_PWM_RESET _u(0x0)
#define RESETS_WDSEL_PWM_BITS _u(0x00004000)
#define RESETS_WDSEL_PWM_MSB _u(14)
@ -315,7 +280,6 @@
#define RESETS_WDSEL_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_USB
// Description : None
#define RESETS_WDSEL_PLL_USB_RESET _u(0x0)
#define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000)
#define RESETS_WDSEL_PLL_USB_MSB _u(13)
@ -323,7 +287,6 @@
#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_SYS
// Description : None
#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0)
#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000)
#define RESETS_WDSEL_PLL_SYS_MSB _u(12)
@ -331,7 +294,6 @@
#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO1
// Description : None
#define RESETS_WDSEL_PIO1_RESET _u(0x0)
#define RESETS_WDSEL_PIO1_BITS _u(0x00000800)
#define RESETS_WDSEL_PIO1_MSB _u(11)
@ -339,7 +301,6 @@
#define RESETS_WDSEL_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO0
// Description : None
#define RESETS_WDSEL_PIO0_RESET _u(0x0)
#define RESETS_WDSEL_PIO0_BITS _u(0x00000400)
#define RESETS_WDSEL_PIO0_MSB _u(10)
@ -347,7 +308,6 @@
#define RESETS_WDSEL_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_QSPI
// Description : None
#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200)
#define RESETS_WDSEL_PADS_QSPI_MSB _u(9)
@ -355,7 +315,6 @@
#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_BANK0
// Description : None
#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100)
#define RESETS_WDSEL_PADS_BANK0_MSB _u(8)
@ -363,7 +322,6 @@
#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_JTAG
// Description : None
#define RESETS_WDSEL_JTAG_RESET _u(0x0)
#define RESETS_WDSEL_JTAG_BITS _u(0x00000080)
#define RESETS_WDSEL_JTAG_MSB _u(7)
@ -371,7 +329,6 @@
#define RESETS_WDSEL_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_QSPI
// Description : None
#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040)
#define RESETS_WDSEL_IO_QSPI_MSB _u(6)
@ -379,7 +336,6 @@
#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_BANK0
// Description : None
#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020)
#define RESETS_WDSEL_IO_BANK0_MSB _u(5)
@ -387,7 +343,6 @@
#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C1
// Description : None
#define RESETS_WDSEL_I2C1_RESET _u(0x0)
#define RESETS_WDSEL_I2C1_BITS _u(0x00000010)
#define RESETS_WDSEL_I2C1_MSB _u(4)
@ -395,7 +350,6 @@
#define RESETS_WDSEL_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C0
// Description : None
#define RESETS_WDSEL_I2C0_RESET _u(0x0)
#define RESETS_WDSEL_I2C0_BITS _u(0x00000008)
#define RESETS_WDSEL_I2C0_MSB _u(3)
@ -403,7 +357,6 @@
#define RESETS_WDSEL_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_DMA
// Description : None
#define RESETS_WDSEL_DMA_RESET _u(0x0)
#define RESETS_WDSEL_DMA_BITS _u(0x00000004)
#define RESETS_WDSEL_DMA_MSB _u(2)
@ -411,7 +364,6 @@
#define RESETS_WDSEL_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_BUSCTRL
// Description : None
#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0)
#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002)
#define RESETS_WDSEL_BUSCTRL_MSB _u(1)
@ -419,7 +371,6 @@
#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_ADC
// Description : None
#define RESETS_WDSEL_ADC_RESET _u(0x0)
#define RESETS_WDSEL_ADC_BITS _u(0x00000001)
#define RESETS_WDSEL_ADC_MSB _u(0)
@ -435,7 +386,6 @@
#define RESETS_RESET_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_USBCTRL
// Description : None
#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000)
#define RESETS_RESET_DONE_USBCTRL_MSB _u(24)
@ -443,7 +393,6 @@
#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART1
// Description : None
#define RESETS_RESET_DONE_UART1_RESET _u(0x0)
#define RESETS_RESET_DONE_UART1_BITS _u(0x00800000)
#define RESETS_RESET_DONE_UART1_MSB _u(23)
@ -451,7 +400,6 @@
#define RESETS_RESET_DONE_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART0
// Description : None
#define RESETS_RESET_DONE_UART0_RESET _u(0x0)
#define RESETS_RESET_DONE_UART0_BITS _u(0x00400000)
#define RESETS_RESET_DONE_UART0_MSB _u(22)
@ -459,7 +407,6 @@
#define RESETS_RESET_DONE_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER
// Description : None
#define RESETS_RESET_DONE_TIMER_RESET _u(0x0)
#define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000)
#define RESETS_RESET_DONE_TIMER_MSB _u(21)
@ -467,7 +414,6 @@
#define RESETS_RESET_DONE_TIMER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TBMAN
// Description : None
#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0)
#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000)
#define RESETS_RESET_DONE_TBMAN_MSB _u(20)
@ -475,7 +421,6 @@
#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSINFO
// Description : None
#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000)
#define RESETS_RESET_DONE_SYSINFO_MSB _u(19)
@ -483,7 +428,6 @@
#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSCFG
// Description : None
#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000)
#define RESETS_RESET_DONE_SYSCFG_MSB _u(18)
@ -491,7 +435,6 @@
#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI1
// Description : None
#define RESETS_RESET_DONE_SPI1_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000)
#define RESETS_RESET_DONE_SPI1_MSB _u(17)
@ -499,7 +442,6 @@
#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI0
// Description : None
#define RESETS_RESET_DONE_SPI0_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000)
#define RESETS_RESET_DONE_SPI0_MSB _u(16)
@ -507,7 +449,6 @@
#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_RTC
// Description : None
#define RESETS_RESET_DONE_RTC_RESET _u(0x0)
#define RESETS_RESET_DONE_RTC_BITS _u(0x00008000)
#define RESETS_RESET_DONE_RTC_MSB _u(15)
@ -515,7 +456,6 @@
#define RESETS_RESET_DONE_RTC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PWM
// Description : None
#define RESETS_RESET_DONE_PWM_RESET _u(0x0)
#define RESETS_RESET_DONE_PWM_BITS _u(0x00004000)
#define RESETS_RESET_DONE_PWM_MSB _u(14)
@ -523,7 +463,6 @@
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_USB
// Description : None
#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000)
#define RESETS_RESET_DONE_PLL_USB_MSB _u(13)
@ -531,7 +470,6 @@
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_SYS
// Description : None
#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000)
#define RESETS_RESET_DONE_PLL_SYS_MSB _u(12)
@ -539,7 +477,6 @@
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO1
// Description : None
#define RESETS_RESET_DONE_PIO1_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800)
#define RESETS_RESET_DONE_PIO1_MSB _u(11)
@ -547,7 +484,6 @@
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO0
// Description : None
#define RESETS_RESET_DONE_PIO0_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400)
#define RESETS_RESET_DONE_PIO0_MSB _u(10)
@ -555,7 +491,6 @@
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_QSPI
// Description : None
#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200)
#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9)
@ -563,7 +498,6 @@
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_BANK0
// Description : None
#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100)
#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8)
@ -571,7 +505,6 @@
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_JTAG
// Description : None
#define RESETS_RESET_DONE_JTAG_RESET _u(0x0)
#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080)
#define RESETS_RESET_DONE_JTAG_MSB _u(7)
@ -579,7 +512,6 @@
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_QSPI
// Description : None
#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040)
#define RESETS_RESET_DONE_IO_QSPI_MSB _u(6)
@ -587,7 +519,6 @@
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_BANK0
// Description : None
#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020)
#define RESETS_RESET_DONE_IO_BANK0_MSB _u(5)
@ -595,7 +526,6 @@
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C1
// Description : None
#define RESETS_RESET_DONE_I2C1_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010)
#define RESETS_RESET_DONE_I2C1_MSB _u(4)
@ -603,7 +533,6 @@
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C0
// Description : None
#define RESETS_RESET_DONE_I2C0_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008)
#define RESETS_RESET_DONE_I2C0_MSB _u(3)
@ -611,7 +540,6 @@
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_DMA
// Description : None
#define RESETS_RESET_DONE_DMA_RESET _u(0x0)
#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DONE_DMA_MSB _u(2)
@ -619,7 +547,6 @@
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_BUSCTRL
// Description : None
#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1)
@ -627,11 +554,11 @@
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_ADC
// Description : None
#define RESETS_RESET_DONE_ADC_RESET _u(0x0)
#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001)
#define RESETS_RESET_DONE_ADC_MSB _u(0)
#define RESETS_RESET_DONE_ADC_LSB _u(0)
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RESETS_DEFINED
#endif // _HARDWARE_REGS_RESETS_H

20
lib/rp2040/hardware/regs/rosc.h → lib/pico-sdk/rp2040/hardware/regs/rosc.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : ROSC
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_ROSC_DEFINED
#define HARDWARE_REGS_ROSC_DEFINED
#ifndef _HARDWARE_REGS_ROSC_H
#define _HARDWARE_REGS_ROSC_H
// =============================================================================
// Register : ROSC_CTRL
// Description : Ring Oscillator control
@ -38,9 +39,9 @@
// Field : ROSC_CTRL_FREQ_RANGE
// Description : Controls the number of delay stages in the ROSC ring
// LOW uses stages 0 to 7
// MEDIUM uses stages 0 to 5
// HIGH uses stages 0 to 3
// TOOHIGH uses stages 0 to 1 and should not be used because its
// MEDIUM uses stages 2 to 7
// HIGH uses stages 4 to 7
// TOOHIGH uses stages 6 to 7 and should not be used because its
// frequency exceeds design specifications
// The clock output will not glitch when changing the range up one
// step at a time
@ -174,7 +175,7 @@
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// 0x636f6d61 -> dormant
// 0x77616b65 -> WAKE
#define ROSC_DORMANT_OFFSET _u(0x0000000c)
#define ROSC_DORMANT_BITS _u(0xffffffff)
@ -309,4 +310,5 @@
#define ROSC_COUNT_LSB _u(0)
#define ROSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_ROSC_DEFINED
#endif // _HARDWARE_REGS_ROSC_H

16
lib/rp2040/hardware/regs/rtc.h → lib/pico-sdk/rp2040/hardware/regs/rtc.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,8 +11,8 @@
// Bus type : apb
// Description : Register block to control RTC
// =============================================================================
#ifndef HARDWARE_REGS_RTC_DEFINED
#define HARDWARE_REGS_RTC_DEFINED
#ifndef _HARDWARE_REGS_RTC_H
#define _HARDWARE_REGS_RTC_H
// =============================================================================
// Register : RTC_CLKDIV_M1
// Description : Divider minus 1 for the 1 second counter. Safe to change the
@ -136,7 +138,6 @@
#define RTC_IRQ_SETUP_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE
// Description : None
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-"
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000)
#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29)
@ -346,7 +347,6 @@
#define RTC_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTR_RTC
// Description : None
#define RTC_INTR_RTC_RESET _u(0x0)
#define RTC_INTR_RTC_BITS _u(0x00000001)
#define RTC_INTR_RTC_MSB _u(0)
@ -360,7 +360,6 @@
#define RTC_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTE_RTC
// Description : None
#define RTC_INTE_RTC_RESET _u(0x0)
#define RTC_INTE_RTC_BITS _u(0x00000001)
#define RTC_INTE_RTC_MSB _u(0)
@ -374,7 +373,6 @@
#define RTC_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTF_RTC
// Description : None
#define RTC_INTF_RTC_RESET _u(0x0)
#define RTC_INTF_RTC_BITS _u(0x00000001)
#define RTC_INTF_RTC_MSB _u(0)
@ -388,11 +386,11 @@
#define RTC_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RTC_INTS_RTC
// Description : None
#define RTC_INTS_RTC_RESET _u(0x0)
#define RTC_INTS_RTC_BITS _u(0x00000001)
#define RTC_INTS_RTC_MSB _u(0)
#define RTC_INTS_RTC_LSB _u(0)
#define RTC_INTS_RTC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_RTC_DEFINED
#endif // _HARDWARE_REGS_RTC_H

105
lib/rp2040/hardware/regs/sio.h → lib/pico-sdk/rp2040/hardware/regs/sio.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -11,8 +13,8 @@
// Provides core-local and inter-core hardware for the two
// processors, with single-cycle access.
// =============================================================================
#ifndef HARDWARE_REGS_SIO_DEFINED
#define HARDWARE_REGS_SIO_DEFINED
#ifndef _HARDWARE_REGS_SIO_H
#define _HARDWARE_REGS_SIO_H
// =============================================================================
// Register : SIO_CPUID
// Description : Processor core identifier
@ -71,7 +73,7 @@
#define SIO_GPIO_OUT_SET_RESET _u(0x00000000)
#define SIO_GPIO_OUT_SET_MSB _u(29)
#define SIO_GPIO_OUT_SET_LSB _u(0)
#define SIO_GPIO_OUT_SET_ACCESS "RW"
#define SIO_GPIO_OUT_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OUT_CLR
// Description : GPIO output value clear
@ -82,7 +84,7 @@
#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000)
#define SIO_GPIO_OUT_CLR_MSB _u(29)
#define SIO_GPIO_OUT_CLR_LSB _u(0)
#define SIO_GPIO_OUT_CLR_ACCESS "RW"
#define SIO_GPIO_OUT_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OUT_XOR
// Description : GPIO output value XOR
@ -93,7 +95,7 @@
#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000)
#define SIO_GPIO_OUT_XOR_MSB _u(29)
#define SIO_GPIO_OUT_XOR_LSB _u(0)
#define SIO_GPIO_OUT_XOR_ACCESS "RW"
#define SIO_GPIO_OUT_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OE
// Description : GPIO output enable
@ -119,7 +121,7 @@
#define SIO_GPIO_OE_SET_RESET _u(0x00000000)
#define SIO_GPIO_OE_SET_MSB _u(29)
#define SIO_GPIO_OE_SET_LSB _u(0)
#define SIO_GPIO_OE_SET_ACCESS "RW"
#define SIO_GPIO_OE_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OE_CLR
// Description : GPIO output enable clear
@ -130,7 +132,7 @@
#define SIO_GPIO_OE_CLR_RESET _u(0x00000000)
#define SIO_GPIO_OE_CLR_MSB _u(29)
#define SIO_GPIO_OE_CLR_LSB _u(0)
#define SIO_GPIO_OE_CLR_ACCESS "RW"
#define SIO_GPIO_OE_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_OE_XOR
// Description : GPIO output enable XOR
@ -141,7 +143,7 @@
#define SIO_GPIO_OE_XOR_RESET _u(0x00000000)
#define SIO_GPIO_OE_XOR_MSB _u(29)
#define SIO_GPIO_OE_XOR_LSB _u(0)
#define SIO_GPIO_OE_XOR_ACCESS "RW"
#define SIO_GPIO_OE_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OUT
// Description : QSPI output value
@ -169,7 +171,7 @@
#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000)
#define SIO_GPIO_HI_OUT_SET_MSB _u(5)
#define SIO_GPIO_HI_OUT_SET_LSB _u(0)
#define SIO_GPIO_HI_OUT_SET_ACCESS "RW"
#define SIO_GPIO_HI_OUT_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OUT_CLR
// Description : QSPI output value clear
@ -180,7 +182,7 @@
#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OUT_CLR_MSB _u(5)
#define SIO_GPIO_HI_OUT_CLR_LSB _u(0)
#define SIO_GPIO_HI_OUT_CLR_ACCESS "RW"
#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OUT_XOR
// Description : QSPI output value XOR
@ -191,7 +193,7 @@
#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OUT_XOR_MSB _u(5)
#define SIO_GPIO_HI_OUT_XOR_LSB _u(0)
#define SIO_GPIO_HI_OUT_XOR_ACCESS "RW"
#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OE
// Description : QSPI output enable
@ -218,7 +220,7 @@
#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000)
#define SIO_GPIO_HI_OE_SET_MSB _u(5)
#define SIO_GPIO_HI_OE_SET_LSB _u(0)
#define SIO_GPIO_HI_OE_SET_ACCESS "RW"
#define SIO_GPIO_HI_OE_SET_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OE_CLR
// Description : QSPI output enable clear
@ -229,7 +231,7 @@
#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OE_CLR_MSB _u(5)
#define SIO_GPIO_HI_OE_CLR_LSB _u(0)
#define SIO_GPIO_HI_OE_CLR_ACCESS "RW"
#define SIO_GPIO_HI_OE_CLR_ACCESS "WO"
// =============================================================================
// Register : SIO_GPIO_HI_OE_XOR
// Description : QSPI output enable XOR
@ -240,7 +242,7 @@
#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000)
#define SIO_GPIO_HI_OE_XOR_MSB _u(5)
#define SIO_GPIO_HI_OE_XOR_LSB _u(0)
#define SIO_GPIO_HI_OE_XOR_ACCESS "RW"
#define SIO_GPIO_HI_OE_XOR_ACCESS "WO"
// =============================================================================
// Register : SIO_FIFO_ST
// Description : Status register for inter-core FIFOs (mailboxes).
@ -344,7 +346,7 @@
// q`.
// Any operand write starts a new calculation. The results appear
// in QUOTIENT, REMAINDER.
// UDIVIDEND/SDIVIDEND are aliases of the same internal register.
// UDIVISOR/SDIVISOR are aliases of the same internal register.
// The U alias starts an
// unsigned calculation, and the S alias starts a signed
// calculation.
@ -440,8 +442,8 @@
// Writing an operand (xDIVIDEND, xDIVISOR) will immediately start
// a new calculation, no
// matter if one is already in progress.
// Writing to a result register will immediately terminate any
// in-progress calculation
// Writing to a result register will immediately terminate any in-
// progress calculation
// and set the READY and DIRTY flags.
#define SIO_DIV_CSR_READY_RESET _u(0x1)
#define SIO_DIV_CSR_READY_BITS _u(0x00000001)
@ -1155,7 +1157,7 @@
#define SIO_SPINLOCK0_RESET _u(0x00000000)
#define SIO_SPINLOCK0_MSB _u(31)
#define SIO_SPINLOCK0_LSB _u(0)
#define SIO_SPINLOCK0_ACCESS "RO"
#define SIO_SPINLOCK0_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK1
// Description : Reading from a spinlock address will:
@ -1171,7 +1173,7 @@
#define SIO_SPINLOCK1_RESET _u(0x00000000)
#define SIO_SPINLOCK1_MSB _u(31)
#define SIO_SPINLOCK1_LSB _u(0)
#define SIO_SPINLOCK1_ACCESS "RO"
#define SIO_SPINLOCK1_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK2
// Description : Reading from a spinlock address will:
@ -1187,7 +1189,7 @@
#define SIO_SPINLOCK2_RESET _u(0x00000000)
#define SIO_SPINLOCK2_MSB _u(31)
#define SIO_SPINLOCK2_LSB _u(0)
#define SIO_SPINLOCK2_ACCESS "RO"
#define SIO_SPINLOCK2_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK3
// Description : Reading from a spinlock address will:
@ -1203,7 +1205,7 @@
#define SIO_SPINLOCK3_RESET _u(0x00000000)
#define SIO_SPINLOCK3_MSB _u(31)
#define SIO_SPINLOCK3_LSB _u(0)
#define SIO_SPINLOCK3_ACCESS "RO"
#define SIO_SPINLOCK3_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK4
// Description : Reading from a spinlock address will:
@ -1219,7 +1221,7 @@
#define SIO_SPINLOCK4_RESET _u(0x00000000)
#define SIO_SPINLOCK4_MSB _u(31)
#define SIO_SPINLOCK4_LSB _u(0)
#define SIO_SPINLOCK4_ACCESS "RO"
#define SIO_SPINLOCK4_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK5
// Description : Reading from a spinlock address will:
@ -1235,7 +1237,7 @@
#define SIO_SPINLOCK5_RESET _u(0x00000000)
#define SIO_SPINLOCK5_MSB _u(31)
#define SIO_SPINLOCK5_LSB _u(0)
#define SIO_SPINLOCK5_ACCESS "RO"
#define SIO_SPINLOCK5_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK6
// Description : Reading from a spinlock address will:
@ -1251,7 +1253,7 @@
#define SIO_SPINLOCK6_RESET _u(0x00000000)
#define SIO_SPINLOCK6_MSB _u(31)
#define SIO_SPINLOCK6_LSB _u(0)
#define SIO_SPINLOCK6_ACCESS "RO"
#define SIO_SPINLOCK6_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK7
// Description : Reading from a spinlock address will:
@ -1267,7 +1269,7 @@
#define SIO_SPINLOCK7_RESET _u(0x00000000)
#define SIO_SPINLOCK7_MSB _u(31)
#define SIO_SPINLOCK7_LSB _u(0)
#define SIO_SPINLOCK7_ACCESS "RO"
#define SIO_SPINLOCK7_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK8
// Description : Reading from a spinlock address will:
@ -1283,7 +1285,7 @@
#define SIO_SPINLOCK8_RESET _u(0x00000000)
#define SIO_SPINLOCK8_MSB _u(31)
#define SIO_SPINLOCK8_LSB _u(0)
#define SIO_SPINLOCK8_ACCESS "RO"
#define SIO_SPINLOCK8_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK9
// Description : Reading from a spinlock address will:
@ -1299,7 +1301,7 @@
#define SIO_SPINLOCK9_RESET _u(0x00000000)
#define SIO_SPINLOCK9_MSB _u(31)
#define SIO_SPINLOCK9_LSB _u(0)
#define SIO_SPINLOCK9_ACCESS "RO"
#define SIO_SPINLOCK9_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK10
// Description : Reading from a spinlock address will:
@ -1315,7 +1317,7 @@
#define SIO_SPINLOCK10_RESET _u(0x00000000)
#define SIO_SPINLOCK10_MSB _u(31)
#define SIO_SPINLOCK10_LSB _u(0)
#define SIO_SPINLOCK10_ACCESS "RO"
#define SIO_SPINLOCK10_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK11
// Description : Reading from a spinlock address will:
@ -1331,7 +1333,7 @@
#define SIO_SPINLOCK11_RESET _u(0x00000000)
#define SIO_SPINLOCK11_MSB _u(31)
#define SIO_SPINLOCK11_LSB _u(0)
#define SIO_SPINLOCK11_ACCESS "RO"
#define SIO_SPINLOCK11_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK12
// Description : Reading from a spinlock address will:
@ -1347,7 +1349,7 @@
#define SIO_SPINLOCK12_RESET _u(0x00000000)
#define SIO_SPINLOCK12_MSB _u(31)
#define SIO_SPINLOCK12_LSB _u(0)
#define SIO_SPINLOCK12_ACCESS "RO"
#define SIO_SPINLOCK12_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK13
// Description : Reading from a spinlock address will:
@ -1363,7 +1365,7 @@
#define SIO_SPINLOCK13_RESET _u(0x00000000)
#define SIO_SPINLOCK13_MSB _u(31)
#define SIO_SPINLOCK13_LSB _u(0)
#define SIO_SPINLOCK13_ACCESS "RO"
#define SIO_SPINLOCK13_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK14
// Description : Reading from a spinlock address will:
@ -1379,7 +1381,7 @@
#define SIO_SPINLOCK14_RESET _u(0x00000000)
#define SIO_SPINLOCK14_MSB _u(31)
#define SIO_SPINLOCK14_LSB _u(0)
#define SIO_SPINLOCK14_ACCESS "RO"
#define SIO_SPINLOCK14_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK15
// Description : Reading from a spinlock address will:
@ -1395,7 +1397,7 @@
#define SIO_SPINLOCK15_RESET _u(0x00000000)
#define SIO_SPINLOCK15_MSB _u(31)
#define SIO_SPINLOCK15_LSB _u(0)
#define SIO_SPINLOCK15_ACCESS "RO"
#define SIO_SPINLOCK15_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK16
// Description : Reading from a spinlock address will:
@ -1411,7 +1413,7 @@
#define SIO_SPINLOCK16_RESET _u(0x00000000)
#define SIO_SPINLOCK16_MSB _u(31)
#define SIO_SPINLOCK16_LSB _u(0)
#define SIO_SPINLOCK16_ACCESS "RO"
#define SIO_SPINLOCK16_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK17
// Description : Reading from a spinlock address will:
@ -1427,7 +1429,7 @@
#define SIO_SPINLOCK17_RESET _u(0x00000000)
#define SIO_SPINLOCK17_MSB _u(31)
#define SIO_SPINLOCK17_LSB _u(0)
#define SIO_SPINLOCK17_ACCESS "RO"
#define SIO_SPINLOCK17_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK18
// Description : Reading from a spinlock address will:
@ -1443,7 +1445,7 @@
#define SIO_SPINLOCK18_RESET _u(0x00000000)
#define SIO_SPINLOCK18_MSB _u(31)
#define SIO_SPINLOCK18_LSB _u(0)
#define SIO_SPINLOCK18_ACCESS "RO"
#define SIO_SPINLOCK18_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK19
// Description : Reading from a spinlock address will:
@ -1459,7 +1461,7 @@
#define SIO_SPINLOCK19_RESET _u(0x00000000)
#define SIO_SPINLOCK19_MSB _u(31)
#define SIO_SPINLOCK19_LSB _u(0)
#define SIO_SPINLOCK19_ACCESS "RO"
#define SIO_SPINLOCK19_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK20
// Description : Reading from a spinlock address will:
@ -1475,7 +1477,7 @@
#define SIO_SPINLOCK20_RESET _u(0x00000000)
#define SIO_SPINLOCK20_MSB _u(31)
#define SIO_SPINLOCK20_LSB _u(0)
#define SIO_SPINLOCK20_ACCESS "RO"
#define SIO_SPINLOCK20_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK21
// Description : Reading from a spinlock address will:
@ -1491,7 +1493,7 @@
#define SIO_SPINLOCK21_RESET _u(0x00000000)
#define SIO_SPINLOCK21_MSB _u(31)
#define SIO_SPINLOCK21_LSB _u(0)
#define SIO_SPINLOCK21_ACCESS "RO"
#define SIO_SPINLOCK21_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK22
// Description : Reading from a spinlock address will:
@ -1507,7 +1509,7 @@
#define SIO_SPINLOCK22_RESET _u(0x00000000)
#define SIO_SPINLOCK22_MSB _u(31)
#define SIO_SPINLOCK22_LSB _u(0)
#define SIO_SPINLOCK22_ACCESS "RO"
#define SIO_SPINLOCK22_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK23
// Description : Reading from a spinlock address will:
@ -1523,7 +1525,7 @@
#define SIO_SPINLOCK23_RESET _u(0x00000000)
#define SIO_SPINLOCK23_MSB _u(31)
#define SIO_SPINLOCK23_LSB _u(0)
#define SIO_SPINLOCK23_ACCESS "RO"
#define SIO_SPINLOCK23_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK24
// Description : Reading from a spinlock address will:
@ -1539,7 +1541,7 @@
#define SIO_SPINLOCK24_RESET _u(0x00000000)
#define SIO_SPINLOCK24_MSB _u(31)
#define SIO_SPINLOCK24_LSB _u(0)
#define SIO_SPINLOCK24_ACCESS "RO"
#define SIO_SPINLOCK24_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK25
// Description : Reading from a spinlock address will:
@ -1555,7 +1557,7 @@
#define SIO_SPINLOCK25_RESET _u(0x00000000)
#define SIO_SPINLOCK25_MSB _u(31)
#define SIO_SPINLOCK25_LSB _u(0)
#define SIO_SPINLOCK25_ACCESS "RO"
#define SIO_SPINLOCK25_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK26
// Description : Reading from a spinlock address will:
@ -1571,7 +1573,7 @@
#define SIO_SPINLOCK26_RESET _u(0x00000000)
#define SIO_SPINLOCK26_MSB _u(31)
#define SIO_SPINLOCK26_LSB _u(0)
#define SIO_SPINLOCK26_ACCESS "RO"
#define SIO_SPINLOCK26_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK27
// Description : Reading from a spinlock address will:
@ -1587,7 +1589,7 @@
#define SIO_SPINLOCK27_RESET _u(0x00000000)
#define SIO_SPINLOCK27_MSB _u(31)
#define SIO_SPINLOCK27_LSB _u(0)
#define SIO_SPINLOCK27_ACCESS "RO"
#define SIO_SPINLOCK27_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK28
// Description : Reading from a spinlock address will:
@ -1603,7 +1605,7 @@
#define SIO_SPINLOCK28_RESET _u(0x00000000)
#define SIO_SPINLOCK28_MSB _u(31)
#define SIO_SPINLOCK28_LSB _u(0)
#define SIO_SPINLOCK28_ACCESS "RO"
#define SIO_SPINLOCK28_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK29
// Description : Reading from a spinlock address will:
@ -1619,7 +1621,7 @@
#define SIO_SPINLOCK29_RESET _u(0x00000000)
#define SIO_SPINLOCK29_MSB _u(31)
#define SIO_SPINLOCK29_LSB _u(0)
#define SIO_SPINLOCK29_ACCESS "RO"
#define SIO_SPINLOCK29_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK30
// Description : Reading from a spinlock address will:
@ -1635,7 +1637,7 @@
#define SIO_SPINLOCK30_RESET _u(0x00000000)
#define SIO_SPINLOCK30_MSB _u(31)
#define SIO_SPINLOCK30_LSB _u(0)
#define SIO_SPINLOCK30_ACCESS "RO"
#define SIO_SPINLOCK30_ACCESS "RW"
// =============================================================================
// Register : SIO_SPINLOCK31
// Description : Reading from a spinlock address will:
@ -1651,6 +1653,7 @@
#define SIO_SPINLOCK31_RESET _u(0x00000000)
#define SIO_SPINLOCK31_MSB _u(31)
#define SIO_SPINLOCK31_LSB _u(0)
#define SIO_SPINLOCK31_ACCESS "RO"
#define SIO_SPINLOCK31_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_SIO_DEFINED
#endif // _HARDWARE_REGS_SIO_H

12
lib/rp2040/hardware/regs/spi.h → lib/pico-sdk/rp2040/hardware/regs/spi.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : SPI
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_SPI_DEFINED
#define HARDWARE_REGS_SPI_DEFINED
#ifndef _HARDWARE_REGS_SPI_H
#define _HARDWARE_REGS_SPI_H
// =============================================================================
// Register : SPI_SSPCR0
// Description : Control register 0, SSPCR0 on page 3-4
@ -518,4 +519,5 @@
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0)
#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SPI_DEFINED
#endif // _HARDWARE_REGS_SPI_H

23
lib/rp2040/hardware/regs/ssi.h → lib/pico-sdk/rp2040/hardware/regs/ssi.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -69,8 +71,8 @@
// - Serial clock phase – capture on first edge of serial-clock
// directly after reset.
// =============================================================================
#ifndef HARDWARE_REGS_SSI_DEFINED
#define HARDWARE_REGS_SSI_DEFINED
#ifndef _HARDWARE_REGS_SSI_H
#define _HARDWARE_REGS_SSI_H
// =============================================================================
// Register : SSI_CTRLR0
// Description : Control register 0
@ -88,8 +90,7 @@
// -----------------------------------------------------------------------------
// Field : SSI_CTRLR0_SPI_FRF
// Description : SPI frame format
// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK,
// full-duplex
// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex
// 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex
// 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex
#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0)
@ -140,8 +141,7 @@
// 0x0 -> Both transmit and receive
// 0x1 -> Transmit only (not for FRF == 0, standard SPI mode)
// 0x2 -> Receive only (not for FRF == 0, standard SPI mode)
// 0x3 -> EEPROM read mode (TX then RX; RX starts after control
// data TX'd)
// 0x3 -> EEPROM read mode (TX then RX; RX starts after control data TX'd)
#define SSI_CTRLR0_TMOD_RESET _u(0x0)
#define SSI_CTRLR0_TMOD_BITS _u(0x00000300)
#define SSI_CTRLR0_TMOD_MSB _u(9)
@ -779,10 +779,8 @@
// Field : SSI_SPI_CTRLR0_TRANS_TYPE
// Description : Address and instruction transfer format
// 0x0 -> Command and address both in standard SPI frame format
// 0x1 -> Command in standard SPI format, address in format
// specified by FRF
// 0x2 -> Command and address both in format specified by FRF
// (e.g. Dual-SPI)
// 0x1 -> Command in standard SPI format, address in format specified by FRF
// 0x2 -> Command and address both in format specified by FRF (e.g. Dual-SPI)
#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0)
#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003)
#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1)
@ -806,4 +804,5 @@
#define SSI_TXD_DRIVE_EDGE_TDE_LSB _u(0)
#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_SSI_DEFINED
#endif // _HARDWARE_REGS_SSI_H

19
lib/rp2040/hardware/regs/syscfg.h → lib/pico-sdk/rp2040/hardware/regs/syscfg.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,8 +11,8 @@
// Bus type : apb
// Description : Register block for various chip control signals
// =============================================================================
#ifndef HARDWARE_REGS_SYSCFG_DEFINED
#define HARDWARE_REGS_SYSCFG_DEFINED
#ifndef _HARDWARE_REGS_SYSCFG_H
#define _HARDWARE_REGS_SYSCFG_H
// =============================================================================
// Register : SYSCFG_PROC0_NMI_MASK
// Description : Processor core 0 NMI source mask
@ -191,7 +193,6 @@
#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_ROM
// Description : None
#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080)
#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7)
@ -199,7 +200,6 @@
#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_USB
// Description : None
#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040)
#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6)
@ -207,7 +207,6 @@
#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM5
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
@ -215,7 +214,6 @@
#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM4
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
@ -223,7 +221,6 @@
#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM3
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
@ -231,7 +228,6 @@
#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM2
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
@ -239,7 +235,6 @@
#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM1
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
@ -247,11 +242,11 @@
#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM0
// Description : None
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_SYSCFG_DEFINED
#endif // _HARDWARE_REGS_SYSCFG_H

19
lib/rp2040/hardware/regs/sysinfo.h → lib/pico-sdk/rp2040/hardware/regs/sysinfo.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : SYSINFO
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_SYSINFO_DEFINED
#define HARDWARE_REGS_SYSINFO_DEFINED
#ifndef _HARDWARE_REGS_SYSINFO_H
#define _HARDWARE_REGS_SYSINFO_H
// =============================================================================
// Register : SYSINFO_CHIP_ID
// Description : JEDEC JEP-106 compliant chip identifier.
@ -19,7 +20,6 @@
#define SYSINFO_CHIP_ID_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_REVISION
// Description : None
#define SYSINFO_CHIP_ID_REVISION_RESET "-"
#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000)
#define SYSINFO_CHIP_ID_REVISION_MSB _u(31)
@ -27,7 +27,6 @@
#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_PART
// Description : None
#define SYSINFO_CHIP_ID_PART_RESET "-"
#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000)
#define SYSINFO_CHIP_ID_PART_MSB _u(27)
@ -35,7 +34,6 @@
#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_MANUFACTURER
// Description : None
#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff)
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11)
@ -50,7 +48,6 @@
#define SYSINFO_PLATFORM_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_ASIC
// Description : None
#define SYSINFO_PLATFORM_ASIC_RESET _u(0x0)
#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002)
#define SYSINFO_PLATFORM_ASIC_MSB _u(1)
@ -58,7 +55,6 @@
#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_FPGA
// Description : None
#define SYSINFO_PLATFORM_FPGA_RESET _u(0x0)
#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001)
#define SYSINFO_PLATFORM_FPGA_MSB _u(0)
@ -67,11 +63,12 @@
// =============================================================================
// Register : SYSINFO_GITREF_RP2040
// Description : Git hash of the chip source. Used to identify chip version.
#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040)
#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000010)
#define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff)
#define SYSINFO_GITREF_RP2040_RESET "-"
#define SYSINFO_GITREF_RP2040_MSB _u(31)
#define SYSINFO_GITREF_RP2040_LSB _u(0)
#define SYSINFO_GITREF_RP2040_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_SYSINFO_DEFINED
#endif // _HARDWARE_REGS_SYSINFO_H

11
lib/rp2040/hardware/regs/tbman.h → lib/pico-sdk/rp2040/hardware/regs/tbman.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,8 +12,8 @@
// Description : Testbench manager. Allows the programmer to know what
// platform their software is running on.
// =============================================================================
#ifndef HARDWARE_REGS_TBMAN_DEFINED
#define HARDWARE_REGS_TBMAN_DEFINED
#ifndef _HARDWARE_REGS_TBMAN_H
#define _HARDWARE_REGS_TBMAN_H
// =============================================================================
// Register : TBMAN_PLATFORM
// Description : Indicates the type of platform in use
@ -35,4 +37,5 @@
#define TBMAN_PLATFORM_ASIC_LSB _u(0)
#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TBMAN_DEFINED
#endif // _HARDWARE_REGS_TBMAN_H

27
lib/rp2040/hardware/regs/timer.h → lib/pico-sdk/rp2040/hardware/regs/timer.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -25,8 +27,8 @@
// To clear the interrupt write a 1 to the corresponding
// alarm_irq
// =============================================================================
#ifndef HARDWARE_REGS_TIMER_DEFINED
#define HARDWARE_REGS_TIMER_DEFINED
#ifndef _HARDWARE_REGS_TIMER_H
#define _HARDWARE_REGS_TIMER_H
// =============================================================================
// Register : TIMER_TIMEHW
// Description : Write to bits 63:32 of time
@ -184,7 +186,6 @@
#define TIMER_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_3
// Description : None
#define TIMER_INTR_ALARM_3_RESET _u(0x0)
#define TIMER_INTR_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTR_ALARM_3_MSB _u(3)
@ -192,7 +193,6 @@
#define TIMER_INTR_ALARM_3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_2
// Description : None
#define TIMER_INTR_ALARM_2_RESET _u(0x0)
#define TIMER_INTR_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTR_ALARM_2_MSB _u(2)
@ -200,7 +200,6 @@
#define TIMER_INTR_ALARM_2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_1
// Description : None
#define TIMER_INTR_ALARM_1_RESET _u(0x0)
#define TIMER_INTR_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTR_ALARM_1_MSB _u(1)
@ -208,7 +207,6 @@
#define TIMER_INTR_ALARM_1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_0
// Description : None
#define TIMER_INTR_ALARM_0_RESET _u(0x0)
#define TIMER_INTR_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTR_ALARM_0_MSB _u(0)
@ -222,7 +220,6 @@
#define TIMER_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_3
// Description : None
#define TIMER_INTE_ALARM_3_RESET _u(0x0)
#define TIMER_INTE_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTE_ALARM_3_MSB _u(3)
@ -230,7 +227,6 @@
#define TIMER_INTE_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_2
// Description : None
#define TIMER_INTE_ALARM_2_RESET _u(0x0)
#define TIMER_INTE_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTE_ALARM_2_MSB _u(2)
@ -238,7 +234,6 @@
#define TIMER_INTE_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_1
// Description : None
#define TIMER_INTE_ALARM_1_RESET _u(0x0)
#define TIMER_INTE_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTE_ALARM_1_MSB _u(1)
@ -246,7 +241,6 @@
#define TIMER_INTE_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_0
// Description : None
#define TIMER_INTE_ALARM_0_RESET _u(0x0)
#define TIMER_INTE_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTE_ALARM_0_MSB _u(0)
@ -260,7 +254,6 @@
#define TIMER_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_3
// Description : None
#define TIMER_INTF_ALARM_3_RESET _u(0x0)
#define TIMER_INTF_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTF_ALARM_3_MSB _u(3)
@ -268,7 +261,6 @@
#define TIMER_INTF_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_2
// Description : None
#define TIMER_INTF_ALARM_2_RESET _u(0x0)
#define TIMER_INTF_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTF_ALARM_2_MSB _u(2)
@ -276,7 +268,6 @@
#define TIMER_INTF_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_1
// Description : None
#define TIMER_INTF_ALARM_1_RESET _u(0x0)
#define TIMER_INTF_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTF_ALARM_1_MSB _u(1)
@ -284,7 +275,6 @@
#define TIMER_INTF_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_0
// Description : None
#define TIMER_INTF_ALARM_0_RESET _u(0x0)
#define TIMER_INTF_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTF_ALARM_0_MSB _u(0)
@ -298,7 +288,6 @@
#define TIMER_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_3
// Description : None
#define TIMER_INTS_ALARM_3_RESET _u(0x0)
#define TIMER_INTS_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTS_ALARM_3_MSB _u(3)
@ -306,7 +295,6 @@
#define TIMER_INTS_ALARM_3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_2
// Description : None
#define TIMER_INTS_ALARM_2_RESET _u(0x0)
#define TIMER_INTS_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTS_ALARM_2_MSB _u(2)
@ -314,7 +302,6 @@
#define TIMER_INTS_ALARM_2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_1
// Description : None
#define TIMER_INTS_ALARM_1_RESET _u(0x0)
#define TIMER_INTS_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTS_ALARM_1_MSB _u(1)
@ -322,11 +309,11 @@
#define TIMER_INTS_ALARM_1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_0
// Description : None
#define TIMER_INTS_ALARM_0_RESET _u(0x0)
#define TIMER_INTS_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTS_ALARM_0_MSB _u(0)
#define TIMER_INTS_ALARM_0_LSB _u(0)
#define TIMER_INTS_ALARM_0_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_TIMER_DEFINED
#endif // _HARDWARE_REGS_TIMER_H

12
lib/rp2040/hardware/regs/uart.h → lib/pico-sdk/rp2040/hardware/regs/uart.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : UART
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_UART_DEFINED
#define HARDWARE_REGS_UART_DEFINED
#ifndef _HARDWARE_REGS_UART_H
#define _HARDWARE_REGS_UART_H
// =============================================================================
// Register : UART_UARTDR
// Description : Data Register, UARTDR
@ -1145,4 +1146,5 @@
#define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0)
#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_UART_DEFINED
#endif // _HARDWARE_REGS_UART_H

336
lib/rp2040/hardware/regs/usb.h → lib/pico-sdk/rp2040/hardware/regs/usb.h
View File

File diff suppressed because it is too large Load Diff

6753
lib/pico-sdk/rp2040/hardware/regs/usb_device_dpram.h Normal file
View File

File diff suppressed because it is too large Load Diff

11
lib/rp2040/hardware/regs/vreg_and_chip_reset.h → lib/pico-sdk/rp2040/hardware/regs/vreg_and_chip_reset.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -10,8 +12,8 @@
// Description : control and status for on-chip voltage regulator and chip
// level reset subsystem
// =============================================================================
#ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
#define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
#ifndef _HARDWARE_REGS_VREG_AND_CHIP_RESET_H
#define _HARDWARE_REGS_VREG_AND_CHIP_RESET_H
// =============================================================================
// Register : VREG_AND_CHIP_RESET_VREG
// Description : Voltage regulator control and status
@ -148,4 +150,5 @@
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8)
#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
// =============================================================================
#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
#endif // _HARDWARE_REGS_VREG_AND_CHIP_RESET_H

14
lib/rp2040/hardware/regs/watchdog.h → lib/pico-sdk/rp2040/hardware/regs/watchdog.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -7,10 +9,9 @@
// Register block : WATCHDOG
// Version : 1
// Bus type : apb
// Description : None
// =============================================================================
#ifndef HARDWARE_REGS_WATCHDOG_DEFINED
#define HARDWARE_REGS_WATCHDOG_DEFINED
#ifndef _HARDWARE_REGS_WATCHDOG_H
#define _HARDWARE_REGS_WATCHDOG_H
// =============================================================================
// Register : WATCHDOG_CTRL
// Description : Watchdog control
@ -89,7 +90,6 @@
#define WATCHDOG_REASON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_FORCE
// Description : None
#define WATCHDOG_REASON_FORCE_RESET _u(0x0)
#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002)
#define WATCHDOG_REASON_FORCE_MSB _u(1)
@ -97,7 +97,6 @@
#define WATCHDOG_REASON_FORCE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_TIMER
// Description : None
#define WATCHDOG_REASON_TIMER_RESET _u(0x0)
#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001)
#define WATCHDOG_REASON_TIMER_MSB _u(0)
@ -223,4 +222,5 @@
#define WATCHDOG_TICK_CYCLES_LSB _u(0)
#define WATCHDOG_TICK_CYCLES_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_WATCHDOG_DEFINED
#endif // _HARDWARE_REGS_WATCHDOG_H

15
lib/rp2040/hardware/regs/xip.h → lib/pico-sdk/rp2040/hardware/regs/xip.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,8 +11,8 @@
// Bus type : ahb
// Description : QSPI flash execute-in-place block
// =============================================================================
#ifndef HARDWARE_REGS_XIP_DEFINED
#define HARDWARE_REGS_XIP_DEFINED
#ifndef _HARDWARE_REGS_XIP_H
#define _HARDWARE_REGS_XIP_H
// =============================================================================
// Register : XIP_CTRL
// Description : Cache control
@ -159,8 +161,8 @@
// a linear data block from flash to the streaming FIFO.
// Decrements automatically (1 at a time) as the stream
// progresses, and halts on reaching 0.
// Write 0 to halt an in-progress stream, and discard any
// in-flight
// Write 0 to halt an in-progress stream, and discard any in-
// flight
// read, so that a new stream can immediately be started (after
// draining the FIFO and reinitialising STREAM_ADDR)
#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
@ -184,4 +186,5 @@
#define XIP_STREAM_FIFO_LSB _u(0)
#define XIP_STREAM_FIFO_ACCESS "RF"
// =============================================================================
#endif // HARDWARE_REGS_XIP_DEFINED
#endif // _HARDWARE_REGS_XIP_H

32
lib/rp2040/hardware/regs/xosc.h → lib/pico-sdk/rp2040/hardware/regs/xosc.h
View File

@ -1,5 +1,7 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,8 +11,8 @@
// Bus type : apb
// Description : Controls the crystal oscillator
// =============================================================================
#ifndef HARDWARE_REGS_XOSC_DEFINED
#define HARDWARE_REGS_XOSC_DEFINED
#ifndef _HARDWARE_REGS_XOSC_H
#define _HARDWARE_REGS_XOSC_H
// =============================================================================
// Register : XOSC_CTRL
// Description : Crystal Oscillator Control
@ -22,9 +24,9 @@
// Description : On power-up this field is initialised to DISABLE and the chip
// runs from the ROSC.
// If the chip has subsequently been programmed to run from the
// XOSC then setting this field to DISABLE may lock-up the chip.
// If this is a concern then run the clk_ref from the ROSC and
// enable the clk_sys RESUS feature.
// XOSC then DISABLE may lock-up the chip. If this is a concern
// then run the clk_ref from the ROSC and enable the clk_sys RESUS
// feature.
// The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will enable the
// oscillator.
@ -39,7 +41,9 @@
#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_FREQ_RANGE
// Description : Frequency range. This resets to 0xAA0 and cannot be changed.
// Description : Frequency range. An invalid setting will retain the previous
// value. The actual value being used can be read from
// STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed.
// 0xaa0 -> 1_15MHZ
// 0xaa1 -> RESERVED_1
// 0xaa2 -> RESERVED_2
@ -107,9 +111,9 @@
// This is used to save power by pausing the XOSC
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// WARNING: stop the PLLs before selecting dormant mode
// WARNING: setup the irq before selecting dormant mode
// 0x636f6d61 -> DORMANT
// Warning: stop the PLLs before selecting dormant mode
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> dormant
// 0x77616b65 -> WAKE
#define XOSC_DORMANT_OFFSET _u(0x00000008)
#define XOSC_DORMANT_BITS _u(0xffffffff)
@ -128,7 +132,7 @@
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4. This is of little value to
// the user given that the delay can be programmed directly
// the user given that the delay can be programmed directly.
#define XOSC_STARTUP_X4_RESET "-"
#define XOSC_STARTUP_X4_BITS _u(0x00100000)
#define XOSC_STARTUP_X4_MSB _u(20)
@ -136,7 +140,8 @@
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
// Description : in multiples of 256*xtal_period
// Description : in multiples of 256*xtal_period. The reset value of 0xc4
// corresponds to approx 50 000 cycles.
#define XOSC_STARTUP_DELAY_RESET "-"
#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
#define XOSC_STARTUP_DELAY_MSB _u(13)
@ -156,4 +161,5 @@
#define XOSC_COUNT_LSB _u(0)
#define XOSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // HARDWARE_REGS_XOSC_DEFINED
#endif // _HARDWARE_REGS_XOSC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_ADC_H
#define _HARDWARE_STRUCTS_ADC_H
/**
* \file rp2040/adc.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/adc.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(ADC_CS_OFFSET) // ADC_CS
// ADC Control and Status
// 0x001f0000 [20:16] RROBIN (0x00) Round-robin sampling
// 0x00007000 [14:12] AINSEL (0x0) Select analog mux input
// 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error
// 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;...
// 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion
// 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1
// 0x00000004 [2] START_ONCE (0) Start a single conversion
// 0x00000002 [1] TS_EN (0) Power on temperature sensor
// 0x00000001 [0] EN (0) Power on ADC and enable its clock
io_rw_32 cs;
_REG_(ADC_RESULT_OFFSET) // ADC_RESULT
// Result of most recent ADC conversion
// 0x00000fff [11:0] RESULT (0x000)
io_ro_32 result;
_REG_(ADC_FCS_OFFSET) // ADC_FCS
// FIFO control and status
// 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold
// 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO
// 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed
// 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed
// 0x00000200 [9] FULL (0)
// 0x00000100 [8] EMPTY (0)
// 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data
// 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside...
// 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size
// 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion
io_rw_32 fcs;
_REG_(ADC_FIFO_OFFSET) // ADC_FIFO
// Conversion result FIFO
// 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error
// 0x00000fff [11:0] VAL (-)
io_ro_32 fifo;
_REG_(ADC_DIV_OFFSET) // ADC_DIV
// Clock divider
// 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor
// 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor
io_rw_32 div;
_REG_(ADC_INTR_OFFSET) // ADC_INTR
// Raw Interrupts
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_ro_32 intr;
_REG_(ADC_INTE_OFFSET) // ADC_INTE
// Interrupt Enable
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_rw_32 inte;
_REG_(ADC_INTF_OFFSET) // ADC_INTF
// Interrupt Force
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_rw_32 intf;
_REG_(ADC_INTS_OFFSET) // ADC_INTS
// Interrupt status after masking & forcing
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_ro_32 ints;
} adc_hw_t;
#define adc_hw ((adc_hw_t *)ADC_BASE)
static_assert(sizeof (adc_hw_t) == 0x0024, "");
#endif // _HARDWARE_STRUCTS_ADC_H

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@ -0,0 +1,9 @@
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/busctrl.h"
#define bus_ctrl_hw busctrl_hw

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_BUSCTRL_H
#define _HARDWARE_STRUCTS_BUSCTRL_H
/**
* \file rp2040/busctrl.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/busctrl.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/** \brief Bus fabric performance counters on RP2040 (used as typedef \ref bus_ctrl_perf_counter_t)
* \ingroup hardware_busctrl
*/
typedef enum bus_ctrl_perf_counter_rp2040 {
arbiter_rom_perf_event_access = 19,
arbiter_rom_perf_event_access_contested = 18,
arbiter_xip_main_perf_event_access = 17,
arbiter_xip_main_perf_event_access_contested = 16,
arbiter_sram0_perf_event_access = 15,
arbiter_sram0_perf_event_access_contested = 14,
arbiter_sram1_perf_event_access = 13,
arbiter_sram1_perf_event_access_contested = 12,
arbiter_sram2_perf_event_access = 11,
arbiter_sram2_perf_event_access_contested = 10,
arbiter_sram3_perf_event_access = 9,
arbiter_sram3_perf_event_access_contested = 8,
arbiter_sram4_perf_event_access = 7,
arbiter_sram4_perf_event_access_contested = 6,
arbiter_sram5_perf_event_access = 5,
arbiter_sram5_perf_event_access_contested = 4,
arbiter_fastperi_perf_event_access = 3,
arbiter_fastperi_perf_event_access_contested = 2,
arbiter_apb_perf_event_access = 1,
arbiter_apb_perf_event_access_contested = 0
} bus_ctrl_perf_counter_t;
typedef struct {
_REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
// Bus fabric performance counter 0
// 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 +
io_rw_32 value;
_REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
// Bus fabric performance event select for PERFCTR0
// 0x0000001f [4:0] PERFSEL0 (0x1f) Select an event for PERFCTR0
io_rw_32 sel;
} bus_ctrl_perf_hw_t;
typedef struct {
_REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
// Set the priority of each master for bus arbitration
// 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority
// 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority
// 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority
// 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority
io_rw_32 priority;
_REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
// Bus priority acknowledge
// 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new...
io_ro_32 priority_ack;
bus_ctrl_perf_hw_t counter[4];
} busctrl_hw_t;
#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE)
static_assert(sizeof (busctrl_hw_t) == 0x0028, "");
#endif // _HARDWARE_STRUCTS_BUSCTRL_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_CLOCKS_H
#define _HARDWARE_STRUCTS_CLOCKS_H
/**
* \file rp2040/clocks.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/clocks.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/** \brief Clock numbers on RP2040 (used as typedef \ref clock_num_t)
* \ingroup hardware_clocks
*/
/// \tag::clkenum[]
typedef enum clock_num_rp2040 {
clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source
clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source
clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source
clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source
clk_ref = 4, ///< Select CLK_REF as clock source
clk_sys = 5, ///< Select CLK_SYS as clock source
clk_peri = 6, ///< Select CLK_PERI as clock source
clk_usb = 7, ///< Select CLK_USB as clock source
clk_adc = 8, ///< Select CLK_ADC as clock source
clk_rtc = 9, ///< Select CLK_RTC as clock source
CLK_COUNT
} clock_num_t;
/// \end::clkenum[]
/** \brief Clock destination numbers on RP2040 (used as typedef \ref clock_dest_num_t)
* \ingroup hardware_clocks
*/
typedef enum clock_dest_num_rp2040 {
CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination
CLK_DEST_ADC_ADC = 1, ///< Select ADC_ADC as clock destination
CLK_DEST_SYS_ADC = 2, ///< Select SYS_ADC as clock destination
CLK_DEST_SYS_BUSCTRL = 3, ///< Select SYS_BUSCTRL as clock destination
CLK_DEST_SYS_BUSFABRIC = 4, ///< Select SYS_BUSFABRIC as clock destination
CLK_DEST_SYS_DMA = 5, ///< Select SYS_DMA as clock destination
CLK_DEST_SYS_I2C0 = 6, ///< Select SYS_I2C0 as clock destination
CLK_DEST_SYS_I2C1 = 7, ///< Select SYS_I2C1 as clock destination
CLK_DEST_SYS_IO = 8, ///< Select SYS_IO as clock destination
CLK_DEST_SYS_JTAG = 9, ///< Select SYS_JTAG as clock destination
CLK_DEST_SYS_VREG_AND_CHIP_RESET = 10, ///< Select SYS_VREG_AND_CHIP_RESET as clock destination
CLK_DEST_SYS_PADS = 11, ///< Select SYS_PADS as clock destination
CLK_DEST_SYS_PIO0 = 12, ///< Select SYS_PIO0 as clock destination
CLK_DEST_SYS_PIO1 = 13, ///< Select SYS_PIO1 as clock destination
CLK_DEST_SYS_PLL_SYS = 14, ///< Select SYS_PLL_SYS as clock destination
CLK_DEST_SYS_PLL_USB = 15, ///< Select SYS_PLL_USB as clock destination
CLK_DEST_SYS_PSM = 16, ///< Select SYS_PSM as clock destination
CLK_DEST_SYS_PWM = 17, ///< Select SYS_PWM as clock destination
CLK_DEST_SYS_RESETS = 18, ///< Select SYS_RESETS as clock destination
CLK_DEST_SYS_ROM = 19, ///< Select SYS_ROM as clock destination
CLK_DEST_SYS_ROSC = 20, ///< Select SYS_ROSC as clock destination
CLK_DEST_RTC_RTC = 21, ///< Select RTC_RTC as clock destination
CLK_DEST_SYS_RTC = 22, ///< Select SYS_RTC as clock destination
CLK_DEST_SYS_SIO = 23, ///< Select SYS_SIO as clock destination
CLK_DEST_PERI_SPI0 = 24, ///< Select PERI_SPI0 as clock destination
CLK_DEST_SYS_SPI0 = 25, ///< Select SYS_SPI0 as clock destination
CLK_DEST_PERI_SPI1 = 26, ///< Select PERI_SPI1 as clock destination
CLK_DEST_SYS_SPI1 = 27, ///< Select SYS_SPI1 as clock destination
CLK_DEST_SYS_SRAM0 = 28, ///< Select SYS_SRAM0 as clock destination
CLK_DEST_SYS_SRAM1 = 29, ///< Select SYS_SRAM1 as clock destination
CLK_DEST_SYS_SRAM2 = 30, ///< Select SYS_SRAM2 as clock destination
CLK_DEST_SYS_SRAM3 = 31, ///< Select SYS_SRAM3 as clock destination
CLK_DEST_SYS_SRAM4 = 32, ///< Select SYS_SRAM4 as clock destination
CLK_DEST_SYS_SRAM5 = 33, ///< Select SYS_SRAM5 as clock destination
CLK_DEST_SYS_SYSCFG = 34, ///< Select SYS_SYSCFG as clock destination
CLK_DEST_SYS_SYSINFO = 35, ///< Select SYS_SYSINFO as clock destination
CLK_DEST_SYS_TBMAN = 36, ///< Select SYS_TBMAN as clock destination
CLK_DEST_SYS_TIMER = 37, ///< Select SYS_TIMER as clock destination
CLK_DEST_PERI_UART0 = 38, ///< Select PERI_UART0 as clock destination
CLK_DEST_SYS_UART0 = 39, ///< Select SYS_UART0 as clock destination
CLK_DEST_PERI_UART1 = 40, ///< Select PERI_UART1 as clock destination
CLK_DEST_SYS_UART1 = 41, ///< Select SYS_UART1 as clock destination
CLK_DEST_SYS_USBCTRL = 42, ///< Select SYS_USBCTRL as clock destination
CLK_DEST_USB_USBCTRL = 43, ///< Select USB_USBCTRL as clock destination
CLK_DEST_SYS_WATCHDOG = 44, ///< Select SYS_WATCHDOG as clock destination
CLK_DEST_SYS_XIP = 45, ///< Select SYS_XIP as clock destination
CLK_DEST_SYS_XOSC = 46, ///< Select SYS_XOSC as clock destination
NUM_CLOCK_DESTINATIONS
} clock_dest_num_t;
/// \tag::clock_hw[]
typedef struct {
_REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
// Clock control, can be changed on-the-fly (except for auxsrc)
// 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by...
// 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the...
// 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors
// 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly
// 0x00000400 [10] KILL (0) Asynchronously kills the clock generator
// 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching
io_rw_32 ctrl;
_REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
// Clock divisor, can be changed on-the-fly
// 0xffffff00 [31:8] INT (0x000001) Integer component of the divisor, 0 -> divide by 2^16
// 0x000000ff [7:0] FRAC (0x00) Fractional component of the divisor
io_rw_32 div;
_REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
// Indicates which SRC is currently selected by the glitchless mux (one-hot)
// 0xffffffff [31:0] CLK_GPOUT0_SELECTED (0x00000001) This slice does not have a glitchless mux (only the...
io_ro_32 selected;
} clock_hw_t;
/// \end::clock_hw[]
typedef struct {
_REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
// 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it...
// 0x00001000 [12] FRCE (0) Force a resus, for test purposes only
// 0x00000100 [8] ENABLE (0) Enable resus
// 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles +
io_rw_32 ctrl;
_REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
// 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send...
io_ro_32 status;
} clock_resus_hw_t;
typedef struct {
_REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
// Reference clock frequency in kHz
// 0x000fffff [19:0] FC0_REF_KHZ (0x00000)
io_rw_32 ref_khz;
_REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
// Minimum pass frequency in kHz
// 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000)
io_rw_32 min_khz;
_REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
// Maximum pass frequency in kHz
// 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff)
io_rw_32 max_khz;
_REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
// Delays the start of frequency counting to allow the mux to settle +
// 0x00000007 [2:0] FC0_DELAY (0x1)
io_rw_32 delay;
_REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
// The test interval is 0
// 0x0000000f [3:0] FC0_INTERVAL (0x8)
io_rw_32 interval;
_REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
// Clock sent to frequency counter, set to 0 when not required +
// 0x000000ff [7:0] FC0_SRC (0x00)
io_rw_32 src;
_REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
// Frequency counter status
// 0x10000000 [28] DIED (0) Test clock stopped during test
// 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1
// 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1
// 0x00010000 [16] FAIL (0) Test failed
// 0x00001000 [12] WAITING (0) Waiting for test clock to start
// 0x00000100 [8] RUNNING (0) Test running
// 0x00000010 [4] DONE (0) Test complete
// 0x00000001 [0] PASS (0) Test passed
io_ro_32 status;
_REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
// Result of frequency measurement, only valid when status_done=1
// 0x3fffffe0 [29:5] KHZ (0x0000000)
// 0x0000001f [4:0] FRAC (0x00)
io_ro_32 result;
} fc_hw_t;
typedef struct {
clock_hw_t clk[10];
clock_resus_hw_t resus;
fc_hw_t fc0;
union {
struct {
_REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
// enable clock in wake mode
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
// 0x08000000 [27] CLK_SYS_SPI1 (1)
// 0x04000000 [26] CLK_PERI_SPI1 (1)
// 0x02000000 [25] CLK_SYS_SPI0 (1)
// 0x01000000 [24] CLK_PERI_SPI0 (1)
// 0x00800000 [23] CLK_SYS_SIOB (1)
// 0x00400000 [22] CLK_SYS_RTC (1)
// 0x00200000 [21] CLK_RTC_RTC (1)
// 0x00100000 [20] CLK_SYS_ROSC (1)
// 0x00080000 [19] CLK_SYS_ROM (1)
// 0x00040000 [18] CLK_SYS_RESETS (1)
// 0x00020000 [17] CLK_SYS_PWM (1)
// 0x00010000 [16] CLK_SYS_POWER (1)
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
// 0x00002000 [13] CLK_SYS_PIO1 (1)
// 0x00001000 [12] CLK_SYS_PIO0 (1)
// 0x00000800 [11] CLK_SYS_PADS (1)
// 0x00000400 [10] CLK_SYS_LDO_POR (1)
// 0x00000200 [9] CLK_SYS_JTAG (1)
// 0x00000100 [8] CLK_SYS_IO (1)
// 0x00000080 [7] CLK_SYS_I2C1 (1)
// 0x00000040 [6] CLK_SYS_I2C0 (1)
// 0x00000020 [5] CLK_SYS_DMA (1)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
// 0x00000004 [2] CLK_SYS_ADC0 (1)
// 0x00000002 [1] CLK_ADC_ADC0 (1)
// 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1)
io_rw_32 wake_en0;
_REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
// enable clock in wake mode
// 0x00004000 [14] CLK_SYS_XOSC (1)
// 0x00002000 [13] CLK_SYS_XIP (1)
// 0x00001000 [12] CLK_SYS_WATCHDOG (1)
// 0x00000800 [11] CLK_USB_USBCTRL (1)
// 0x00000400 [10] CLK_SYS_USBCTRL (1)
// 0x00000200 [9] CLK_SYS_UART1 (1)
// 0x00000100 [8] CLK_PERI_UART1 (1)
// 0x00000080 [7] CLK_SYS_UART0 (1)
// 0x00000040 [6] CLK_PERI_UART0 (1)
// 0x00000020 [5] CLK_SYS_TIMER (1)
// 0x00000010 [4] CLK_SYS_TBMAN (1)
// 0x00000008 [3] CLK_SYS_SYSINFO (1)
// 0x00000004 [2] CLK_SYS_SYSCFG (1)
// 0x00000002 [1] CLK_SYS_SRAM5 (1)
// 0x00000001 [0] CLK_SYS_SRAM4 (1)
io_rw_32 wake_en1;
};
// (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes)
_REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
// enable clock in wake mode
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
// 0x08000000 [27] CLK_SYS_SPI1 (1)
// 0x04000000 [26] CLK_PERI_SPI1 (1)
// 0x02000000 [25] CLK_SYS_SPI0 (1)
// 0x01000000 [24] CLK_PERI_SPI0 (1)
// 0x00800000 [23] CLK_SYS_SIO (1)
// 0x00400000 [22] CLK_SYS_RTC (1)
// 0x00200000 [21] CLK_RTC_RTC (1)
// 0x00100000 [20] CLK_SYS_ROSC (1)
// 0x00080000 [19] CLK_SYS_ROM (1)
// 0x00040000 [18] CLK_SYS_RESETS (1)
// 0x00020000 [17] CLK_SYS_PWM (1)
// 0x00010000 [16] CLK_SYS_PSM (1)
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
// 0x00002000 [13] CLK_SYS_PIO1 (1)
// 0x00001000 [12] CLK_SYS_PIO0 (1)
// 0x00000800 [11] CLK_SYS_PADS (1)
// 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1)
// 0x00000200 [9] CLK_SYS_JTAG (1)
// 0x00000100 [8] CLK_SYS_IO (1)
// 0x00000080 [7] CLK_SYS_I2C1 (1)
// 0x00000040 [6] CLK_SYS_I2C0 (1)
// 0x00000020 [5] CLK_SYS_DMA (1)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
// 0x00000004 [2] CLK_SYS_ADC (1)
// 0x00000002 [1] CLK_ADC_ADC (1)
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
io_rw_32 wake_en[2];
};
union {
struct {
_REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
// enable clock in sleep mode
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
// 0x08000000 [27] CLK_SYS_SPI1 (1)
// 0x04000000 [26] CLK_PERI_SPI1 (1)
// 0x02000000 [25] CLK_SYS_SPI0 (1)
// 0x01000000 [24] CLK_PERI_SPI0 (1)
// 0x00800000 [23] CLK_SYS_SIOB (1)
// 0x00400000 [22] CLK_SYS_RTC (1)
// 0x00200000 [21] CLK_RTC_RTC (1)
// 0x00100000 [20] CLK_SYS_ROSC (1)
// 0x00080000 [19] CLK_SYS_ROM (1)
// 0x00040000 [18] CLK_SYS_RESETS (1)
// 0x00020000 [17] CLK_SYS_PWM (1)
// 0x00010000 [16] CLK_SYS_POWER (1)
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
// 0x00002000 [13] CLK_SYS_PIO1 (1)
// 0x00001000 [12] CLK_SYS_PIO0 (1)
// 0x00000800 [11] CLK_SYS_PADS (1)
// 0x00000400 [10] CLK_SYS_LDO_POR (1)
// 0x00000200 [9] CLK_SYS_JTAG (1)
// 0x00000100 [8] CLK_SYS_IO (1)
// 0x00000080 [7] CLK_SYS_I2C1 (1)
// 0x00000040 [6] CLK_SYS_I2C0 (1)
// 0x00000020 [5] CLK_SYS_DMA (1)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
// 0x00000004 [2] CLK_SYS_ADC0 (1)
// 0x00000002 [1] CLK_ADC_ADC0 (1)
// 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1)
io_rw_32 sleep_en0;
_REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
// enable clock in sleep mode
// 0x00004000 [14] CLK_SYS_XOSC (1)
// 0x00002000 [13] CLK_SYS_XIP (1)
// 0x00001000 [12] CLK_SYS_WATCHDOG (1)
// 0x00000800 [11] CLK_USB_USBCTRL (1)
// 0x00000400 [10] CLK_SYS_USBCTRL (1)
// 0x00000200 [9] CLK_SYS_UART1 (1)
// 0x00000100 [8] CLK_PERI_UART1 (1)
// 0x00000080 [7] CLK_SYS_UART0 (1)
// 0x00000040 [6] CLK_PERI_UART0 (1)
// 0x00000020 [5] CLK_SYS_TIMER (1)
// 0x00000010 [4] CLK_SYS_TBMAN (1)
// 0x00000008 [3] CLK_SYS_SYSINFO (1)
// 0x00000004 [2] CLK_SYS_SYSCFG (1)
// 0x00000002 [1] CLK_SYS_SRAM5 (1)
// 0x00000001 [0] CLK_SYS_SRAM4 (1)
io_rw_32 sleep_en1;
};
// (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes)
_REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
// enable clock in sleep mode
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
// 0x08000000 [27] CLK_SYS_SPI1 (1)
// 0x04000000 [26] CLK_PERI_SPI1 (1)
// 0x02000000 [25] CLK_SYS_SPI0 (1)
// 0x01000000 [24] CLK_PERI_SPI0 (1)
// 0x00800000 [23] CLK_SYS_SIO (1)
// 0x00400000 [22] CLK_SYS_RTC (1)
// 0x00200000 [21] CLK_RTC_RTC (1)
// 0x00100000 [20] CLK_SYS_ROSC (1)
// 0x00080000 [19] CLK_SYS_ROM (1)
// 0x00040000 [18] CLK_SYS_RESETS (1)
// 0x00020000 [17] CLK_SYS_PWM (1)
// 0x00010000 [16] CLK_SYS_PSM (1)
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
// 0x00002000 [13] CLK_SYS_PIO1 (1)
// 0x00001000 [12] CLK_SYS_PIO0 (1)
// 0x00000800 [11] CLK_SYS_PADS (1)
// 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1)
// 0x00000200 [9] CLK_SYS_JTAG (1)
// 0x00000100 [8] CLK_SYS_IO (1)
// 0x00000080 [7] CLK_SYS_I2C1 (1)
// 0x00000040 [6] CLK_SYS_I2C0 (1)
// 0x00000020 [5] CLK_SYS_DMA (1)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
// 0x00000004 [2] CLK_SYS_ADC (1)
// 0x00000002 [1] CLK_ADC_ADC (1)
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
io_rw_32 sleep_en[2];
};
union {
struct {
_REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
// indicates the state of the clock enable
// 0x80000000 [31] CLK_SYS_SRAM3 (0)
// 0x40000000 [30] CLK_SYS_SRAM2 (0)
// 0x20000000 [29] CLK_SYS_SRAM1 (0)
// 0x10000000 [28] CLK_SYS_SRAM0 (0)
// 0x08000000 [27] CLK_SYS_SPI1 (0)
// 0x04000000 [26] CLK_PERI_SPI1 (0)
// 0x02000000 [25] CLK_SYS_SPI0 (0)
// 0x01000000 [24] CLK_PERI_SPI0 (0)
// 0x00800000 [23] CLK_SYS_SIOB (0)
// 0x00400000 [22] CLK_SYS_RTC (0)
// 0x00200000 [21] CLK_RTC_RTC (0)
// 0x00100000 [20] CLK_SYS_ROSC (0)
// 0x00080000 [19] CLK_SYS_ROM (0)
// 0x00040000 [18] CLK_SYS_RESETS (0)
// 0x00020000 [17] CLK_SYS_PWM (0)
// 0x00010000 [16] CLK_SYS_POWER (0)
// 0x00008000 [15] CLK_SYS_PLL_USB (0)
// 0x00004000 [14] CLK_SYS_PLL_SYS (0)
// 0x00002000 [13] CLK_SYS_PIO1 (0)
// 0x00001000 [12] CLK_SYS_PIO0 (0)
// 0x00000800 [11] CLK_SYS_PADS (0)
// 0x00000400 [10] CLK_SYS_LDO_POR (0)
// 0x00000200 [9] CLK_SYS_JTAG (0)
// 0x00000100 [8] CLK_SYS_IO (0)
// 0x00000080 [7] CLK_SYS_I2C1 (0)
// 0x00000040 [6] CLK_SYS_I2C0 (0)
// 0x00000020 [5] CLK_SYS_DMA (0)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (0)
// 0x00000008 [3] CLK_SYS_BUSCTRL (0)
// 0x00000004 [2] CLK_SYS_ADC0 (0)
// 0x00000002 [1] CLK_ADC_ADC0 (0)
// 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (0)
io_ro_32 enabled0;
_REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
// indicates the state of the clock enable
// 0x00004000 [14] CLK_SYS_XOSC (0)
// 0x00002000 [13] CLK_SYS_XIP (0)
// 0x00001000 [12] CLK_SYS_WATCHDOG (0)
// 0x00000800 [11] CLK_USB_USBCTRL (0)
// 0x00000400 [10] CLK_SYS_USBCTRL (0)
// 0x00000200 [9] CLK_SYS_UART1 (0)
// 0x00000100 [8] CLK_PERI_UART1 (0)
// 0x00000080 [7] CLK_SYS_UART0 (0)
// 0x00000040 [6] CLK_PERI_UART0 (0)
// 0x00000020 [5] CLK_SYS_TIMER (0)
// 0x00000010 [4] CLK_SYS_TBMAN (0)
// 0x00000008 [3] CLK_SYS_SYSINFO (0)
// 0x00000004 [2] CLK_SYS_SYSCFG (0)
// 0x00000002 [1] CLK_SYS_SRAM5 (0)
// 0x00000001 [0] CLK_SYS_SRAM4 (0)
io_ro_32 enabled1;
};
// (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes)
_REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
// indicates the state of the clock enable
// 0x80000000 [31] CLK_SYS_SRAM3 (0)
// 0x40000000 [30] CLK_SYS_SRAM2 (0)
// 0x20000000 [29] CLK_SYS_SRAM1 (0)
// 0x10000000 [28] CLK_SYS_SRAM0 (0)
// 0x08000000 [27] CLK_SYS_SPI1 (0)
// 0x04000000 [26] CLK_PERI_SPI1 (0)
// 0x02000000 [25] CLK_SYS_SPI0 (0)
// 0x01000000 [24] CLK_PERI_SPI0 (0)
// 0x00800000 [23] CLK_SYS_SIO (0)
// 0x00400000 [22] CLK_SYS_RTC (0)
// 0x00200000 [21] CLK_RTC_RTC (0)
// 0x00100000 [20] CLK_SYS_ROSC (0)
// 0x00080000 [19] CLK_SYS_ROM (0)
// 0x00040000 [18] CLK_SYS_RESETS (0)
// 0x00020000 [17] CLK_SYS_PWM (0)
// 0x00010000 [16] CLK_SYS_PSM (0)
// 0x00008000 [15] CLK_SYS_PLL_USB (0)
// 0x00004000 [14] CLK_SYS_PLL_SYS (0)
// 0x00002000 [13] CLK_SYS_PIO1 (0)
// 0x00001000 [12] CLK_SYS_PIO0 (0)
// 0x00000800 [11] CLK_SYS_PADS (0)
// 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (0)
// 0x00000200 [9] CLK_SYS_JTAG (0)
// 0x00000100 [8] CLK_SYS_IO (0)
// 0x00000080 [7] CLK_SYS_I2C1 (0)
// 0x00000040 [6] CLK_SYS_I2C0 (0)
// 0x00000020 [5] CLK_SYS_DMA (0)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (0)
// 0x00000008 [3] CLK_SYS_BUSCTRL (0)
// 0x00000004 [2] CLK_SYS_ADC (0)
// 0x00000002 [1] CLK_ADC_ADC (0)
// 0x00000001 [0] CLK_SYS_CLOCKS (0)
io_ro_32 enabled[2];
};
_REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
// Raw Interrupts
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_ro_32 intr;
_REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
// Interrupt Enable
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_rw_32 inte;
_REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
// Interrupt Force
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_rw_32 intf;
_REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
// Interrupt status after masking & forcing
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_ro_32 ints;
} clocks_hw_t;
#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE)
static_assert(sizeof (clocks_hw_t) == 0x00c8, "");
#endif // _HARDWARE_STRUCTS_CLOCKS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_DMA_H
#define _HARDWARE_STRUCTS_DMA_H
/**
* \file rp2040/dma.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/dma.h"
#include "hardware/structs/dma_debug.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
// DMA Channel 0 Read Address pointer
// 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes
io_rw_32 read_addr;
_REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
// DMA Channel 0 Write Address pointer
// 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes
io_rw_32 write_addr;
_REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
// DMA Channel 0 Transfer Count
// 0xffffffff [31:0] CH0_TRANS_COUNT (0x00000000) Program the number of bus transfers a channel will...
io_rw_32 transfer_count;
_REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
// DMA Channel 0 Control and Status
// 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags
// 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error
// 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error
// 0x01000000 [24] BUSY (0) This flag goes high when the channel starts a new...
// 0x00800000 [23] SNIFF_EN (0) If 1, this channel's data transfers are visible to the...
// 0x00400000 [22] BSWAP (0) Apply byte-swap transformation to DMA data
// 0x00200000 [21] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the...
// 0x001f8000 [20:15] TREQ_SEL (0x00) Select a Transfer Request signal
// 0x00007800 [14:11] CHAIN_TO (0x0) When this channel completes, it will trigger the channel...
// 0x00000400 [10] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses
// 0x000003c0 [9:6] RING_SIZE (0x0) Size of address wrap region
// 0x00000020 [5] INCR_WRITE (0) If 1, the write address increments with each transfer
// 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer
// 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word)
// 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in...
// 0x00000001 [0] EN (0) DMA Channel Enable
io_rw_32 ctrl_trig;
_REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
// Alias for channel 0 CTRL register
// 0xffffffff [31:0] CH0_AL1_CTRL (-)
io_rw_32 al1_ctrl;
_REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
// Alias for channel 0 READ_ADDR register
// 0xffffffff [31:0] CH0_AL1_READ_ADDR (-)
io_rw_32 al1_read_addr;
_REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
// Alias for channel 0 WRITE_ADDR register
// 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-)
io_rw_32 al1_write_addr;
_REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
// Alias for channel 0 TRANS_COUNT register +
// 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-)
io_rw_32 al1_transfer_count_trig;
_REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
// Alias for channel 0 CTRL register
// 0xffffffff [31:0] CH0_AL2_CTRL (-)
io_rw_32 al2_ctrl;
_REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
// Alias for channel 0 TRANS_COUNT register
// 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-)
io_rw_32 al2_transfer_count;
_REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
// Alias for channel 0 READ_ADDR register
// 0xffffffff [31:0] CH0_AL2_READ_ADDR (-)
io_rw_32 al2_read_addr;
_REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
// Alias for channel 0 WRITE_ADDR register +
// 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-)
io_rw_32 al2_write_addr_trig;
_REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
// Alias for channel 0 CTRL register
// 0xffffffff [31:0] CH0_AL3_CTRL (-)
io_rw_32 al3_ctrl;
_REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
// Alias for channel 0 WRITE_ADDR register
// 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-)
io_rw_32 al3_write_addr;
_REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
// Alias for channel 0 TRANS_COUNT register
// 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-)
io_rw_32 al3_transfer_count;
_REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
// Alias for channel 0 READ_ADDR register +
// 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-)
io_rw_32 al3_read_addr_trig;
} dma_channel_hw_t;
typedef struct {
_REG_(DMA_INTR_OFFSET) // DMA_INTR
// Interrupt Status (raw)
// 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
io_rw_32 intr;
_REG_(DMA_INTE0_OFFSET) // DMA_INTE0
// Interrupt Enables for IRQ 0
// 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
io_rw_32 inte;
_REG_(DMA_INTF0_OFFSET) // DMA_INTF0
// Force Interrupts
// 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0
io_rw_32 intf;
_REG_(DMA_INTS0_OFFSET) // DMA_INTS0
// Interrupt Status for IRQ 0
// 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
io_rw_32 ints;
} dma_irq_ctrl_hw_t;
typedef struct {
dma_channel_hw_t ch[12];
uint32_t _pad0[64];
union {
struct {
_REG_(DMA_INTR_OFFSET) // DMA_INTR
// Interrupt Status (raw)
// 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
io_rw_32 intr;
_REG_(DMA_INTE0_OFFSET) // DMA_INTE0
// Interrupt Enables for IRQ 0
// 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
io_rw_32 inte0;
_REG_(DMA_INTF0_OFFSET) // DMA_INTF0
// Force Interrupts
// 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0
io_rw_32 intf0;
_REG_(DMA_INTS0_OFFSET) // DMA_INTS0
// Interrupt Status for IRQ 0
// 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
io_rw_32 ints0;
uint32_t __pad0;
_REG_(DMA_INTE1_OFFSET) // DMA_INTE1
// Interrupt Enables for IRQ 1
// 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1
io_rw_32 inte1;
_REG_(DMA_INTF1_OFFSET) // DMA_INTF1
// Force Interrupts for IRQ 1
// 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1
io_rw_32 intf1;
_REG_(DMA_INTS1_OFFSET) // DMA_INTS1
// Interrupt Status (masked) for IRQ 1
// 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are...
io_rw_32 ints1;
};
dma_irq_ctrl_hw_t irq_ctrl[2];
};
// (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
_REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
// Pacing (X/Y) Fractional Timer +
// 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend
// 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor
io_rw_32 timer[4];
_REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
// Trigger one or more channels simultaneously
// 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel
io_wo_32 multi_channel_trigger;
_REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
// Sniffer Control
// 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)...
// 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read
// 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,...
// 0x000001e0 [8:5] CALC (0x0)
// 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe
// 0x00000001 [0] EN (0) Enable sniffer
io_rw_32 sniff_ctrl;
_REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
// Data accumulator for sniff hardware
// 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA...
io_rw_32 sniff_data;
uint32_t _pad1;
_REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
// Debug RAF, WAF, TDF levels
// 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level
// 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level
// 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level
io_ro_32 fifo_levels;
_REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
// Abort an in-progress transfer sequence on one or more channels
// 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel
io_wo_32 abort;
} dma_hw_t;
#define dma_hw ((dma_hw_t *)DMA_BASE)
static_assert(sizeof (dma_hw_t) == 0x0448, "");
#endif // _HARDWARE_STRUCTS_DMA_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H
#define _HARDWARE_STRUCTS_DMA_DEBUG_H
/**
* \file rp2040/dma_debug.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/dma.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ
// Read: get channel DREQ counter (i
// 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00)
io_rw_32 dbg_ctdreq;
_REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR
// Read to get channel TRANS_COUNT reload value, i
// 0xffffffff [31:0] CH0_DBG_TCR (0x00000000)
io_ro_32 dbg_tcr;
uint32_t _pad0[14];
} dma_debug_channel_hw_t;
typedef struct {
dma_debug_channel_hw_t ch[12];
} dma_debug_hw_t;
#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_I2C_H
#define _HARDWARE_STRUCTS_I2C_H
/**
* \file rp2040/i2c.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/i2c.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON
// I2C Control Register
// 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of...
// 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus...
// 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY...
// 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt...
// 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,...
// 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when...
// 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in...
// 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the...
// 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c...
// 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled
io_rw_32 con;
_REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR
// I2C Target Address Register
// 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID...
// 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is...
// 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction
io_rw_32 tar;
_REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR
// I2C Slave Address Register
// 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is...
io_rw_32 sar;
uint32_t _pad0;
_REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD
// I2C Rx/Tx Data Buffer and Command Register
// 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address...
// 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the...
// 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the...
// 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed
// 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or...
io_rw_32 data_cmd;
_REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT
// Standard Speed I2C Clock SCL High Count Register
// 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction...
io_rw_32 ss_scl_hcnt;
_REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT
// Standard Speed I2C Clock SCL Low Count Register
// 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction...
io_rw_32 ss_scl_lcnt;
_REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT
// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
// 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction...
io_rw_32 fs_scl_hcnt;
_REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT
// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
// 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction...
io_rw_32 fs_scl_lcnt;
uint32_t _pad1[2];
_REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT
// I2C Interrupt Status Register
// 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of...
// 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit
// 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of...
// 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit
// 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit
// 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit
// 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit
// 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit
// 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit
// 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit
// 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit
// 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit
// 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit
io_ro_32 intr_stat;
_REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK
// I2C Interrupt Mask Register
// 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in...
// 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register
// 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register
// 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register
// 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register
// 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register
// 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register
// 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register
// 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register
// 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register
// 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register
// 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register
// 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register
io_rw_32 intr_mask;
_REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT
// I2C Raw Interrupt Status Register
// 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on...
// 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it...
// 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has...
// 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the...
// 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set...
// 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,...
// 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,...
// 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a...
// 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs...
// 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to...
// 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the...
// 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to...
// 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer...
io_ro_32 raw_intr_stat;
_REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL
// I2C Receive FIFO Threshold Register
// 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level
io_rw_32 rx_tl;
_REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL
// I2C Transmit FIFO Threshold Register
// 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level
io_rw_32 tx_tl;
_REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR
// Clear Combined and Individual Interrupt Register
// 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all...
io_ro_32 clr_intr;
_REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER
// Clear RX_UNDER Interrupt Register
// 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit...
io_ro_32 clr_rx_under;
_REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER
// Clear RX_OVER Interrupt Register
// 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit...
io_ro_32 clr_rx_over;
_REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER
// Clear TX_OVER Interrupt Register
// 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit...
io_ro_32 clr_tx_over;
_REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ
// Clear RD_REQ Interrupt Register
// 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)...
io_ro_32 clr_rd_req;
_REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT
// Clear TX_ABRT Interrupt Register
// 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit...
io_ro_32 clr_tx_abrt;
_REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE
// Clear RX_DONE Interrupt Register
// 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit...
io_ro_32 clr_rx_done;
_REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY
// Clear ACTIVITY Interrupt Register
// 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if...
io_ro_32 clr_activity;
_REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET
// Clear STOP_DET Interrupt Register
// 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit...
io_ro_32 clr_stop_det;
_REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET
// Clear START_DET Interrupt Register
// 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit...
io_ro_32 clr_start_det;
_REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL
// Clear GEN_CALL Interrupt Register
// 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit...
io_ro_32 clr_gen_call;
_REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE
// I2C ENABLE Register
// 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data...
// 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort
// 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled
io_rw_32 enable;
_REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS
// I2C STATUS Register
// 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status
// 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status
// 0x00000010 [4] RFF (0) Receive FIFO Completely Full
// 0x00000008 [3] RFNE (0) Receive FIFO Not Empty
// 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty
// 0x00000002 [1] TFNF (1) Transmit FIFO Not Full
// 0x00000001 [0] ACTIVITY (0) I2C Activity Status
io_ro_32 status;
_REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR
// I2C Transmit FIFO Level Register
// 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level
io_ro_32 txflr;
_REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR
// I2C Receive FIFO Level Register
// 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level
io_ro_32 rxflr;
_REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD
// I2C SDA Hold Time Length Register
// 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk...
// 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk...
io_rw_32 sda_hold;
_REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE
// I2C Transmit Abort Source Register
// 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands...
// 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit
// 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode...
// 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while...
// 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read...
// 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost...
// 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a...
// 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled...
// 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT...
// 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled...
// 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START...
// 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed...
// 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode...
// 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has...
// 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit
// 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit...
// 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit...
// 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit...
io_ro_32 tx_abrt_source;
_REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY
// Generate Slave Data NACK Register
// 0x00000001 [0] NACK (0) Generate NACK
io_rw_32 slv_data_nack_only;
_REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR
// DMA Control Register
// 0x00000002 [1] TDMAE (0) Transmit DMA Enable
// 0x00000001 [0] RDMAE (0) Receive DMA Enable
io_rw_32 dma_cr;
_REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR
// DMA Transmit Data Level Register
// 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level
io_rw_32 dma_tdlr;
_REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR
// DMA Transmit Data Level Register
// 0x0000000f [3:0] DMARDL (0x0) Receive Data Level
io_rw_32 dma_rdlr;
_REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP
// I2C SDA Setup Register
// 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup
io_rw_32 sda_setup;
_REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL
// I2C ACK General Call Register
// 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call
io_rw_32 ack_general_call;
_REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS
// I2C Enable Status Register
// 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost
// 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive)
// 0x00000001 [0] IC_EN (0) ic_en Status
io_ro_32 enable_status;
_REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN
// I2C SS, FS or FM+ spike suppression limit
// 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction...
io_rw_32 fs_spklen;
uint32_t _pad2;
_REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET
// Clear RESTART_DET Interrupt Register
// 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt...
io_ro_32 clr_restart_det;
uint32_t _pad3[18];
_REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1
// Component Parameter Register 1
// 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16
// 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16
// 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible
// 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled
// 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs
// 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode
// 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE
// 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits
io_ro_32 comp_param_1;
_REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION
// I2C Component Version Register
// 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a)
io_ro_32 comp_version;
_REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE
// I2C Component Type Register
// 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40
io_ro_32 comp_type;
} i2c_hw_t;
#define i2c0_hw ((i2c_hw_t *)I2C0_BASE)
#define i2c1_hw ((i2c_hw_t *)I2C1_BASE)
static_assert(sizeof (i2c_hw_t) == 0x0100, "");
#endif // _HARDWARE_STRUCTS_I2C_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_INTERP_H
#define _HARDWARE_STRUCTS_INTERP_H
/**
* \file rp2040/interp.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sio.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
// Read/write access to accumulator 0
// 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000)
io_rw_32 accum[2];
// (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
// Read/write access to BASE0 register
// 0xffffffff [31:0] INTERP0_BASE0 (0x00000000)
io_rw_32 base[3];
// (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
// Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
// 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000)
io_ro_32 pop[3];
// (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
// Read LANE0 result, without altering any internal state (PEEK)
// 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000)
io_ro_32 peek[3];
// (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
// Control register for lane 0
// 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set
// 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set
// 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set
// 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core
// 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the...
// 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result
// 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's...
// 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this...
// 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator...
// 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask...
// 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive)
// 0x0000001f [4:0] SHIFT (0x00) Logical right-shift applied to accumulator before masking
io_rw_32 ctrl[2];
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
_REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
// Values written here are atomically added to ACCUM0
// 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000)
io_rw_32 add_raw[2];
_REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
// 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000)
io_wo_32 base01;
} interp_hw_t;
#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET))
static_assert(sizeof (interp_hw_t) == 0x0040, "");
#define interp0_hw (&interp_hw_array[0])
#define interp1_hw (&interp_hw_array[1])
#endif // _HARDWARE_STRUCTS_INTERP_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_IO_BANK0_H
#define _HARDWARE_STRUCTS_IO_BANK0_H
/**
* \file rp2040/io_bank0.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/io_bank0.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/**
* \brief GPIO pin function selectors on RP2040 (used as typedef \ref gpio_function_t)
* \ingroup hardware_gpio
*/
typedef enum gpio_function_rp2040 {
GPIO_FUNC_XIP = 0, ///< Select XIP as GPIO pin function
GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function
GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function
GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function
GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function
GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function
GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function
GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function
GPIO_FUNC_GPCK = 8, ///< Select GPCK as GPIO pin function
GPIO_FUNC_USB = 9, ///< Select USB as GPIO pin function
GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function
} gpio_function_t;
typedef struct {
_REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
// GPIO status
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
// 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied
// 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
// 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register...
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
// 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register...
io_ro_32 status;
_REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
// GPIO control including function select and overrides
// 0x30000000 [29:28] IRQOVER (0x0)
// 0x00030000 [17:16] INOVER (0x0)
// 0x00003000 [13:12] OEOVER (0x0)
// 0x00000300 [9:8] OUTOVER (0x0)
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
io_rw_32 ctrl;
} io_bank0_status_ctrl_hw_t;
typedef struct {
// (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
_REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
// Interrupt Enable for proc0
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_rw_32 inte[4];
// (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
_REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
// Interrupt Force for proc0
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_rw_32 intf[4];
// (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
_REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
// Interrupt status after masking & forcing for proc0
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_ro_32 ints[4];
} io_bank0_irq_ctrl_hw_t;
/// \tag::io_bank0_hw[]
typedef struct {
io_bank0_status_ctrl_hw_t io[30];
// (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
_REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
// Raw Interrupts
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_rw_32 intr[4];
union {
struct {
io_bank0_irq_ctrl_hw_t proc0_irq_ctrl;
io_bank0_irq_ctrl_hw_t proc1_irq_ctrl;
io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl;
};
io_bank0_irq_ctrl_hw_t irq_ctrl[3];
};
} io_bank0_hw_t;
/// \end::io_bank0_hw[]
#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE)
static_assert(sizeof (io_bank0_hw_t) == 0x0190, "");
#endif // _HARDWARE_STRUCTS_IO_BANK0_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_IO_QSPI_H
#define _HARDWARE_STRUCTS_IO_QSPI_H
/**
* \file rp2040/io_qspi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/io_qspi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/**
* \brief QSPI pin function selectors on RP2040 (used as typedef \ref gpio_function1_t)
*/
typedef enum gpio_function1_rp2040 {
GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function
GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function
GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function
} gpio_function1_t;
typedef struct {
_REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
// GPIO status
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
// 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied
// 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
// 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register...
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
// 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register...
io_ro_32 status;
_REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
// GPIO control including function select and overrides
// 0x30000000 [29:28] IRQOVER (0x0)
// 0x00030000 [17:16] INOVER (0x0)
// 0x00003000 [13:12] OEOVER (0x0)
// 0x00000300 [9:8] OUTOVER (0x0)
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
io_rw_32 ctrl;
} io_qspi_status_ctrl_hw_t;
typedef struct {
_REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
// Interrupt Enable for proc0
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
io_rw_32 inte;
_REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
// Interrupt Force for proc0
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
io_rw_32 intf;
_REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
// Interrupt status after masking & forcing for proc0
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
io_ro_32 ints;
} io_qspi_irq_ctrl_hw_t;
typedef struct {
io_qspi_status_ctrl_hw_t io[6];
_REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
// Raw Interrupts
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
io_rw_32 intr;
union {
struct {
io_qspi_irq_ctrl_hw_t proc0_irq_ctrl;
io_qspi_irq_ctrl_hw_t proc1_irq_ctrl;
io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl;
};
io_qspi_irq_ctrl_hw_t irq_ctrl[3];
};
} io_qspi_hw_t;
#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE)
static_assert(sizeof (io_qspi_hw_t) == 0x0058, "");
#endif // _HARDWARE_STRUCTS_IO_QSPI_H

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/io_bank0.h"
#define iobank0_hw io_bank0_hw

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/io_qspi.h"
#define ioqspi_hw io_qspi_hw

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_M0PLUS_H
#define _HARDWARE_STRUCTS_M0PLUS_H
/**
* \file rp2040/m0plus.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
uint32_t _pad0[14340];
_REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
// SysTick Control and Status Register
// 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read
// 0x00000004 [2] CLKSOURCE (0) SysTick clock source
// 0x00000002 [1] TICKINT (0) Enables SysTick exception request: +
// 0x00000001 [0] ENABLE (0) Enable SysTick counter: +
io_rw_32 syst_csr;
_REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
// SysTick Reload Value Register
// 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register...
io_rw_32 syst_rvr;
_REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
// SysTick Current Value Register
// 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter
io_rw_32 syst_cvr;
_REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
// SysTick Calibration Value Register
// 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the...
// 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact...
// 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)...
io_ro_32 syst_calib;
uint32_t _pad1[56];
_REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
// Interrupt Set-Enable Register
// 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits
io_rw_32 nvic_iser;
uint32_t _pad2[31];
_REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
// Interrupt Clear-Enable Register
// 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits
io_rw_32 nvic_icer;
uint32_t _pad3[31];
_REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
// Interrupt Set-Pending Register
// 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits
io_rw_32 nvic_ispr;
uint32_t _pad4[31];
_REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
// Interrupt Clear-Pending Register
// 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits
io_rw_32 nvic_icpr;
uint32_t _pad5[95];
// (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
_REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
// Interrupt Priority Register 0
// 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3
// 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2
// 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1
// 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0
io_rw_32 nvic_ipr[8];
uint32_t _pad6[568];
_REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
// CPUID Base Register
// 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM
// 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: +
// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +
// 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+
// 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: +
io_ro_32 cpuid;
_REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
// Interrupt Control and State Register
// 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI
// 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit
// 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit
// 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit
// 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit
// 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted
// 0x00400000 [22] ISRPENDING (0) External interrupt pending flag
// 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority...
// 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field
io_rw_32 icsr;
_REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
// Vector Table Offset Register
// 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address
io_rw_32 vtor;
_REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
// Application Interrupt and Reset Control Register
// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
io_rw_32 aircr;
_REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
// System Control Register
// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
io_rw_32 scr;
_REG_(M0PLUS_CCR_OFFSET) // M0PLUS_CCR
// Configuration and Control Register
// 0x00000200 [9] STKALIGN (0) Always reads as one, indicates 8-byte stack alignment on...
// 0x00000008 [3] UNALIGN_TRP (0) Always reads as one, indicates that all unaligned...
io_ro_32 ccr;
uint32_t _pad7;
// (Description copied from array index 0 register M0PLUS_SHPR2 applies similarly to other array indexes)
_REG_(M0PLUS_SHPR2_OFFSET) // M0PLUS_SHPR2
// System Handler Priority Register 2
// 0xc0000000 [31:30] PRI_11 (0x0) Priority of system handler 11, SVCall
io_rw_32 shpr[2];
_REG_(M0PLUS_SHCSR_OFFSET) // M0PLUS_SHCSR
// System Handler Control and State Register
// 0x00008000 [15] SVCALLPENDED (0) Reads as 1 if SVCall is Pending
io_rw_32 shcsr;
uint32_t _pad8[26];
_REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
// MPU Type Register
// 0x00ff0000 [23:16] IREGION (0x00) Instruction region
// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
// 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps
io_ro_32 mpu_type;
_REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
// MPU Control Register
// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a...
// 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs
// 0x00000001 [0] ENABLE (0) Enables the MPU
io_rw_32 mpu_ctrl;
_REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
// MPU Region Number Register
// 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and...
io_rw_32 mpu_rnr;
_REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
// MPU Region Base Address Register
// 0xffffff00 [31:8] ADDR (0x000000) Base address of the region
// 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the...
// 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base...
io_rw_32 mpu_rbar;
_REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
// MPU Region Attribute and Size Register
// 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field
// 0x0000ff00 [15:8] SRD (0x00) Subregion Disable
// 0x0000003e [5:1] SIZE (0x00) Indicates the region size
// 0x00000001 [0] ENABLE (0) Enables the region
io_rw_32 mpu_rasr;
} m0plus_hw_t;
#define ppb_hw ((m0plus_hw_t *)PPB_BASE)
static_assert(sizeof (m0plus_hw_t) == 0xeda4, "");
#endif // _HARDWARE_STRUCTS_M0PLUS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_MPU_H
#define _HARDWARE_STRUCTS_MPU_H
/**
* \file rp2040/mpu.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
// MPU Type Register
// 0x00ff0000 [23:16] IREGION (0x00) Instruction region
// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
// 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps
io_ro_32 type;
_REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
// MPU Control Register
// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a...
// 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs
// 0x00000001 [0] ENABLE (0) Enables the MPU
io_rw_32 ctrl;
_REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
// MPU Region Number Register
// 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and...
io_rw_32 rnr;
_REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
// MPU Region Base Address Register
// 0xffffff00 [31:8] ADDR (0x000000) Base address of the region
// 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the...
// 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base...
io_rw_32 rbar;
_REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
// MPU Region Attribute and Size Register
// 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field
// 0x0000ff00 [15:8] SRD (0x00) Subregion Disable
// 0x0000003e [5:1] SIZE (0x00) Indicates the region size
// 0x00000001 [0] ENABLE (0) Enables the region
io_rw_32 rasr;
} mpu_hw_t;
#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
static_assert(sizeof (mpu_hw_t) == 0x0014, "");
#endif // _HARDWARE_STRUCTS_MPU_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_NVIC_H
#define _HARDWARE_STRUCTS_NVIC_H
/**
* \file rp2040/nvic.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
// Interrupt Set-Enable Register
// 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits
io_rw_32 iser;
uint32_t _pad0[31];
_REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
// Interrupt Clear-Enable Register
// 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits
io_rw_32 icer;
uint32_t _pad1[31];
_REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
// Interrupt Set-Pending Register
// 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits
io_rw_32 ispr;
uint32_t _pad2[31];
_REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
// Interrupt Clear-Pending Register
// 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits
io_rw_32 icpr;
uint32_t _pad3[95];
// (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
_REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
// Interrupt Priority Register 0
// 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3
// 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2
// 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1
// 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0
io_rw_32 ipr[8];
} nvic_hw_t;
#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))
static_assert(sizeof (nvic_hw_t) == 0x0320, "");
#endif // _HARDWARE_STRUCTS_NVIC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H
#define _HARDWARE_STRUCTS_PADS_BANK0_H
/**
* \file rp2040/pads_bank0.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pads_bank0.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT
// Voltage select
// 0x00000001 [0] VOLTAGE_SELECT (0)
io_rw_32 voltage_select;
// (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
_REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
// Pad control register
// 0x00000080 [7] OD (0) Output disable
// 0x00000040 [6] IE (1) Input enable
// 0x00000030 [5:4] DRIVE (0x1) Drive strength
// 0x00000008 [3] PUE (0) Pull up enable
// 0x00000004 [2] PDE (1) Pull down enable
// 0x00000002 [1] SCHMITT (1) Enable schmitt trigger
// 0x00000001 [0] SLEWFAST (0) Slew rate control
io_rw_32 io[30];
} pads_bank0_hw_t;
#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE)
static_assert(sizeof (pads_bank0_hw_t) == 0x007c, "");
#endif // _HARDWARE_STRUCTS_PADS_BANK0_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H
#define _HARDWARE_STRUCTS_PADS_QSPI_H
/**
* \file rp2040/pads_qspi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pads_qspi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT
// Voltage select
// 0x00000001 [0] VOLTAGE_SELECT (0)
io_rw_32 voltage_select;
// (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
_REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
// Pad control register
// 0x00000080 [7] OD (0) Output disable
// 0x00000040 [6] IE (1) Input enable
// 0x00000030 [5:4] DRIVE (0x1) Drive strength
// 0x00000008 [3] PUE (0) Pull up enable
// 0x00000004 [2] PDE (1) Pull down enable
// 0x00000002 [1] SCHMITT (1) Enable schmitt trigger
// 0x00000001 [0] SLEWFAST (0) Slew rate control
io_rw_32 io[6];
} pads_qspi_hw_t;
#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE)
static_assert(sizeof (pads_qspi_hw_t) == 0x001c, "");
#endif // _HARDWARE_STRUCTS_PADS_QSPI_H

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/pads_bank0.h"
#define padsbank0_hw pads_bank0_hw

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PIO_H
#define _HARDWARE_STRUCTS_PIO_H
/**
* \file rp2040/pio.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pio.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV
// Clock divisor register for state machine 0 +
// 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256)
// 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor
io_rw_32 clkdiv;
_REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL
// Execution/behavioural settings for state machine 0
// 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,...
// 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is...
// 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,...
// 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN
// 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable
// 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable +
// 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins
// 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom
// 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address
// 0x00000010 [4] STATUS_SEL (0) Comparison used for the MOV x, STATUS instruction
// 0x0000000f [3:0] STATUS_N (0x0) Comparison level for the MOV x, STATUS instruction
io_rw_32 execctrl;
_REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL
// Control behaviour of the input/output shift registers for state machine 0
// 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and...
// 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and...
// 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or...
// 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or...
// 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right
// 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left)
// 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i
// 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i
io_rw_32 shiftctrl;
_REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR
// Current instruction address of state machine 0
// 0x0000001f [4:0] SM0_ADDR (0x00)
io_ro_32 addr;
_REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR
// Read to see the instruction currently addressed by state machine 0's program counter +
// 0x0000ffff [15:0] SM0_INSTR (-)
io_rw_32 instr;
_REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL
// State machine pin control
// 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction...
// 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET
// 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS...
// 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of...
// 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a...
// 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET...
// 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT...
io_rw_32 pinctrl;
} pio_sm_hw_t;
typedef struct {
_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
// Interrupt Enable for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 inte;
_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
// Interrupt Force for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 intf;
_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
// Interrupt status after masking & forcing for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 ints;
} pio_irq_ctrl_hw_t;
typedef struct {
_REG_(PIO_CTRL_OFFSET) // PIO_CTRL
// PIO control register
// 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial...
// 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may...
// 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by...
io_rw_32 ctrl;
_REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT
// FIFO status register
// 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty
// 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full
// 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty
// 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full
io_ro_32 fstat;
_REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG
// FIFO debug register
// 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a...
// 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i
// 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i
// 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a...
io_rw_32 fdebug;
_REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL
// FIFO levels
// 0xf0000000 [31:28] RX3 (0x0)
// 0x0f000000 [27:24] TX3 (0x0)
// 0x00f00000 [23:20] RX2 (0x0)
// 0x000f0000 [19:16] TX2 (0x0)
// 0x0000f000 [15:12] RX1 (0x0)
// 0x00000f00 [11:8] TX1 (0x0)
// 0x000000f0 [7:4] RX0 (0x0)
// 0x0000000f [3:0] TX0 (0x0)
io_ro_32 flevel;
// (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)
_REG_(PIO_TXF0_OFFSET) // PIO_TXF0
// Direct write access to the TX FIFO for this state machine
// 0xffffffff [31:0] TXF0 (0x00000000)
io_wo_32 txf[4];
// (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)
_REG_(PIO_RXF0_OFFSET) // PIO_RXF0
// Direct read access to the RX FIFO for this state machine
// 0xffffffff [31:0] RXF0 (-)
io_ro_32 rxf[4];
_REG_(PIO_IRQ_OFFSET) // PIO_IRQ
// State machine IRQ flags register
// 0x000000ff [7:0] IRQ (0x00)
io_rw_32 irq;
_REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE
// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ
// 0x000000ff [7:0] IRQ_FORCE (0x00)
io_wo_32 irq_force;
_REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS
// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities
// 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000)
io_rw_32 input_sync_bypass;
_REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT
// Read to sample the pad output values PIO is currently driving to the GPIOs
// 0xffffffff [31:0] DBG_PADOUT (0x00000000)
io_ro_32 dbg_padout;
_REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE
// Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs
// 0xffffffff [31:0] DBG_PADOE (0x00000000)
io_ro_32 dbg_padoe;
_REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO
// The PIO hardware has some free parameters that may vary between chip products
// 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of...
// 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with
// 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words
io_ro_32 dbg_cfginfo;
// (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)
_REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0
// Write-only access to instruction memory location 0
// 0x0000ffff [15:0] INSTR_MEM0 (0x0000)
io_wo_32 instr_mem[32];
pio_sm_hw_t sm[4];
_REG_(PIO_INTR_OFFSET) // PIO_INTR
// Raw Interrupts
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 intr;
union {
struct {
_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
// Interrupt Enable for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 inte0;
_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
// Interrupt Force for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 intf0;
_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
// Interrupt status after masking & forcing for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 ints0;
_REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE
// Interrupt Enable for irq1
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 inte1;
_REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF
// Interrupt Force for irq1
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 intf1;
_REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS
// Interrupt status after masking & forcing for irq1
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 ints1;
};
pio_irq_ctrl_hw_t irq_ctrl[2];
};
} pio_hw_t;
#define pio0_hw ((pio_hw_t *)PIO0_BASE)
#define pio1_hw ((pio_hw_t *)PIO1_BASE)
static_assert(sizeof (pio_hw_t) == 0x0144, "");
#endif // _HARDWARE_STRUCTS_PIO_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PLL_H
#define _HARDWARE_STRUCTS_PLL_H
/**
* \file rp2040/pll.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pll.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pll.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/// \tag::pll_hw[]
typedef struct {
_REG_(PLL_CS_OFFSET) // PLL_CS
// Control and Status
// 0x80000000 [31] LOCK (0) PLL is locked
// 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the...
// 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock
io_rw_32 cs;
_REG_(PLL_PWR_OFFSET) // PLL_PWR
// Controls the PLL power modes
// 0x00000020 [5] VCOPD (1) PLL VCO powerdown +
// 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown +
// 0x00000004 [2] DSMPD (1) PLL DSM powerdown +
// 0x00000001 [0] PD (1) PLL powerdown +
io_rw_32 pwr;
_REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
// Feedback divisor
// 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints
io_rw_32 fbdiv_int;
_REG_(PLL_PRIM_OFFSET) // PLL_PRIM
// Controls the PLL post dividers for the primary output
// 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7
// 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7
io_rw_32 prim;
} pll_hw_t;
/// \end::pll_hw[]
#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE)
#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE)
static_assert(sizeof (pll_hw_t) == 0x0010, "");
#endif // _HARDWARE_STRUCTS_PLL_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PSM_H
#define _HARDWARE_STRUCTS_PSM_H
/**
* \file rp2040/psm.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/psm.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/psm.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON
// Force block out of reset (i
// 0x00010000 [16] PROC1 (0)
// 0x00008000 [15] PROC0 (0)
// 0x00004000 [14] SIO (0)
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
// 0x00001000 [12] XIP (0)
// 0x00000800 [11] SRAM5 (0)
// 0x00000400 [10] SRAM4 (0)
// 0x00000200 [9] SRAM3 (0)
// 0x00000100 [8] SRAM2 (0)
// 0x00000080 [7] SRAM1 (0)
// 0x00000040 [6] SRAM0 (0)
// 0x00000020 [5] ROM (0)
// 0x00000010 [4] BUSFABRIC (0)
// 0x00000008 [3] RESETS (0)
// 0x00000004 [2] CLOCKS (0)
// 0x00000002 [1] XOSC (0)
// 0x00000001 [0] ROSC (0)
io_rw_32 frce_on;
_REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF
// Force into reset (i
// 0x00010000 [16] PROC1 (0)
// 0x00008000 [15] PROC0 (0)
// 0x00004000 [14] SIO (0)
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
// 0x00001000 [12] XIP (0)
// 0x00000800 [11] SRAM5 (0)
// 0x00000400 [10] SRAM4 (0)
// 0x00000200 [9] SRAM3 (0)
// 0x00000100 [8] SRAM2 (0)
// 0x00000080 [7] SRAM1 (0)
// 0x00000040 [6] SRAM0 (0)
// 0x00000020 [5] ROM (0)
// 0x00000010 [4] BUSFABRIC (0)
// 0x00000008 [3] RESETS (0)
// 0x00000004 [2] CLOCKS (0)
// 0x00000002 [1] XOSC (0)
// 0x00000001 [0] ROSC (0)
io_rw_32 frce_off;
_REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL
// Set to 1 if this peripheral should be reset when the watchdog fires
// 0x00010000 [16] PROC1 (0)
// 0x00008000 [15] PROC0 (0)
// 0x00004000 [14] SIO (0)
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
// 0x00001000 [12] XIP (0)
// 0x00000800 [11] SRAM5 (0)
// 0x00000400 [10] SRAM4 (0)
// 0x00000200 [9] SRAM3 (0)
// 0x00000100 [8] SRAM2 (0)
// 0x00000080 [7] SRAM1 (0)
// 0x00000040 [6] SRAM0 (0)
// 0x00000020 [5] ROM (0)
// 0x00000010 [4] BUSFABRIC (0)
// 0x00000008 [3] RESETS (0)
// 0x00000004 [2] CLOCKS (0)
// 0x00000002 [1] XOSC (0)
// 0x00000001 [0] ROSC (0)
io_rw_32 wdsel;
_REG_(PSM_DONE_OFFSET) // PSM_DONE
// Indicates the peripheral's registers are ready to access
// 0x00010000 [16] PROC1 (0)
// 0x00008000 [15] PROC0 (0)
// 0x00004000 [14] SIO (0)
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
// 0x00001000 [12] XIP (0)
// 0x00000800 [11] SRAM5 (0)
// 0x00000400 [10] SRAM4 (0)
// 0x00000200 [9] SRAM3 (0)
// 0x00000100 [8] SRAM2 (0)
// 0x00000080 [7] SRAM1 (0)
// 0x00000040 [6] SRAM0 (0)
// 0x00000020 [5] ROM (0)
// 0x00000010 [4] BUSFABRIC (0)
// 0x00000008 [3] RESETS (0)
// 0x00000004 [2] CLOCKS (0)
// 0x00000002 [1] XOSC (0)
// 0x00000001 [0] ROSC (0)
io_ro_32 done;
} psm_hw_t;
#define psm_hw ((psm_hw_t *)PSM_BASE)
static_assert(sizeof (psm_hw_t) == 0x0010, "");
#endif // _HARDWARE_STRUCTS_PSM_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PWM_H
#define _HARDWARE_STRUCTS_PWM_H
/**
* \file rp2040/pwm.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pwm.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
// Control and status register
// 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running
// 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running
// 0x00000030 [5:4] DIVMODE (0x0)
// 0x00000008 [3] B_INV (0) Invert output B
// 0x00000004 [2] A_INV (0) Invert output A
// 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation
// 0x00000001 [0] EN (0) Enable the PWM channel
io_rw_32 csr;
_REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
// INT and FRAC form a fixed-point fractional number
// 0x00000ff0 [11:4] INT (0x01)
// 0x0000000f [3:0] FRAC (0x0)
io_rw_32 div;
_REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
// Direct access to the PWM counter
// 0x0000ffff [15:0] CH0_CTR (0x0000)
io_rw_32 ctr;
_REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
// Counter compare values
// 0xffff0000 [31:16] B (0x0000)
// 0x0000ffff [15:0] A (0x0000)
io_rw_32 cc;
_REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
// Counter wrap value
// 0x0000ffff [15:0] CH0_TOP (0xffff)
io_rw_32 top;
} pwm_slice_hw_t;
typedef struct {
_REG_(PWM_INTE_OFFSET) // PWM_INTE
// Interrupt Enable
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 inte;
_REG_(PWM_INTF_OFFSET) // PWM_INTF
// Interrupt Force
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intf;
_REG_(PWM_INTS_OFFSET) // PWM_INTS
// Interrupt status after masking & forcing
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_ro_32 ints;
} pwm_irq_ctrl_hw_t;
typedef struct {
pwm_slice_hw_t slice[8];
_REG_(PWM_EN_OFFSET) // PWM_EN
// This register aliases the CSR_EN bits for all channels
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 en;
_REG_(PWM_INTR_OFFSET) // PWM_INTR
// Raw Interrupts
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intr;
union {
struct {
_REG_(PWM_INTE_OFFSET) // PWM_INTE
// Interrupt Enable
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 inte;
_REG_(PWM_INTF_OFFSET) // PWM_INTF
// Interrupt Force
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intf;
_REG_(PWM_INTS_OFFSET) // PWM_INTS
// Interrupt status after masking & forcing
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 ints;
};
pwm_irq_ctrl_hw_t irq_ctrl[1];
};
} pwm_hw_t;
#define pwm_hw ((pwm_hw_t *)PWM_BASE)
static_assert(sizeof (pwm_hw_t) == 0x00b4, "");
#endif // _HARDWARE_STRUCTS_PWM_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_RESETS_H
#define _HARDWARE_STRUCTS_RESETS_H
/**
* \file rp2040/resets.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/resets.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/resets.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/** \brief Resettable component numbers on RP2040 (used as typedef \ref reset_num_t)
* \ingroup hardware_resets
*/
typedef enum reset_num_rp2040 {
RESET_ADC = 0, ///< Select ADC to be reset
RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset
RESET_DMA = 2, ///< Select DMA to be reset
RESET_I2C0 = 3, ///< Select I2C0 to be reset
RESET_I2C1 = 4, ///< Select I2C1 to be reset
RESET_IO_BANK0 = 5, ///< Select IO_BANK0 to be reset
RESET_IO_QSPI = 6, ///< Select IO_QSPI to be reset
RESET_JTAG = 7, ///< Select JTAG to be reset
RESET_PADS_BANK0 = 8, ///< Select PADS_BANK0 to be reset
RESET_PADS_QSPI = 9, ///< Select PADS_QSPI to be reset
RESET_PIO0 = 10, ///< Select PIO0 to be reset
RESET_PIO1 = 11, ///< Select PIO1 to be reset
RESET_PLL_SYS = 12, ///< Select PLL_SYS to be reset
RESET_PLL_USB = 13, ///< Select PLL_USB to be reset
RESET_PWM = 14, ///< Select PWM to be reset
RESET_RTC = 15, ///< Select RTC to be reset
RESET_SPI0 = 16, ///< Select SPI0 to be reset
RESET_SPI1 = 17, ///< Select SPI1 to be reset
RESET_SYSCFG = 18, ///< Select SYSCFG to be reset
RESET_SYSINFO = 19, ///< Select SYSINFO to be reset
RESET_TBMAN = 20, ///< Select TBMAN to be reset
RESET_TIMER = 21, ///< Select TIMER to be reset
RESET_UART0 = 22, ///< Select UART0 to be reset
RESET_UART1 = 23, ///< Select UART1 to be reset
RESET_USBCTRL = 24, ///< Select USBCTRL to be reset
RESET_COUNT
} reset_num_t;
/// \tag::resets_hw[]
typedef struct {
_REG_(RESETS_RESET_OFFSET) // RESETS_RESET
// Reset control.
// 0x01000000 [24] USBCTRL (1)
// 0x00800000 [23] UART1 (1)
// 0x00400000 [22] UART0 (1)
// 0x00200000 [21] TIMER (1)
// 0x00100000 [20] TBMAN (1)
// 0x00080000 [19] SYSINFO (1)
// 0x00040000 [18] SYSCFG (1)
// 0x00020000 [17] SPI1 (1)
// 0x00010000 [16] SPI0 (1)
// 0x00008000 [15] RTC (1)
// 0x00004000 [14] PWM (1)
// 0x00002000 [13] PLL_USB (1)
// 0x00001000 [12] PLL_SYS (1)
// 0x00000800 [11] PIO1 (1)
// 0x00000400 [10] PIO0 (1)
// 0x00000200 [9] PADS_QSPI (1)
// 0x00000100 [8] PADS_BANK0 (1)
// 0x00000080 [7] JTAG (1)
// 0x00000040 [6] IO_QSPI (1)
// 0x00000020 [5] IO_BANK0 (1)
// 0x00000010 [4] I2C1 (1)
// 0x00000008 [3] I2C0 (1)
// 0x00000004 [2] DMA (1)
// 0x00000002 [1] BUSCTRL (1)
// 0x00000001 [0] ADC (1)
io_rw_32 reset;
_REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL
// Watchdog select.
// 0x01000000 [24] USBCTRL (0)
// 0x00800000 [23] UART1 (0)
// 0x00400000 [22] UART0 (0)
// 0x00200000 [21] TIMER (0)
// 0x00100000 [20] TBMAN (0)
// 0x00080000 [19] SYSINFO (0)
// 0x00040000 [18] SYSCFG (0)
// 0x00020000 [17] SPI1 (0)
// 0x00010000 [16] SPI0 (0)
// 0x00008000 [15] RTC (0)
// 0x00004000 [14] PWM (0)
// 0x00002000 [13] PLL_USB (0)
// 0x00001000 [12] PLL_SYS (0)
// 0x00000800 [11] PIO1 (0)
// 0x00000400 [10] PIO0 (0)
// 0x00000200 [9] PADS_QSPI (0)
// 0x00000100 [8] PADS_BANK0 (0)
// 0x00000080 [7] JTAG (0)
// 0x00000040 [6] IO_QSPI (0)
// 0x00000020 [5] IO_BANK0 (0)
// 0x00000010 [4] I2C1 (0)
// 0x00000008 [3] I2C0 (0)
// 0x00000004 [2] DMA (0)
// 0x00000002 [1] BUSCTRL (0)
// 0x00000001 [0] ADC (0)
io_rw_32 wdsel;
_REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE
// Reset done.
// 0x01000000 [24] USBCTRL (0)
// 0x00800000 [23] UART1 (0)
// 0x00400000 [22] UART0 (0)
// 0x00200000 [21] TIMER (0)
// 0x00100000 [20] TBMAN (0)
// 0x00080000 [19] SYSINFO (0)
// 0x00040000 [18] SYSCFG (0)
// 0x00020000 [17] SPI1 (0)
// 0x00010000 [16] SPI0 (0)
// 0x00008000 [15] RTC (0)
// 0x00004000 [14] PWM (0)
// 0x00002000 [13] PLL_USB (0)
// 0x00001000 [12] PLL_SYS (0)
// 0x00000800 [11] PIO1 (0)
// 0x00000400 [10] PIO0 (0)
// 0x00000200 [9] PADS_QSPI (0)
// 0x00000100 [8] PADS_BANK0 (0)
// 0x00000080 [7] JTAG (0)
// 0x00000040 [6] IO_QSPI (0)
// 0x00000020 [5] IO_BANK0 (0)
// 0x00000010 [4] I2C1 (0)
// 0x00000008 [3] I2C0 (0)
// 0x00000004 [2] DMA (0)
// 0x00000002 [1] BUSCTRL (0)
// 0x00000001 [0] ADC (0)
io_ro_32 reset_done;
} resets_hw_t;
/// \end::resets_hw[]
#define resets_hw ((resets_hw_t *)RESETS_BASE)
static_assert(sizeof (resets_hw_t) == 0x000c, "");
#endif // _HARDWARE_STRUCTS_RESETS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_ROSC_H
#define _HARDWARE_STRUCTS_ROSC_H
/**
* \file rp2040/rosc.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/rosc.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
// Ring Oscillator control
// 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE +
// 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring +
io_rw_32 ctrl;
_REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
// Ring Oscillator frequency control A
// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
// 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength
// 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength
// 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength
// 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength
io_rw_32 freqa;
_REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
// Ring Oscillator frequency control B
// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
// 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength
// 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength
// 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength
// 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength
io_rw_32 freqb;
_REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
// Ring Oscillator pause control
// 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC +
io_rw_32 dormant;
_REG_(ROSC_DIV_OFFSET) // ROSC_DIV
// Controls the output divider
// 0x00000fff [11:0] DIV (-) set to 0xaa0 + div where +
io_rw_32 div;
_REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
// Controls the phase shifted output
// 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa +
// 0x00000008 [3] ENABLE (1) enable the phase-shifted output +
// 0x00000004 [2] FLIP (0) invert the phase-shifted output +
// 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks +
io_rw_32 phase;
_REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
// Ring Oscillator Status
// 0x80000000 [31] STABLE (0) Oscillator is running and stable
// 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or...
// 0x00010000 [16] DIV_RUNNING (-) post-divider is running +
// 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable +
io_rw_32 status;
_REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
// Returns a 1 bit random value
// 0x00000001 [0] RANDOMBIT (1)
io_ro_32 randombit;
_REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
// A down counter running at the ROSC frequency which counts to zero and stops.
// 0x000000ff [7:0] COUNT (0x00)
io_rw_32 count;
} rosc_hw_t;
#define rosc_hw ((rosc_hw_t *)ROSC_BASE)
static_assert(sizeof (rosc_hw_t) == 0x0024, "");
#endif // _HARDWARE_STRUCTS_ROSC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_RTC_H
#define _HARDWARE_STRUCTS_RTC_H
/**
* \file rp2040/rtc.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/rtc.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1
// Divider minus 1 for the 1 second counter
// 0x0000ffff [15:0] CLKDIV_M1 (0x0000)
io_rw_32 clkdiv_m1;
_REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0
// RTC setup register 0
// 0x00fff000 [23:12] YEAR (0x000) Year
// 0x00000f00 [11:8] MONTH (0x0) Month (1
// 0x0000001f [4:0] DAY (0x00) Day of the month (1
io_rw_32 setup_0;
_REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1
// RTC setup register 1
// 0x07000000 [26:24] DOTW (0x0) Day of the week: 1-Monday
// 0x001f0000 [20:16] HOUR (0x00) Hours
// 0x00003f00 [13:8] MIN (0x00) Minutes
// 0x0000003f [5:0] SEC (0x00) Seconds
io_rw_32 setup_1;
_REG_(RTC_CTRL_OFFSET) // RTC_CTRL
// RTC Control and status
// 0x00000100 [8] FORCE_NOTLEAPYEAR (0) If set, leapyear is forced off
// 0x00000010 [4] LOAD (0) Load RTC
// 0x00000002 [1] RTC_ACTIVE (-) RTC enabled (running)
// 0x00000001 [0] RTC_ENABLE (0) Enable RTC
io_rw_32 ctrl;
_REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0
// Interrupt setup register 0
// 0x20000000 [29] MATCH_ACTIVE (-)
// 0x10000000 [28] MATCH_ENA (0) Global match enable
// 0x04000000 [26] YEAR_ENA (0) Enable year matching
// 0x02000000 [25] MONTH_ENA (0) Enable month matching
// 0x01000000 [24] DAY_ENA (0) Enable day matching
// 0x00fff000 [23:12] YEAR (0x000) Year
// 0x00000f00 [11:8] MONTH (0x0) Month (1
// 0x0000001f [4:0] DAY (0x00) Day of the month (1
io_rw_32 irq_setup_0;
_REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1
// Interrupt setup register 1
// 0x80000000 [31] DOTW_ENA (0) Enable day of the week matching
// 0x40000000 [30] HOUR_ENA (0) Enable hour matching
// 0x20000000 [29] MIN_ENA (0) Enable minute matching
// 0x10000000 [28] SEC_ENA (0) Enable second matching
// 0x07000000 [26:24] DOTW (0x0) Day of the week
// 0x001f0000 [20:16] HOUR (0x00) Hours
// 0x00003f00 [13:8] MIN (0x00) Minutes
// 0x0000003f [5:0] SEC (0x00) Seconds
io_rw_32 irq_setup_1;
_REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1
// RTC register 1
// 0x00fff000 [23:12] YEAR (-) Year
// 0x00000f00 [11:8] MONTH (-) Month (1
// 0x0000001f [4:0] DAY (-) Day of the month (1
io_ro_32 rtc_1;
_REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0
// RTC register 0 +
// 0x07000000 [26:24] DOTW (-) Day of the week
// 0x001f0000 [20:16] HOUR (-) Hours
// 0x00003f00 [13:8] MIN (-) Minutes
// 0x0000003f [5:0] SEC (-) Seconds
io_ro_32 rtc_0;
_REG_(RTC_INTR_OFFSET) // RTC_INTR
// Raw Interrupts
// 0x00000001 [0] RTC (0)
io_ro_32 intr;
_REG_(RTC_INTE_OFFSET) // RTC_INTE
// Interrupt Enable
// 0x00000001 [0] RTC (0)
io_rw_32 inte;
_REG_(RTC_INTF_OFFSET) // RTC_INTF
// Interrupt Force
// 0x00000001 [0] RTC (0)
io_rw_32 intf;
_REG_(RTC_INTS_OFFSET) // RTC_INTS
// Interrupt status after masking & forcing
// 0x00000001 [0] RTC (0)
io_ro_32 ints;
} rtc_hw_t;
#define rtc_hw ((rtc_hw_t *)RTC_BASE)
static_assert(sizeof (rtc_hw_t) == 0x0030, "");
#endif // _HARDWARE_STRUCTS_RTC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SCB_H
#define _HARDWARE_STRUCTS_SCB_H
/**
* \file rp2040/scb.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
// CPUID Base Register
// 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM
// 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: +
// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +
// 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+
// 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: +
io_ro_32 cpuid;
_REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
// Interrupt Control and State Register
// 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI
// 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit
// 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit
// 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit
// 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit
// 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted
// 0x00400000 [22] ISRPENDING (0) External interrupt pending flag
// 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority...
// 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field
io_rw_32 icsr;
_REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
// Vector Table Offset Register
// 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address
io_rw_32 vtor;
_REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
// Application Interrupt and Reset Control Register
// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
io_rw_32 aircr;
_REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
// System Control Register
// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
io_rw_32 scr;
} armv6m_scb_hw_t;
#define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))
static_assert(sizeof (armv6m_scb_hw_t) == 0x0014, "");
#endif // _HARDWARE_STRUCTS_SCB_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SIO_H
#define _HARDWARE_STRUCTS_SIO_H
/**
* \file rp2040/sio.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sio.h"
#include "hardware/structs/interp.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SIO_CPUID_OFFSET) // SIO_CPUID
// Processor core identifier
// 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when...
io_ro_32 cpuid;
_REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
// Input value for GPIO pins
// 0x3fffffff [29:0] GPIO_IN (0x00000000) Input value for GPIO0
io_ro_32 gpio_in;
_REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
// Input value for QSPI pins
// 0x0000003f [5:0] GPIO_HI_IN (0x00) Input value on QSPI IO in order 0
io_ro_32 gpio_hi_in;
uint32_t _pad0;
_REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
// GPIO output value
// 0x3fffffff [29:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0
io_rw_32 gpio_out;
_REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
// GPIO output value set
// 0x3fffffff [29:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i
io_wo_32 gpio_set;
_REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
// GPIO output value clear
// 0x3fffffff [29:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i
io_wo_32 gpio_clr;
_REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
// GPIO output value XOR
// 0x3fffffff [29:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i
io_wo_32 gpio_togl;
_REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
// GPIO output enable
// 0x3fffffff [29:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0
io_rw_32 gpio_oe;
_REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
// GPIO output enable set
// 0x3fffffff [29:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i
io_wo_32 gpio_oe_set;
_REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
// GPIO output enable clear
// 0x3fffffff [29:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i
io_wo_32 gpio_oe_clr;
_REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
// GPIO output enable XOR
// 0x3fffffff [29:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i
io_wo_32 gpio_oe_togl;
_REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
// QSPI output value
// 0x0000003f [5:0] GPIO_HI_OUT (0x00) Set output level (1/0 -> high/low) for QSPI IO0
io_rw_32 gpio_hi_out;
_REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
// QSPI output value set
// 0x0000003f [5:0] GPIO_HI_OUT_SET (0x00) Perform an atomic bit-set on GPIO_HI_OUT, i
io_wo_32 gpio_hi_set;
_REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
// QSPI output value clear
// 0x0000003f [5:0] GPIO_HI_OUT_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OUT, i
io_wo_32 gpio_hi_clr;
_REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
// QSPI output value XOR
// 0x0000003f [5:0] GPIO_HI_OUT_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OUT, i
io_wo_32 gpio_hi_togl;
_REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
// QSPI output enable
// 0x0000003f [5:0] GPIO_HI_OE (0x00) Set output enable (1/0 -> output/input) for QSPI IO0
io_rw_32 gpio_hi_oe;
_REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
// QSPI output enable set
// 0x0000003f [5:0] GPIO_HI_OE_SET (0x00) Perform an atomic bit-set on GPIO_HI_OE, i
io_wo_32 gpio_hi_oe_set;
_REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
// QSPI output enable clear
// 0x0000003f [5:0] GPIO_HI_OE_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OE, i
io_wo_32 gpio_hi_oe_clr;
_REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
// QSPI output enable XOR
// 0x0000003f [5:0] GPIO_HI_OE_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OE, i
io_wo_32 gpio_hi_oe_togl;
_REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
// Status register for inter-core FIFOs (mailboxes).
// 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty
// 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full
// 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i
// 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i
io_rw_32 fifo_st;
_REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
// Write access to this core's TX FIFO
// 0xffffffff [31:0] FIFO_WR (0x00000000)
io_wo_32 fifo_wr;
_REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
// Read access to this core's RX FIFO
// 0xffffffff [31:0] FIFO_RD (-)
io_ro_32 fifo_rd;
_REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
// Spinlock state
// 0xffffffff [31:0] SPINLOCK_ST (0x00000000)
io_ro_32 spinlock_st;
_REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND
// Divider unsigned dividend
// 0xffffffff [31:0] DIV_UDIVIDEND (0x00000000)
io_rw_32 div_udividend;
_REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR
// Divider unsigned divisor
// 0xffffffff [31:0] DIV_UDIVISOR (0x00000000)
io_rw_32 div_udivisor;
_REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND
// Divider signed dividend
// 0xffffffff [31:0] DIV_SDIVIDEND (0x00000000)
io_rw_32 div_sdividend;
_REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR
// Divider signed divisor
// 0xffffffff [31:0] DIV_SDIVISOR (0x00000000)
io_rw_32 div_sdivisor;
_REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT
// Divider result quotient
// 0xffffffff [31:0] DIV_QUOTIENT (0x00000000)
io_rw_32 div_quotient;
_REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER
// Divider result remainder
// 0xffffffff [31:0] DIV_REMAINDER (0x00000000)
io_rw_32 div_remainder;
_REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR
// Control and status register for divider
// 0x00000002 [1] DIRTY (0) Changes to 1 when any register is written, and back to 0...
// 0x00000001 [0] READY (1) Reads as 0 when a calculation is in progress, 1 otherwise
io_ro_32 div_csr;
uint32_t _pad1;
interp_hw_t interp[2];
// (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes)
_REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0
// Spinlock register 0
// 0xffffffff [31:0] SPINLOCK0 (0x00000000)
io_rw_32 spinlock[32];
} sio_hw_t;
#define sio_hw ((sio_hw_t *)SIO_BASE)
static_assert(sizeof (sio_hw_t) == 0x0180, "");
#endif // _HARDWARE_STRUCTS_SIO_H

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