mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
524 lines
26 KiB
C
524 lines
26 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : SPI
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// Version : 1
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// Bus type : apb
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// =============================================================================
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#ifndef _HARDWARE_REGS_SPI_H
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#define _HARDWARE_REGS_SPI_H
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// =============================================================================
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// Register : SPI_SSPCR0
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// Description : Control register 0, SSPCR0 on page 3-4
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#define SPI_SSPCR0_OFFSET _u(0x00000000)
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#define SPI_SSPCR0_BITS _u(0x0000ffff)
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#define SPI_SSPCR0_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCR0_SCR
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// Description : Serial clock rate. The value SCR is used to generate the
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// transmit and receive bit rate of the PrimeCell SSP. The bit
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// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
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// value from 2-254, programmed through the SSPCPSR register and
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// SCR is a value from 0-255.
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#define SPI_SSPCR0_SCR_RESET _u(0x00)
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#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00)
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#define SPI_SSPCR0_SCR_MSB _u(15)
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#define SPI_SSPCR0_SCR_LSB _u(8)
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#define SPI_SSPCR0_SCR_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCR0_SPH
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// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
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// See Motorola SPI frame format on page 2-10.
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#define SPI_SSPCR0_SPH_RESET _u(0x0)
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#define SPI_SSPCR0_SPH_BITS _u(0x00000080)
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#define SPI_SSPCR0_SPH_MSB _u(7)
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#define SPI_SSPCR0_SPH_LSB _u(7)
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#define SPI_SSPCR0_SPH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCR0_SPO
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// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
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// only. See Motorola SPI frame format on page 2-10.
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#define SPI_SSPCR0_SPO_RESET _u(0x0)
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#define SPI_SSPCR0_SPO_BITS _u(0x00000040)
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#define SPI_SSPCR0_SPO_MSB _u(6)
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#define SPI_SSPCR0_SPO_LSB _u(6)
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#define SPI_SSPCR0_SPO_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCR0_FRF
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// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
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// serial frame format. 10 National Microwire frame format. 11
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// Reserved, undefined operation.
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#define SPI_SSPCR0_FRF_RESET _u(0x0)
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#define SPI_SSPCR0_FRF_BITS _u(0x00000030)
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#define SPI_SSPCR0_FRF_MSB _u(5)
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#define SPI_SSPCR0_FRF_LSB _u(4)
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#define SPI_SSPCR0_FRF_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCR0_DSS
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// Description : Data Size Select: 0000 Reserved, undefined operation. 0001
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// Reserved, undefined operation. 0010 Reserved, undefined
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// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data.
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// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
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// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
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// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
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#define SPI_SSPCR0_DSS_RESET _u(0x0)
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#define SPI_SSPCR0_DSS_BITS _u(0x0000000f)
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#define SPI_SSPCR0_DSS_MSB _u(3)
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#define SPI_SSPCR0_DSS_LSB _u(0)
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#define SPI_SSPCR0_DSS_ACCESS "RW"
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// =============================================================================
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// Register : SPI_SSPCR1
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// Description : Control register 1, SSPCR1 on page 3-5
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#define SPI_SSPCR1_OFFSET _u(0x00000004)
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#define SPI_SSPCR1_BITS _u(0x0000000f)
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#define SPI_SSPCR1_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCR1_SOD
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// Description : Slave-mode output disable. This bit is relevant only in the
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// slave mode, MS=1. In multiple-slave systems, it is possible for
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// an PrimeCell SSP master to broadcast a message to all slaves in
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// the system while ensuring that only one slave drives data onto
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// its serial output line. In such systems the RXD lines from
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// multiple slaves could be tied together. To operate in such
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// systems, the SOD bit can be set if the PrimeCell SSP slave is
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// not supposed to drive the SSPTXD line: 0 SSP can drive the
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// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
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// output in slave mode.
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#define SPI_SSPCR1_SOD_RESET _u(0x0)
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#define SPI_SSPCR1_SOD_BITS _u(0x00000008)
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#define SPI_SSPCR1_SOD_MSB _u(3)
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#define SPI_SSPCR1_SOD_LSB _u(3)
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#define SPI_SSPCR1_SOD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCR1_MS
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// Description : Master or slave mode select. This bit can be modified only when
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// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
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// master, default. 1 Device configured as slave.
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#define SPI_SSPCR1_MS_RESET _u(0x0)
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#define SPI_SSPCR1_MS_BITS _u(0x00000004)
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#define SPI_SSPCR1_MS_MSB _u(2)
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#define SPI_SSPCR1_MS_LSB _u(2)
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#define SPI_SSPCR1_MS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCR1_SSE
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// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
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// operation enabled.
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#define SPI_SSPCR1_SSE_RESET _u(0x0)
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#define SPI_SSPCR1_SSE_BITS _u(0x00000002)
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#define SPI_SSPCR1_SSE_MSB _u(1)
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#define SPI_SSPCR1_SSE_LSB _u(1)
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#define SPI_SSPCR1_SSE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCR1_LBM
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// Description : Loop back mode: 0 Normal serial port operation enabled. 1
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// Output of transmit serial shifter is connected to input of
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// receive serial shifter internally.
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#define SPI_SSPCR1_LBM_RESET _u(0x0)
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#define SPI_SSPCR1_LBM_BITS _u(0x00000001)
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#define SPI_SSPCR1_LBM_MSB _u(0)
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#define SPI_SSPCR1_LBM_LSB _u(0)
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#define SPI_SSPCR1_LBM_ACCESS "RW"
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// =============================================================================
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// Register : SPI_SSPDR
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// Description : Data register, SSPDR on page 3-6
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#define SPI_SSPDR_OFFSET _u(0x00000008)
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#define SPI_SSPDR_BITS _u(0x0000ffff)
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#define SPI_SSPDR_RESET "-"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPDR_DATA
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// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO.
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// You must right-justify data when the PrimeCell SSP is
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// programmed for a data size that is less than 16 bits. Unused
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// bits at the top are ignored by transmit logic. The receive
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// logic automatically right-justifies.
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#define SPI_SSPDR_DATA_RESET "-"
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#define SPI_SSPDR_DATA_BITS _u(0x0000ffff)
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#define SPI_SSPDR_DATA_MSB _u(15)
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#define SPI_SSPDR_DATA_LSB _u(0)
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#define SPI_SSPDR_DATA_ACCESS "RWF"
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// =============================================================================
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// Register : SPI_SSPSR
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// Description : Status register, SSPSR on page 3-7
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#define SPI_SSPSR_OFFSET _u(0x0000000c)
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#define SPI_SSPSR_BITS _u(0x0000001f)
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#define SPI_SSPSR_RESET _u(0x00000003)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPSR_BSY
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// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
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// transmitting and/or receiving a frame or the transmit FIFO is
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// not empty.
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#define SPI_SSPSR_BSY_RESET _u(0x0)
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#define SPI_SSPSR_BSY_BITS _u(0x00000010)
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#define SPI_SSPSR_BSY_MSB _u(4)
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#define SPI_SSPSR_BSY_LSB _u(4)
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#define SPI_SSPSR_BSY_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPSR_RFF
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// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
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// FIFO is full.
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#define SPI_SSPSR_RFF_RESET _u(0x0)
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#define SPI_SSPSR_RFF_BITS _u(0x00000008)
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#define SPI_SSPSR_RFF_MSB _u(3)
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#define SPI_SSPSR_RFF_LSB _u(3)
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#define SPI_SSPSR_RFF_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPSR_RNE
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// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
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// FIFO is not empty.
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#define SPI_SSPSR_RNE_RESET _u(0x0)
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#define SPI_SSPSR_RNE_BITS _u(0x00000004)
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#define SPI_SSPSR_RNE_MSB _u(2)
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#define SPI_SSPSR_RNE_LSB _u(2)
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#define SPI_SSPSR_RNE_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPSR_TNF
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// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
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// FIFO is not full.
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#define SPI_SSPSR_TNF_RESET _u(0x1)
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#define SPI_SSPSR_TNF_BITS _u(0x00000002)
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#define SPI_SSPSR_TNF_MSB _u(1)
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#define SPI_SSPSR_TNF_LSB _u(1)
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#define SPI_SSPSR_TNF_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPSR_TFE
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// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
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// Transmit FIFO is empty.
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#define SPI_SSPSR_TFE_RESET _u(0x1)
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#define SPI_SSPSR_TFE_BITS _u(0x00000001)
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#define SPI_SSPSR_TFE_MSB _u(0)
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#define SPI_SSPSR_TFE_LSB _u(0)
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#define SPI_SSPSR_TFE_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPCPSR
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// Description : Clock prescale register, SSPCPSR on page 3-8
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#define SPI_SSPCPSR_OFFSET _u(0x00000010)
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#define SPI_SSPCPSR_BITS _u(0x000000ff)
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#define SPI_SSPCPSR_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPCPSR_CPSDVSR
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// Description : Clock prescale divisor. Must be an even number from 2-254,
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// depending on the frequency of SSPCLK. The least significant bit
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// always returns zero on reads.
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#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00)
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#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff)
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#define SPI_SSPCPSR_CPSDVSR_MSB _u(7)
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#define SPI_SSPCPSR_CPSDVSR_LSB _u(0)
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#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
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// =============================================================================
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// Register : SPI_SSPIMSC
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// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
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#define SPI_SSPIMSC_OFFSET _u(0x00000014)
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#define SPI_SSPIMSC_BITS _u(0x0000000f)
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#define SPI_SSPIMSC_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPIMSC_TXIM
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// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
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// less condition interrupt is masked. 1 Transmit FIFO half empty
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// or less condition interrupt is not masked.
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#define SPI_SSPIMSC_TXIM_RESET _u(0x0)
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#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008)
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#define SPI_SSPIMSC_TXIM_MSB _u(3)
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#define SPI_SSPIMSC_TXIM_LSB _u(3)
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#define SPI_SSPIMSC_TXIM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPIMSC_RXIM
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// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
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// condition interrupt is masked. 1 Receive FIFO half full or less
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// condition interrupt is not masked.
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#define SPI_SSPIMSC_RXIM_RESET _u(0x0)
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#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004)
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#define SPI_SSPIMSC_RXIM_MSB _u(2)
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#define SPI_SSPIMSC_RXIM_LSB _u(2)
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#define SPI_SSPIMSC_RXIM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPIMSC_RTIM
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// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no
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// read prior to timeout period interrupt is masked. 1 Receive
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// FIFO not empty and no read prior to timeout period interrupt is
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// not masked.
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#define SPI_SSPIMSC_RTIM_RESET _u(0x0)
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#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002)
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#define SPI_SSPIMSC_RTIM_MSB _u(1)
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#define SPI_SSPIMSC_RTIM_LSB _u(1)
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#define SPI_SSPIMSC_RTIM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPIMSC_RORIM
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// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
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// full condition interrupt is masked. 1 Receive FIFO written to
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// while full condition interrupt is not masked.
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#define SPI_SSPIMSC_RORIM_RESET _u(0x0)
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#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001)
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#define SPI_SSPIMSC_RORIM_MSB _u(0)
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#define SPI_SSPIMSC_RORIM_LSB _u(0)
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#define SPI_SSPIMSC_RORIM_ACCESS "RW"
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// =============================================================================
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// Register : SPI_SSPRIS
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// Description : Raw interrupt status register, SSPRIS on page 3-10
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#define SPI_SSPRIS_OFFSET _u(0x00000018)
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#define SPI_SSPRIS_BITS _u(0x0000000f)
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#define SPI_SSPRIS_RESET _u(0x00000008)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPRIS_TXRIS
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// Description : Gives the raw interrupt state, prior to masking, of the
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// SSPTXINTR interrupt
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#define SPI_SSPRIS_TXRIS_RESET _u(0x1)
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#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008)
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#define SPI_SSPRIS_TXRIS_MSB _u(3)
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#define SPI_SSPRIS_TXRIS_LSB _u(3)
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#define SPI_SSPRIS_TXRIS_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPRIS_RXRIS
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// Description : Gives the raw interrupt state, prior to masking, of the
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// SSPRXINTR interrupt
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#define SPI_SSPRIS_RXRIS_RESET _u(0x0)
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#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004)
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#define SPI_SSPRIS_RXRIS_MSB _u(2)
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#define SPI_SSPRIS_RXRIS_LSB _u(2)
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#define SPI_SSPRIS_RXRIS_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPRIS_RTRIS
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// Description : Gives the raw interrupt state, prior to masking, of the
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// SSPRTINTR interrupt
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#define SPI_SSPRIS_RTRIS_RESET _u(0x0)
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#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002)
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#define SPI_SSPRIS_RTRIS_MSB _u(1)
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#define SPI_SSPRIS_RTRIS_LSB _u(1)
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#define SPI_SSPRIS_RTRIS_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPRIS_RORRIS
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// Description : Gives the raw interrupt state, prior to masking, of the
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// SSPRORINTR interrupt
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#define SPI_SSPRIS_RORRIS_RESET _u(0x0)
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#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001)
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#define SPI_SSPRIS_RORRIS_MSB _u(0)
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#define SPI_SSPRIS_RORRIS_LSB _u(0)
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#define SPI_SSPRIS_RORRIS_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPMIS
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// Description : Masked interrupt status register, SSPMIS on page 3-11
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#define SPI_SSPMIS_OFFSET _u(0x0000001c)
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#define SPI_SSPMIS_BITS _u(0x0000000f)
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#define SPI_SSPMIS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPMIS_TXMIS
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// Description : Gives the transmit FIFO masked interrupt state, after masking,
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// of the SSPTXINTR interrupt
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#define SPI_SSPMIS_TXMIS_RESET _u(0x0)
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#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008)
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#define SPI_SSPMIS_TXMIS_MSB _u(3)
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#define SPI_SSPMIS_TXMIS_LSB _u(3)
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#define SPI_SSPMIS_TXMIS_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPMIS_RXMIS
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// Description : Gives the receive FIFO masked interrupt state, after masking,
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// of the SSPRXINTR interrupt
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#define SPI_SSPMIS_RXMIS_RESET _u(0x0)
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#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004)
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#define SPI_SSPMIS_RXMIS_MSB _u(2)
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#define SPI_SSPMIS_RXMIS_LSB _u(2)
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#define SPI_SSPMIS_RXMIS_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPMIS_RTMIS
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// Description : Gives the receive timeout masked interrupt state, after
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// masking, of the SSPRTINTR interrupt
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#define SPI_SSPMIS_RTMIS_RESET _u(0x0)
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#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002)
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#define SPI_SSPMIS_RTMIS_MSB _u(1)
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#define SPI_SSPMIS_RTMIS_LSB _u(1)
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#define SPI_SSPMIS_RTMIS_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPMIS_RORMIS
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// Description : Gives the receive over run masked interrupt status, after
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// masking, of the SSPRORINTR interrupt
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#define SPI_SSPMIS_RORMIS_RESET _u(0x0)
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#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001)
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#define SPI_SSPMIS_RORMIS_MSB _u(0)
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#define SPI_SSPMIS_RORMIS_LSB _u(0)
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#define SPI_SSPMIS_RORMIS_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPICR
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// Description : Interrupt clear register, SSPICR on page 3-11
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#define SPI_SSPICR_OFFSET _u(0x00000020)
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#define SPI_SSPICR_BITS _u(0x00000003)
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#define SPI_SSPICR_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPICR_RTIC
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// Description : Clears the SSPRTINTR interrupt
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#define SPI_SSPICR_RTIC_RESET _u(0x0)
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#define SPI_SSPICR_RTIC_BITS _u(0x00000002)
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#define SPI_SSPICR_RTIC_MSB _u(1)
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#define SPI_SSPICR_RTIC_LSB _u(1)
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#define SPI_SSPICR_RTIC_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPICR_RORIC
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// Description : Clears the SSPRORINTR interrupt
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#define SPI_SSPICR_RORIC_RESET _u(0x0)
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#define SPI_SSPICR_RORIC_BITS _u(0x00000001)
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#define SPI_SSPICR_RORIC_MSB _u(0)
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#define SPI_SSPICR_RORIC_LSB _u(0)
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#define SPI_SSPICR_RORIC_ACCESS "WC"
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// =============================================================================
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// Register : SPI_SSPDMACR
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// Description : DMA control register, SSPDMACR on page 3-12
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#define SPI_SSPDMACR_OFFSET _u(0x00000024)
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#define SPI_SSPDMACR_BITS _u(0x00000003)
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#define SPI_SSPDMACR_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPDMACR_TXDMAE
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// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
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// transmit FIFO is enabled.
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#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0)
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#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002)
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#define SPI_SSPDMACR_TXDMAE_MSB _u(1)
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#define SPI_SSPDMACR_TXDMAE_LSB _u(1)
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#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPDMACR_RXDMAE
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// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
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// receive FIFO is enabled.
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#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0)
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#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001)
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#define SPI_SSPDMACR_RXDMAE_MSB _u(0)
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#define SPI_SSPDMACR_RXDMAE_LSB _u(0)
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#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
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// =============================================================================
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// Register : SPI_SSPPERIPHID0
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// Description : Peripheral identification registers, SSPPeriphID0-3 on page
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// 3-13
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#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0)
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#define SPI_SSPPERIPHID0_BITS _u(0x000000ff)
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#define SPI_SSPPERIPHID0_RESET _u(0x00000022)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPERIPHID0_PARTNUMBER0
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// Description : These bits read back as 0x22
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#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22)
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#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
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#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7)
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#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0)
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#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPPERIPHID1
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// Description : Peripheral identification registers, SSPPeriphID0-3 on page
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// 3-13
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#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4)
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#define SPI_SSPPERIPHID1_BITS _u(0x000000ff)
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#define SPI_SSPPERIPHID1_RESET _u(0x00000010)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPERIPHID1_DESIGNER0
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// Description : These bits read back as 0x1
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#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1)
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#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
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#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7)
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#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4)
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#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPERIPHID1_PARTNUMBER1
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// Description : These bits read back as 0x0
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#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0)
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#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
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#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3)
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#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0)
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#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPPERIPHID2
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// Description : Peripheral identification registers, SSPPeriphID0-3 on page
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// 3-13
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#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8)
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#define SPI_SSPPERIPHID2_BITS _u(0x000000ff)
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#define SPI_SSPPERIPHID2_RESET _u(0x00000034)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPERIPHID2_REVISION
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// Description : These bits return the peripheral revision
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#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3)
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#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0)
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#define SPI_SSPPERIPHID2_REVISION_MSB _u(7)
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#define SPI_SSPPERIPHID2_REVISION_LSB _u(4)
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#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPERIPHID2_DESIGNER1
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// Description : These bits read back as 0x4
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#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4)
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#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
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#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3)
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#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0)
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#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPPERIPHID3
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// Description : Peripheral identification registers, SSPPeriphID0-3 on page
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// 3-13
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#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec)
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#define SPI_SSPPERIPHID3_BITS _u(0x000000ff)
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#define SPI_SSPPERIPHID3_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPERIPHID3_CONFIGURATION
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// Description : These bits read back as 0x00
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#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00)
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#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
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#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7)
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#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0)
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#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPPCELLID0
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// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
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#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0)
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#define SPI_SSPPCELLID0_BITS _u(0x000000ff)
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#define SPI_SSPPCELLID0_RESET _u(0x0000000d)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPCELLID0_SSPPCELLID0
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// Description : These bits read back as 0x0D
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#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d)
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#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff)
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#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7)
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#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0)
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#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPPCELLID1
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// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
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#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4)
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#define SPI_SSPPCELLID1_BITS _u(0x000000ff)
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#define SPI_SSPPCELLID1_RESET _u(0x000000f0)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPCELLID1_SSPPCELLID1
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// Description : These bits read back as 0xF0
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#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0)
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#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff)
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#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7)
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#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0)
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#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPPCELLID2
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// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
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#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8)
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#define SPI_SSPPCELLID2_BITS _u(0x000000ff)
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#define SPI_SSPPCELLID2_RESET _u(0x00000005)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPCELLID2_SSPPCELLID2
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// Description : These bits read back as 0x05
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#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05)
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#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff)
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#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7)
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#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0)
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#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
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// =============================================================================
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// Register : SPI_SSPPCELLID3
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// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
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#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc)
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#define SPI_SSPPCELLID3_BITS _u(0x000000ff)
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#define SPI_SSPPCELLID3_RESET _u(0x000000b1)
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// -----------------------------------------------------------------------------
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// Field : SPI_SSPPCELLID3_SSPPCELLID3
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// Description : These bits read back as 0xB1
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#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1)
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#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff)
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#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7)
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#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0)
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#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
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// =============================================================================
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#endif // _HARDWARE_REGS_SPI_H
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