mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
173 lines
6.1 KiB
C
173 lines
6.1 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_PWM_H
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#define _HARDWARE_STRUCTS_PWM_H
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/**
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* \file rp2040/pwm.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/pwm.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
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// Control and status register
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// 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running
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// 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running
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// 0x00000030 [5:4] DIVMODE (0x0)
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// 0x00000008 [3] B_INV (0) Invert output B
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// 0x00000004 [2] A_INV (0) Invert output A
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// 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation
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// 0x00000001 [0] EN (0) Enable the PWM channel
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io_rw_32 csr;
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_REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
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// INT and FRAC form a fixed-point fractional number
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// 0x00000ff0 [11:4] INT (0x01)
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// 0x0000000f [3:0] FRAC (0x0)
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io_rw_32 div;
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_REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
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// Direct access to the PWM counter
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// 0x0000ffff [15:0] CH0_CTR (0x0000)
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io_rw_32 ctr;
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_REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
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// Counter compare values
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// 0xffff0000 [31:16] B (0x0000)
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// 0x0000ffff [15:0] A (0x0000)
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io_rw_32 cc;
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_REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
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// Counter wrap value
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// 0x0000ffff [15:0] CH0_TOP (0xffff)
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io_rw_32 top;
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} pwm_slice_hw_t;
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typedef struct {
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_REG_(PWM_INTE_OFFSET) // PWM_INTE
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// Interrupt Enable
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// 0x00000080 [7] CH7 (0)
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// 0x00000040 [6] CH6 (0)
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// 0x00000020 [5] CH5 (0)
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// 0x00000010 [4] CH4 (0)
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// 0x00000008 [3] CH3 (0)
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// 0x00000004 [2] CH2 (0)
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// 0x00000002 [1] CH1 (0)
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// 0x00000001 [0] CH0 (0)
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io_rw_32 inte;
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_REG_(PWM_INTF_OFFSET) // PWM_INTF
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// Interrupt Force
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// 0x00000080 [7] CH7 (0)
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// 0x00000040 [6] CH6 (0)
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// 0x00000020 [5] CH5 (0)
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// 0x00000010 [4] CH4 (0)
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// 0x00000008 [3] CH3 (0)
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// 0x00000004 [2] CH2 (0)
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// 0x00000002 [1] CH1 (0)
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// 0x00000001 [0] CH0 (0)
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io_rw_32 intf;
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_REG_(PWM_INTS_OFFSET) // PWM_INTS
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// Interrupt status after masking & forcing
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// 0x00000080 [7] CH7 (0)
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// 0x00000040 [6] CH6 (0)
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// 0x00000020 [5] CH5 (0)
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// 0x00000010 [4] CH4 (0)
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// 0x00000008 [3] CH3 (0)
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// 0x00000004 [2] CH2 (0)
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// 0x00000002 [1] CH1 (0)
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// 0x00000001 [0] CH0 (0)
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io_ro_32 ints;
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} pwm_irq_ctrl_hw_t;
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typedef struct {
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pwm_slice_hw_t slice[8];
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_REG_(PWM_EN_OFFSET) // PWM_EN
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// This register aliases the CSR_EN bits for all channels
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// 0x00000080 [7] CH7 (0)
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// 0x00000040 [6] CH6 (0)
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// 0x00000020 [5] CH5 (0)
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// 0x00000010 [4] CH4 (0)
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// 0x00000008 [3] CH3 (0)
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// 0x00000004 [2] CH2 (0)
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// 0x00000002 [1] CH1 (0)
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// 0x00000001 [0] CH0 (0)
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io_rw_32 en;
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_REG_(PWM_INTR_OFFSET) // PWM_INTR
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// Raw Interrupts
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// 0x00000080 [7] CH7 (0)
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// 0x00000040 [6] CH6 (0)
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// 0x00000020 [5] CH5 (0)
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// 0x00000010 [4] CH4 (0)
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// 0x00000008 [3] CH3 (0)
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// 0x00000004 [2] CH2 (0)
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// 0x00000002 [1] CH1 (0)
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// 0x00000001 [0] CH0 (0)
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io_rw_32 intr;
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union {
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struct {
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_REG_(PWM_INTE_OFFSET) // PWM_INTE
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// Interrupt Enable
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// 0x00000080 [7] CH7 (0)
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// 0x00000040 [6] CH6 (0)
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// 0x00000020 [5] CH5 (0)
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// 0x00000010 [4] CH4 (0)
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// 0x00000008 [3] CH3 (0)
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// 0x00000004 [2] CH2 (0)
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// 0x00000002 [1] CH1 (0)
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// 0x00000001 [0] CH0 (0)
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io_rw_32 inte;
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_REG_(PWM_INTF_OFFSET) // PWM_INTF
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// Interrupt Force
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// 0x00000080 [7] CH7 (0)
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// 0x00000040 [6] CH6 (0)
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// 0x00000020 [5] CH5 (0)
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// 0x00000010 [4] CH4 (0)
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// 0x00000008 [3] CH3 (0)
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// 0x00000004 [2] CH2 (0)
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// 0x00000002 [1] CH1 (0)
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// 0x00000001 [0] CH0 (0)
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io_rw_32 intf;
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_REG_(PWM_INTS_OFFSET) // PWM_INTS
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// Interrupt status after masking & forcing
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// 0x00000080 [7] CH7 (0)
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// 0x00000040 [6] CH6 (0)
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// 0x00000020 [5] CH5 (0)
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// 0x00000010 [4] CH4 (0)
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// 0x00000008 [3] CH3 (0)
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// 0x00000004 [2] CH2 (0)
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// 0x00000002 [1] CH1 (0)
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// 0x00000001 [0] CH0 (0)
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io_rw_32 ints;
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};
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pwm_irq_ctrl_hw_t irq_ctrl[1];
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};
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} pwm_hw_t;
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#define pwm_hw ((pwm_hw_t *)PWM_BASE)
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static_assert(sizeof (pwm_hw_t) == 0x00b4, "");
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#endif // _HARDWARE_STRUCTS_PWM_H
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