mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
227 lines
11 KiB
C
227 lines
11 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : WATCHDOG
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// Version : 1
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// Bus type : apb
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// =============================================================================
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#ifndef _HARDWARE_REGS_WATCHDOG_H
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#define _HARDWARE_REGS_WATCHDOG_H
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// =============================================================================
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// Register : WATCHDOG_CTRL
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// Description : Watchdog control
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// The rst_wdsel register determines which subsystems are reset
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// when the watchdog is triggered.
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// The watchdog can be triggered in software.
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#define WATCHDOG_CTRL_OFFSET _u(0x00000000)
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#define WATCHDOG_CTRL_BITS _u(0xc7ffffff)
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#define WATCHDOG_CTRL_RESET _u(0x07000000)
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_CTRL_TRIGGER
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// Description : Trigger a watchdog reset
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#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0)
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#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000)
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#define WATCHDOG_CTRL_TRIGGER_MSB _u(31)
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#define WATCHDOG_CTRL_TRIGGER_LSB _u(31)
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#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_CTRL_ENABLE
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// Description : When not enabled the watchdog timer is paused
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#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
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#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000)
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#define WATCHDOG_CTRL_ENABLE_MSB _u(30)
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#define WATCHDOG_CTRL_ENABLE_LSB _u(30)
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#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_CTRL_PAUSE_DBG1
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// Description : Pause the watchdog timer when processor 1 is in debug mode
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#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1)
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#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000)
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#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26)
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#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26)
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#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_CTRL_PAUSE_DBG0
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// Description : Pause the watchdog timer when processor 0 is in debug mode
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#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1)
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#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000)
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#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25)
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#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25)
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#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_CTRL_PAUSE_JTAG
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// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
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#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1)
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#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000)
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#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24)
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#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24)
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#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_CTRL_TIME
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// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before
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// a watchdog reset will be triggered
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#define WATCHDOG_CTRL_TIME_RESET _u(0x000000)
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#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff)
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#define WATCHDOG_CTRL_TIME_MSB _u(23)
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#define WATCHDOG_CTRL_TIME_LSB _u(0)
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#define WATCHDOG_CTRL_TIME_ACCESS "RO"
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// =============================================================================
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// Register : WATCHDOG_LOAD
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// Description : Load the watchdog timer. The maximum setting is 0xffffff which
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// corresponds to 0xffffff / 2 ticks before triggering a watchdog
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// reset (see errata RP2040-E1).
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#define WATCHDOG_LOAD_OFFSET _u(0x00000004)
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#define WATCHDOG_LOAD_BITS _u(0x00ffffff)
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#define WATCHDOG_LOAD_RESET _u(0x00000000)
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#define WATCHDOG_LOAD_MSB _u(23)
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#define WATCHDOG_LOAD_LSB _u(0)
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#define WATCHDOG_LOAD_ACCESS "WF"
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// =============================================================================
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// Register : WATCHDOG_REASON
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// Description : Logs the reason for the last reset. Both bits are zero for the
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// case of a hardware reset.
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#define WATCHDOG_REASON_OFFSET _u(0x00000008)
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#define WATCHDOG_REASON_BITS _u(0x00000003)
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#define WATCHDOG_REASON_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_REASON_FORCE
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#define WATCHDOG_REASON_FORCE_RESET _u(0x0)
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#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002)
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#define WATCHDOG_REASON_FORCE_MSB _u(1)
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#define WATCHDOG_REASON_FORCE_LSB _u(1)
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#define WATCHDOG_REASON_FORCE_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_REASON_TIMER
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#define WATCHDOG_REASON_TIMER_RESET _u(0x0)
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#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001)
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#define WATCHDOG_REASON_TIMER_MSB _u(0)
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#define WATCHDOG_REASON_TIMER_LSB _u(0)
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#define WATCHDOG_REASON_TIMER_ACCESS "RO"
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// =============================================================================
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// Register : WATCHDOG_SCRATCH0
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// Description : Scratch register. Information persists through soft reset of
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// the chip.
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#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
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#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff)
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#define WATCHDOG_SCRATCH0_RESET _u(0x00000000)
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#define WATCHDOG_SCRATCH0_MSB _u(31)
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#define WATCHDOG_SCRATCH0_LSB _u(0)
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#define WATCHDOG_SCRATCH0_ACCESS "RW"
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// =============================================================================
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// Register : WATCHDOG_SCRATCH1
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// Description : Scratch register. Information persists through soft reset of
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// the chip.
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#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
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#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff)
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#define WATCHDOG_SCRATCH1_RESET _u(0x00000000)
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#define WATCHDOG_SCRATCH1_MSB _u(31)
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#define WATCHDOG_SCRATCH1_LSB _u(0)
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#define WATCHDOG_SCRATCH1_ACCESS "RW"
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// =============================================================================
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// Register : WATCHDOG_SCRATCH2
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// Description : Scratch register. Information persists through soft reset of
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// the chip.
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#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
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#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff)
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#define WATCHDOG_SCRATCH2_RESET _u(0x00000000)
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#define WATCHDOG_SCRATCH2_MSB _u(31)
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#define WATCHDOG_SCRATCH2_LSB _u(0)
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#define WATCHDOG_SCRATCH2_ACCESS "RW"
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// =============================================================================
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// Register : WATCHDOG_SCRATCH3
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// Description : Scratch register. Information persists through soft reset of
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// the chip.
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#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
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#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff)
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#define WATCHDOG_SCRATCH3_RESET _u(0x00000000)
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#define WATCHDOG_SCRATCH3_MSB _u(31)
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#define WATCHDOG_SCRATCH3_LSB _u(0)
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#define WATCHDOG_SCRATCH3_ACCESS "RW"
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// =============================================================================
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// Register : WATCHDOG_SCRATCH4
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// Description : Scratch register. Information persists through soft reset of
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// the chip.
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#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
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#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff)
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#define WATCHDOG_SCRATCH4_RESET _u(0x00000000)
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#define WATCHDOG_SCRATCH4_MSB _u(31)
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#define WATCHDOG_SCRATCH4_LSB _u(0)
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#define WATCHDOG_SCRATCH4_ACCESS "RW"
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// =============================================================================
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// Register : WATCHDOG_SCRATCH5
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// Description : Scratch register. Information persists through soft reset of
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// the chip.
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#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
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#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff)
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#define WATCHDOG_SCRATCH5_RESET _u(0x00000000)
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#define WATCHDOG_SCRATCH5_MSB _u(31)
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#define WATCHDOG_SCRATCH5_LSB _u(0)
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#define WATCHDOG_SCRATCH5_ACCESS "RW"
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// =============================================================================
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// Register : WATCHDOG_SCRATCH6
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// Description : Scratch register. Information persists through soft reset of
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// the chip.
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#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
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#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff)
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#define WATCHDOG_SCRATCH6_RESET _u(0x00000000)
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#define WATCHDOG_SCRATCH6_MSB _u(31)
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#define WATCHDOG_SCRATCH6_LSB _u(0)
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#define WATCHDOG_SCRATCH6_ACCESS "RW"
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// =============================================================================
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// Register : WATCHDOG_SCRATCH7
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// Description : Scratch register. Information persists through soft reset of
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// the chip.
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#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
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#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff)
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#define WATCHDOG_SCRATCH7_RESET _u(0x00000000)
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#define WATCHDOG_SCRATCH7_MSB _u(31)
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#define WATCHDOG_SCRATCH7_LSB _u(0)
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#define WATCHDOG_SCRATCH7_ACCESS "RW"
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// =============================================================================
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// Register : WATCHDOG_TICK
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// Description : Controls the tick generator
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#define WATCHDOG_TICK_OFFSET _u(0x0000002c)
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#define WATCHDOG_TICK_BITS _u(0x000fffff)
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#define WATCHDOG_TICK_RESET _u(0x00000200)
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_TICK_COUNT
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// Description : Count down timer: the remaining number clk_tick cycles before
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// the next tick is generated.
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#define WATCHDOG_TICK_COUNT_RESET "-"
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#define WATCHDOG_TICK_COUNT_BITS _u(0x000ff800)
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#define WATCHDOG_TICK_COUNT_MSB _u(19)
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#define WATCHDOG_TICK_COUNT_LSB _u(11)
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#define WATCHDOG_TICK_COUNT_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_TICK_RUNNING
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// Description : Is the tick generator running?
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#define WATCHDOG_TICK_RUNNING_RESET "-"
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#define WATCHDOG_TICK_RUNNING_BITS _u(0x00000400)
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#define WATCHDOG_TICK_RUNNING_MSB _u(10)
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#define WATCHDOG_TICK_RUNNING_LSB _u(10)
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#define WATCHDOG_TICK_RUNNING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_TICK_ENABLE
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// Description : start / stop tick generation
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#define WATCHDOG_TICK_ENABLE_RESET _u(0x1)
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#define WATCHDOG_TICK_ENABLE_BITS _u(0x00000200)
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#define WATCHDOG_TICK_ENABLE_MSB _u(9)
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#define WATCHDOG_TICK_ENABLE_LSB _u(9)
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#define WATCHDOG_TICK_ENABLE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : WATCHDOG_TICK_CYCLES
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// Description : Total number of clk_tick cycles before the next tick.
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#define WATCHDOG_TICK_CYCLES_RESET _u(0x000)
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#define WATCHDOG_TICK_CYCLES_BITS _u(0x000001ff)
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#define WATCHDOG_TICK_CYCLES_MSB _u(8)
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#define WATCHDOG_TICK_CYCLES_LSB _u(0)
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#define WATCHDOG_TICK_CYCLES_ACCESS "RW"
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// =============================================================================
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#endif // _HARDWARE_REGS_WATCHDOG_H
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