mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
320 lines
15 KiB
C
320 lines
15 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : TIMER
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// Version : 1
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// Bus type : apb
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// Description : Controls time and alarms
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// time is a 64 bit value indicating the time in usec since
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// power-on
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// timeh is the top 32 bits of time & timel is the bottom 32
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// bits
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// to change time write to timelw before timehw
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// to read time read from timelr before timehr
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// An alarm is set by setting alarm_enable and writing to the
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// corresponding alarm register
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// When an alarm is pending, the corresponding alarm_running
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// signal will be high
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// An alarm can be cancelled before it has finished by clearing
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// the alarm_enable
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// When an alarm fires, the corresponding alarm_irq is set and
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// alarm_running is cleared
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// To clear the interrupt write a 1 to the corresponding
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// alarm_irq
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// =============================================================================
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#ifndef _HARDWARE_REGS_TIMER_H
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#define _HARDWARE_REGS_TIMER_H
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// =============================================================================
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// Register : TIMER_TIMEHW
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// Description : Write to bits 63:32 of time
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// always write timelw before timehw
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#define TIMER_TIMEHW_OFFSET _u(0x00000000)
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#define TIMER_TIMEHW_BITS _u(0xffffffff)
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#define TIMER_TIMEHW_RESET _u(0x00000000)
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#define TIMER_TIMEHW_MSB _u(31)
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#define TIMER_TIMEHW_LSB _u(0)
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#define TIMER_TIMEHW_ACCESS "WF"
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// =============================================================================
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// Register : TIMER_TIMELW
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// Description : Write to bits 31:0 of time
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// writes do not get copied to time until timehw is written
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#define TIMER_TIMELW_OFFSET _u(0x00000004)
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#define TIMER_TIMELW_BITS _u(0xffffffff)
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#define TIMER_TIMELW_RESET _u(0x00000000)
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#define TIMER_TIMELW_MSB _u(31)
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#define TIMER_TIMELW_LSB _u(0)
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#define TIMER_TIMELW_ACCESS "WF"
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// =============================================================================
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// Register : TIMER_TIMEHR
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// Description : Read from bits 63:32 of time
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// always read timelr before timehr
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#define TIMER_TIMEHR_OFFSET _u(0x00000008)
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#define TIMER_TIMEHR_BITS _u(0xffffffff)
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#define TIMER_TIMEHR_RESET _u(0x00000000)
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#define TIMER_TIMEHR_MSB _u(31)
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#define TIMER_TIMEHR_LSB _u(0)
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#define TIMER_TIMEHR_ACCESS "RO"
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// =============================================================================
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// Register : TIMER_TIMELR
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// Description : Read from bits 31:0 of time
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#define TIMER_TIMELR_OFFSET _u(0x0000000c)
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#define TIMER_TIMELR_BITS _u(0xffffffff)
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#define TIMER_TIMELR_RESET _u(0x00000000)
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#define TIMER_TIMELR_MSB _u(31)
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#define TIMER_TIMELR_LSB _u(0)
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#define TIMER_TIMELR_ACCESS "RO"
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// =============================================================================
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// Register : TIMER_ALARM0
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// Description : Arm alarm 0, and configure the time it will fire.
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// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
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// The alarm will disarm itself once it fires, and can
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// be disarmed early using the ARMED status register.
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#define TIMER_ALARM0_OFFSET _u(0x00000010)
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#define TIMER_ALARM0_BITS _u(0xffffffff)
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#define TIMER_ALARM0_RESET _u(0x00000000)
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#define TIMER_ALARM0_MSB _u(31)
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#define TIMER_ALARM0_LSB _u(0)
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#define TIMER_ALARM0_ACCESS "RW"
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// =============================================================================
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// Register : TIMER_ALARM1
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// Description : Arm alarm 1, and configure the time it will fire.
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// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
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// The alarm will disarm itself once it fires, and can
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// be disarmed early using the ARMED status register.
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#define TIMER_ALARM1_OFFSET _u(0x00000014)
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#define TIMER_ALARM1_BITS _u(0xffffffff)
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#define TIMER_ALARM1_RESET _u(0x00000000)
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#define TIMER_ALARM1_MSB _u(31)
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#define TIMER_ALARM1_LSB _u(0)
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#define TIMER_ALARM1_ACCESS "RW"
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// =============================================================================
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// Register : TIMER_ALARM2
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// Description : Arm alarm 2, and configure the time it will fire.
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// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
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// The alarm will disarm itself once it fires, and can
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// be disarmed early using the ARMED status register.
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#define TIMER_ALARM2_OFFSET _u(0x00000018)
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#define TIMER_ALARM2_BITS _u(0xffffffff)
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#define TIMER_ALARM2_RESET _u(0x00000000)
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#define TIMER_ALARM2_MSB _u(31)
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#define TIMER_ALARM2_LSB _u(0)
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#define TIMER_ALARM2_ACCESS "RW"
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// =============================================================================
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// Register : TIMER_ALARM3
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// Description : Arm alarm 3, and configure the time it will fire.
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// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
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// The alarm will disarm itself once it fires, and can
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// be disarmed early using the ARMED status register.
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#define TIMER_ALARM3_OFFSET _u(0x0000001c)
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#define TIMER_ALARM3_BITS _u(0xffffffff)
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#define TIMER_ALARM3_RESET _u(0x00000000)
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#define TIMER_ALARM3_MSB _u(31)
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#define TIMER_ALARM3_LSB _u(0)
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#define TIMER_ALARM3_ACCESS "RW"
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// =============================================================================
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// Register : TIMER_ARMED
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// Description : Indicates the armed/disarmed status of each alarm.
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// A write to the corresponding ALARMx register arms the alarm.
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// Alarms automatically disarm upon firing, but writing ones here
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// will disarm immediately without waiting to fire.
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#define TIMER_ARMED_OFFSET _u(0x00000020)
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#define TIMER_ARMED_BITS _u(0x0000000f)
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#define TIMER_ARMED_RESET _u(0x00000000)
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#define TIMER_ARMED_MSB _u(3)
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#define TIMER_ARMED_LSB _u(0)
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#define TIMER_ARMED_ACCESS "WC"
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// =============================================================================
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// Register : TIMER_TIMERAWH
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// Description : Raw read from bits 63:32 of time (no side effects)
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#define TIMER_TIMERAWH_OFFSET _u(0x00000024)
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#define TIMER_TIMERAWH_BITS _u(0xffffffff)
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#define TIMER_TIMERAWH_RESET _u(0x00000000)
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#define TIMER_TIMERAWH_MSB _u(31)
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#define TIMER_TIMERAWH_LSB _u(0)
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#define TIMER_TIMERAWH_ACCESS "RO"
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// =============================================================================
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// Register : TIMER_TIMERAWL
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// Description : Raw read from bits 31:0 of time (no side effects)
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#define TIMER_TIMERAWL_OFFSET _u(0x00000028)
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#define TIMER_TIMERAWL_BITS _u(0xffffffff)
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#define TIMER_TIMERAWL_RESET _u(0x00000000)
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#define TIMER_TIMERAWL_MSB _u(31)
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#define TIMER_TIMERAWL_LSB _u(0)
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#define TIMER_TIMERAWL_ACCESS "RO"
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// =============================================================================
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// Register : TIMER_DBGPAUSE
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// Description : Set bits high to enable pause when the corresponding debug
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// ports are active
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#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
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#define TIMER_DBGPAUSE_BITS _u(0x00000006)
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#define TIMER_DBGPAUSE_RESET _u(0x00000007)
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// -----------------------------------------------------------------------------
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// Field : TIMER_DBGPAUSE_DBG1
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// Description : Pause when processor 1 is in debug mode
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#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1)
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#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004)
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#define TIMER_DBGPAUSE_DBG1_MSB _u(2)
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#define TIMER_DBGPAUSE_DBG1_LSB _u(2)
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#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : TIMER_DBGPAUSE_DBG0
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// Description : Pause when processor 0 is in debug mode
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#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1)
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#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002)
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#define TIMER_DBGPAUSE_DBG0_MSB _u(1)
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#define TIMER_DBGPAUSE_DBG0_LSB _u(1)
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#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
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// =============================================================================
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// Register : TIMER_PAUSE
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// Description : Set high to pause the timer
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#define TIMER_PAUSE_OFFSET _u(0x00000030)
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#define TIMER_PAUSE_BITS _u(0x00000001)
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#define TIMER_PAUSE_RESET _u(0x00000000)
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#define TIMER_PAUSE_MSB _u(0)
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#define TIMER_PAUSE_LSB _u(0)
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#define TIMER_PAUSE_ACCESS "RW"
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// =============================================================================
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// Register : TIMER_INTR
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// Description : Raw Interrupts
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#define TIMER_INTR_OFFSET _u(0x00000034)
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#define TIMER_INTR_BITS _u(0x0000000f)
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#define TIMER_INTR_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTR_ALARM_3
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#define TIMER_INTR_ALARM_3_RESET _u(0x0)
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#define TIMER_INTR_ALARM_3_BITS _u(0x00000008)
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#define TIMER_INTR_ALARM_3_MSB _u(3)
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#define TIMER_INTR_ALARM_3_LSB _u(3)
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#define TIMER_INTR_ALARM_3_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTR_ALARM_2
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#define TIMER_INTR_ALARM_2_RESET _u(0x0)
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#define TIMER_INTR_ALARM_2_BITS _u(0x00000004)
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#define TIMER_INTR_ALARM_2_MSB _u(2)
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#define TIMER_INTR_ALARM_2_LSB _u(2)
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#define TIMER_INTR_ALARM_2_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTR_ALARM_1
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#define TIMER_INTR_ALARM_1_RESET _u(0x0)
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#define TIMER_INTR_ALARM_1_BITS _u(0x00000002)
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#define TIMER_INTR_ALARM_1_MSB _u(1)
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#define TIMER_INTR_ALARM_1_LSB _u(1)
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#define TIMER_INTR_ALARM_1_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTR_ALARM_0
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#define TIMER_INTR_ALARM_0_RESET _u(0x0)
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#define TIMER_INTR_ALARM_0_BITS _u(0x00000001)
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#define TIMER_INTR_ALARM_0_MSB _u(0)
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#define TIMER_INTR_ALARM_0_LSB _u(0)
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#define TIMER_INTR_ALARM_0_ACCESS "WC"
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// =============================================================================
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// Register : TIMER_INTE
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// Description : Interrupt Enable
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#define TIMER_INTE_OFFSET _u(0x00000038)
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#define TIMER_INTE_BITS _u(0x0000000f)
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#define TIMER_INTE_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTE_ALARM_3
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#define TIMER_INTE_ALARM_3_RESET _u(0x0)
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#define TIMER_INTE_ALARM_3_BITS _u(0x00000008)
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#define TIMER_INTE_ALARM_3_MSB _u(3)
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#define TIMER_INTE_ALARM_3_LSB _u(3)
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#define TIMER_INTE_ALARM_3_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTE_ALARM_2
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#define TIMER_INTE_ALARM_2_RESET _u(0x0)
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#define TIMER_INTE_ALARM_2_BITS _u(0x00000004)
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#define TIMER_INTE_ALARM_2_MSB _u(2)
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#define TIMER_INTE_ALARM_2_LSB _u(2)
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#define TIMER_INTE_ALARM_2_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTE_ALARM_1
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#define TIMER_INTE_ALARM_1_RESET _u(0x0)
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#define TIMER_INTE_ALARM_1_BITS _u(0x00000002)
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#define TIMER_INTE_ALARM_1_MSB _u(1)
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#define TIMER_INTE_ALARM_1_LSB _u(1)
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#define TIMER_INTE_ALARM_1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTE_ALARM_0
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#define TIMER_INTE_ALARM_0_RESET _u(0x0)
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#define TIMER_INTE_ALARM_0_BITS _u(0x00000001)
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#define TIMER_INTE_ALARM_0_MSB _u(0)
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#define TIMER_INTE_ALARM_0_LSB _u(0)
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#define TIMER_INTE_ALARM_0_ACCESS "RW"
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// =============================================================================
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// Register : TIMER_INTF
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// Description : Interrupt Force
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#define TIMER_INTF_OFFSET _u(0x0000003c)
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#define TIMER_INTF_BITS _u(0x0000000f)
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#define TIMER_INTF_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTF_ALARM_3
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#define TIMER_INTF_ALARM_3_RESET _u(0x0)
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#define TIMER_INTF_ALARM_3_BITS _u(0x00000008)
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#define TIMER_INTF_ALARM_3_MSB _u(3)
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#define TIMER_INTF_ALARM_3_LSB _u(3)
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#define TIMER_INTF_ALARM_3_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTF_ALARM_2
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#define TIMER_INTF_ALARM_2_RESET _u(0x0)
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#define TIMER_INTF_ALARM_2_BITS _u(0x00000004)
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#define TIMER_INTF_ALARM_2_MSB _u(2)
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#define TIMER_INTF_ALARM_2_LSB _u(2)
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#define TIMER_INTF_ALARM_2_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTF_ALARM_1
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#define TIMER_INTF_ALARM_1_RESET _u(0x0)
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#define TIMER_INTF_ALARM_1_BITS _u(0x00000002)
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#define TIMER_INTF_ALARM_1_MSB _u(1)
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#define TIMER_INTF_ALARM_1_LSB _u(1)
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#define TIMER_INTF_ALARM_1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTF_ALARM_0
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#define TIMER_INTF_ALARM_0_RESET _u(0x0)
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#define TIMER_INTF_ALARM_0_BITS _u(0x00000001)
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#define TIMER_INTF_ALARM_0_MSB _u(0)
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#define TIMER_INTF_ALARM_0_LSB _u(0)
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#define TIMER_INTF_ALARM_0_ACCESS "RW"
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// =============================================================================
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// Register : TIMER_INTS
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// Description : Interrupt status after masking & forcing
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#define TIMER_INTS_OFFSET _u(0x00000040)
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#define TIMER_INTS_BITS _u(0x0000000f)
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#define TIMER_INTS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTS_ALARM_3
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#define TIMER_INTS_ALARM_3_RESET _u(0x0)
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#define TIMER_INTS_ALARM_3_BITS _u(0x00000008)
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#define TIMER_INTS_ALARM_3_MSB _u(3)
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#define TIMER_INTS_ALARM_3_LSB _u(3)
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#define TIMER_INTS_ALARM_3_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTS_ALARM_2
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#define TIMER_INTS_ALARM_2_RESET _u(0x0)
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#define TIMER_INTS_ALARM_2_BITS _u(0x00000004)
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#define TIMER_INTS_ALARM_2_MSB _u(2)
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#define TIMER_INTS_ALARM_2_LSB _u(2)
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#define TIMER_INTS_ALARM_2_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTS_ALARM_1
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#define TIMER_INTS_ALARM_1_RESET _u(0x0)
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#define TIMER_INTS_ALARM_1_BITS _u(0x00000002)
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#define TIMER_INTS_ALARM_1_MSB _u(1)
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#define TIMER_INTS_ALARM_1_LSB _u(1)
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#define TIMER_INTS_ALARM_1_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : TIMER_INTS_ALARM_0
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#define TIMER_INTS_ALARM_0_RESET _u(0x0)
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#define TIMER_INTS_ALARM_0_BITS _u(0x00000001)
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#define TIMER_INTS_ALARM_0_MSB _u(0)
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#define TIMER_INTS_ALARM_0_LSB _u(0)
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#define TIMER_INTS_ALARM_0_ACCESS "RO"
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// =============================================================================
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#endif // _HARDWARE_REGS_TIMER_H
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