mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
75 lines
3.3 KiB
C
75 lines
3.3 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_SCB_H
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#define _HARDWARE_STRUCTS_SCB_H
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/**
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* \file rp2040/scb.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/m0plus.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
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// CPUID Base Register
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// 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM
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// 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: +
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// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +
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// 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+
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// 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: +
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io_ro_32 cpuid;
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_REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
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// Interrupt Control and State Register
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// 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI
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// 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit
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// 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit
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// 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit
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// 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit
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// 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted
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// 0x00400000 [22] ISRPENDING (0) External interrupt pending flag
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// 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority...
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// 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field
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io_rw_32 icsr;
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_REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
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// Vector Table Offset Register
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// 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address
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io_rw_32 vtor;
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_REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
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// Application Interrupt and Reset Control Register
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// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
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// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
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// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
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// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
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io_rw_32 aircr;
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_REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
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// System Control Register
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// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
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// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
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// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
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io_rw_32 scr;
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} armv6m_scb_hw_t;
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#define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))
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static_assert(sizeof (armv6m_scb_hw_t) == 0x0014, "");
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#endif // _HARDWARE_STRUCTS_SCB_H
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