mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
86 lines
3.2 KiB
C
86 lines
3.2 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_BUSCTRL_H
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#define _HARDWARE_STRUCTS_BUSCTRL_H
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/**
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* \file rp2040/busctrl.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/busctrl.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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/** \brief Bus fabric performance counters on RP2040 (used as typedef \ref bus_ctrl_perf_counter_t)
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* \ingroup hardware_busctrl
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*/
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typedef enum bus_ctrl_perf_counter_rp2040 {
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arbiter_rom_perf_event_access = 19,
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arbiter_rom_perf_event_access_contested = 18,
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arbiter_xip_main_perf_event_access = 17,
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arbiter_xip_main_perf_event_access_contested = 16,
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arbiter_sram0_perf_event_access = 15,
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arbiter_sram0_perf_event_access_contested = 14,
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arbiter_sram1_perf_event_access = 13,
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arbiter_sram1_perf_event_access_contested = 12,
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arbiter_sram2_perf_event_access = 11,
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arbiter_sram2_perf_event_access_contested = 10,
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arbiter_sram3_perf_event_access = 9,
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arbiter_sram3_perf_event_access_contested = 8,
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arbiter_sram4_perf_event_access = 7,
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arbiter_sram4_perf_event_access_contested = 6,
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arbiter_sram5_perf_event_access = 5,
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arbiter_sram5_perf_event_access_contested = 4,
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arbiter_fastperi_perf_event_access = 3,
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arbiter_fastperi_perf_event_access_contested = 2,
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arbiter_apb_perf_event_access = 1,
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arbiter_apb_perf_event_access_contested = 0
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} bus_ctrl_perf_counter_t;
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typedef struct {
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_REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
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// Bus fabric performance counter 0
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// 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 +
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io_rw_32 value;
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_REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
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// Bus fabric performance event select for PERFCTR0
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// 0x0000001f [4:0] PERFSEL0 (0x1f) Select an event for PERFCTR0
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io_rw_32 sel;
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} bus_ctrl_perf_hw_t;
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typedef struct {
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_REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
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// Set the priority of each master for bus arbitration
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// 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority
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// 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority
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// 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority
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// 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority
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io_rw_32 priority;
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_REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
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// Bus priority acknowledge
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// 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new...
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io_ro_32 priority_ack;
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bus_ctrl_perf_hw_t counter[4];
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} busctrl_hw_t;
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#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE)
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static_assert(sizeof (busctrl_hw_t) == 0x0028, "");
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#endif // _HARDWARE_STRUCTS_BUSCTRL_H
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