mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
97 lines
3.9 KiB
C
97 lines
3.9 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_ADC_H
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#define _HARDWARE_STRUCTS_ADC_H
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/**
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* \file rp2040/adc.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/adc.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(ADC_CS_OFFSET) // ADC_CS
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// ADC Control and Status
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// 0x001f0000 [20:16] RROBIN (0x00) Round-robin sampling
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// 0x00007000 [14:12] AINSEL (0x0) Select analog mux input
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// 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error
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// 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;...
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// 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion
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// 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1
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// 0x00000004 [2] START_ONCE (0) Start a single conversion
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// 0x00000002 [1] TS_EN (0) Power on temperature sensor
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// 0x00000001 [0] EN (0) Power on ADC and enable its clock
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io_rw_32 cs;
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_REG_(ADC_RESULT_OFFSET) // ADC_RESULT
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// Result of most recent ADC conversion
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// 0x00000fff [11:0] RESULT (0x000)
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io_ro_32 result;
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_REG_(ADC_FCS_OFFSET) // ADC_FCS
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// FIFO control and status
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// 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold
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// 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO
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// 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed
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// 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed
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// 0x00000200 [9] FULL (0)
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// 0x00000100 [8] EMPTY (0)
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// 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data
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// 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside...
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// 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size
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// 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion
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io_rw_32 fcs;
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_REG_(ADC_FIFO_OFFSET) // ADC_FIFO
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// Conversion result FIFO
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// 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error
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// 0x00000fff [11:0] VAL (-)
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io_ro_32 fifo;
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_REG_(ADC_DIV_OFFSET) // ADC_DIV
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// Clock divider
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// 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor
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// 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor
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io_rw_32 div;
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_REG_(ADC_INTR_OFFSET) // ADC_INTR
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// Raw Interrupts
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// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
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io_ro_32 intr;
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_REG_(ADC_INTE_OFFSET) // ADC_INTE
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// Interrupt Enable
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// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
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io_rw_32 inte;
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_REG_(ADC_INTF_OFFSET) // ADC_INTF
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// Interrupt Force
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// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
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io_rw_32 intf;
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_REG_(ADC_INTS_OFFSET) // ADC_INTS
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// Interrupt status after masking & forcing
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// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
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io_ro_32 ints;
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} adc_hw_t;
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#define adc_hw ((adc_hw_t *)ADC_BASE)
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static_assert(sizeof (adc_hw_t) == 0x0024, "");
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#endif // _HARDWARE_STRUCTS_ADC_H
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