mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
315 lines
14 KiB
C
315 lines
14 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : ADC
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// Version : 2
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// Bus type : apb
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// Description : Control and data interface to SAR ADC
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// =============================================================================
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#ifndef _HARDWARE_REGS_ADC_H
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#define _HARDWARE_REGS_ADC_H
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// =============================================================================
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// Register : ADC_CS
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// Description : ADC Control and Status
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#define ADC_CS_OFFSET _u(0x00000000)
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#define ADC_CS_BITS _u(0x001f770f)
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#define ADC_CS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ADC_CS_RROBIN
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// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
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// disable.
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// Otherwise, the ADC will cycle through each enabled channel in a
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// round-robin fashion.
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// The first channel to be sampled will be the one currently
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// indicated by AINSEL.
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// AINSEL will be updated after each conversion with the newly-
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// selected channel.
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#define ADC_CS_RROBIN_RESET _u(0x00)
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#define ADC_CS_RROBIN_BITS _u(0x001f0000)
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#define ADC_CS_RROBIN_MSB _u(20)
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#define ADC_CS_RROBIN_LSB _u(16)
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#define ADC_CS_RROBIN_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ADC_CS_AINSEL
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// Description : Select analog mux input. Updated automatically in round-robin
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// mode.
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#define ADC_CS_AINSEL_RESET _u(0x0)
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#define ADC_CS_AINSEL_BITS _u(0x00007000)
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#define ADC_CS_AINSEL_MSB _u(14)
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#define ADC_CS_AINSEL_LSB _u(12)
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#define ADC_CS_AINSEL_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ADC_CS_ERR_STICKY
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// Description : Some past ADC conversion encountered an error. Write 1 to
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// clear.
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#define ADC_CS_ERR_STICKY_RESET _u(0x0)
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#define ADC_CS_ERR_STICKY_BITS _u(0x00000400)
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#define ADC_CS_ERR_STICKY_MSB _u(10)
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#define ADC_CS_ERR_STICKY_LSB _u(10)
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#define ADC_CS_ERR_STICKY_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : ADC_CS_ERR
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// Description : The most recent ADC conversion encountered an error; result is
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// undefined or noisy.
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#define ADC_CS_ERR_RESET _u(0x0)
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#define ADC_CS_ERR_BITS _u(0x00000200)
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#define ADC_CS_ERR_MSB _u(9)
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#define ADC_CS_ERR_LSB _u(9)
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#define ADC_CS_ERR_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : ADC_CS_READY
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// Description : 1 if the ADC is ready to start a new conversion. Implies any
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// previous conversion has completed.
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// 0 whilst conversion in progress.
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#define ADC_CS_READY_RESET _u(0x0)
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#define ADC_CS_READY_BITS _u(0x00000100)
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#define ADC_CS_READY_MSB _u(8)
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#define ADC_CS_READY_LSB _u(8)
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#define ADC_CS_READY_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : ADC_CS_START_MANY
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// Description : Continuously perform conversions whilst this bit is 1. A new
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// conversion will start immediately after the previous finishes.
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#define ADC_CS_START_MANY_RESET _u(0x0)
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#define ADC_CS_START_MANY_BITS _u(0x00000008)
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#define ADC_CS_START_MANY_MSB _u(3)
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#define ADC_CS_START_MANY_LSB _u(3)
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#define ADC_CS_START_MANY_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ADC_CS_START_ONCE
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// Description : Start a single conversion. Self-clearing. Ignored if start_many
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// is asserted.
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#define ADC_CS_START_ONCE_RESET _u(0x0)
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#define ADC_CS_START_ONCE_BITS _u(0x00000004)
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#define ADC_CS_START_ONCE_MSB _u(2)
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#define ADC_CS_START_ONCE_LSB _u(2)
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#define ADC_CS_START_ONCE_ACCESS "SC"
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// -----------------------------------------------------------------------------
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// Field : ADC_CS_TS_EN
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// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
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#define ADC_CS_TS_EN_RESET _u(0x0)
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#define ADC_CS_TS_EN_BITS _u(0x00000002)
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#define ADC_CS_TS_EN_MSB _u(1)
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#define ADC_CS_TS_EN_LSB _u(1)
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#define ADC_CS_TS_EN_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ADC_CS_EN
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// Description : Power on ADC and enable its clock.
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// 1 - enabled. 0 - disabled.
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#define ADC_CS_EN_RESET _u(0x0)
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#define ADC_CS_EN_BITS _u(0x00000001)
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#define ADC_CS_EN_MSB _u(0)
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#define ADC_CS_EN_LSB _u(0)
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#define ADC_CS_EN_ACCESS "RW"
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// =============================================================================
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// Register : ADC_RESULT
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// Description : Result of most recent ADC conversion
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#define ADC_RESULT_OFFSET _u(0x00000004)
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#define ADC_RESULT_BITS _u(0x00000fff)
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#define ADC_RESULT_RESET _u(0x00000000)
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#define ADC_RESULT_MSB _u(11)
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#define ADC_RESULT_LSB _u(0)
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#define ADC_RESULT_ACCESS "RO"
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// =============================================================================
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// Register : ADC_FCS
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// Description : FIFO control and status
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#define ADC_FCS_OFFSET _u(0x00000008)
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#define ADC_FCS_BITS _u(0x0f0f0f0f)
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#define ADC_FCS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_THRESH
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// Description : DREQ/IRQ asserted when level >= threshold
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#define ADC_FCS_THRESH_RESET _u(0x0)
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#define ADC_FCS_THRESH_BITS _u(0x0f000000)
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#define ADC_FCS_THRESH_MSB _u(27)
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#define ADC_FCS_THRESH_LSB _u(24)
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#define ADC_FCS_THRESH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_LEVEL
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// Description : The number of conversion results currently waiting in the FIFO
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#define ADC_FCS_LEVEL_RESET _u(0x0)
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#define ADC_FCS_LEVEL_BITS _u(0x000f0000)
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#define ADC_FCS_LEVEL_MSB _u(19)
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#define ADC_FCS_LEVEL_LSB _u(16)
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#define ADC_FCS_LEVEL_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_OVER
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// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
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#define ADC_FCS_OVER_RESET _u(0x0)
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#define ADC_FCS_OVER_BITS _u(0x00000800)
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#define ADC_FCS_OVER_MSB _u(11)
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#define ADC_FCS_OVER_LSB _u(11)
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#define ADC_FCS_OVER_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_UNDER
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// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
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#define ADC_FCS_UNDER_RESET _u(0x0)
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#define ADC_FCS_UNDER_BITS _u(0x00000400)
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#define ADC_FCS_UNDER_MSB _u(10)
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#define ADC_FCS_UNDER_LSB _u(10)
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#define ADC_FCS_UNDER_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_FULL
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#define ADC_FCS_FULL_RESET _u(0x0)
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#define ADC_FCS_FULL_BITS _u(0x00000200)
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#define ADC_FCS_FULL_MSB _u(9)
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#define ADC_FCS_FULL_LSB _u(9)
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#define ADC_FCS_FULL_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_EMPTY
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#define ADC_FCS_EMPTY_RESET _u(0x0)
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#define ADC_FCS_EMPTY_BITS _u(0x00000100)
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#define ADC_FCS_EMPTY_MSB _u(8)
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#define ADC_FCS_EMPTY_LSB _u(8)
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#define ADC_FCS_EMPTY_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_DREQ_EN
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// Description : If 1: assert DMA requests when FIFO contains data
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#define ADC_FCS_DREQ_EN_RESET _u(0x0)
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#define ADC_FCS_DREQ_EN_BITS _u(0x00000008)
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#define ADC_FCS_DREQ_EN_MSB _u(3)
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#define ADC_FCS_DREQ_EN_LSB _u(3)
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#define ADC_FCS_DREQ_EN_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_ERR
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// Description : If 1: conversion error bit appears in the FIFO alongside the
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// result
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#define ADC_FCS_ERR_RESET _u(0x0)
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#define ADC_FCS_ERR_BITS _u(0x00000004)
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#define ADC_FCS_ERR_MSB _u(2)
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#define ADC_FCS_ERR_LSB _u(2)
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#define ADC_FCS_ERR_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_SHIFT
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// Description : If 1: FIFO results are right-shifted to be one byte in size.
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// Enables DMA to byte buffers.
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#define ADC_FCS_SHIFT_RESET _u(0x0)
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#define ADC_FCS_SHIFT_BITS _u(0x00000002)
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#define ADC_FCS_SHIFT_MSB _u(1)
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#define ADC_FCS_SHIFT_LSB _u(1)
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#define ADC_FCS_SHIFT_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ADC_FCS_EN
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// Description : If 1: write result to the FIFO after each conversion.
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#define ADC_FCS_EN_RESET _u(0x0)
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#define ADC_FCS_EN_BITS _u(0x00000001)
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#define ADC_FCS_EN_MSB _u(0)
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#define ADC_FCS_EN_LSB _u(0)
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#define ADC_FCS_EN_ACCESS "RW"
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// =============================================================================
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// Register : ADC_FIFO
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// Description : Conversion result FIFO
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#define ADC_FIFO_OFFSET _u(0x0000000c)
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#define ADC_FIFO_BITS _u(0x00008fff)
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#define ADC_FIFO_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ADC_FIFO_ERR
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// Description : 1 if this particular sample experienced a conversion error.
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// Remains in the same location if the sample is shifted.
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#define ADC_FIFO_ERR_RESET "-"
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#define ADC_FIFO_ERR_BITS _u(0x00008000)
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#define ADC_FIFO_ERR_MSB _u(15)
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#define ADC_FIFO_ERR_LSB _u(15)
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#define ADC_FIFO_ERR_ACCESS "RF"
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// -----------------------------------------------------------------------------
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// Field : ADC_FIFO_VAL
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#define ADC_FIFO_VAL_RESET "-"
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#define ADC_FIFO_VAL_BITS _u(0x00000fff)
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#define ADC_FIFO_VAL_MSB _u(11)
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#define ADC_FIFO_VAL_LSB _u(0)
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#define ADC_FIFO_VAL_ACCESS "RF"
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// =============================================================================
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// Register : ADC_DIV
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// Description : Clock divider. If non-zero, CS_START_MANY will start
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// conversions
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// at regular intervals rather than back-to-back.
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// The divider is reset when either of these fields are written.
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// Total period is 1 + INT + FRAC / 256
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#define ADC_DIV_OFFSET _u(0x00000010)
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#define ADC_DIV_BITS _u(0x00ffffff)
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#define ADC_DIV_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ADC_DIV_INT
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// Description : Integer part of clock divisor.
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#define ADC_DIV_INT_RESET _u(0x0000)
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#define ADC_DIV_INT_BITS _u(0x00ffff00)
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#define ADC_DIV_INT_MSB _u(23)
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#define ADC_DIV_INT_LSB _u(8)
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#define ADC_DIV_INT_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : ADC_DIV_FRAC
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// Description : Fractional part of clock divisor. First-order delta-sigma.
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#define ADC_DIV_FRAC_RESET _u(0x00)
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#define ADC_DIV_FRAC_BITS _u(0x000000ff)
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#define ADC_DIV_FRAC_MSB _u(7)
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#define ADC_DIV_FRAC_LSB _u(0)
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#define ADC_DIV_FRAC_ACCESS "RW"
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// =============================================================================
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// Register : ADC_INTR
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// Description : Raw Interrupts
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#define ADC_INTR_OFFSET _u(0x00000014)
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#define ADC_INTR_BITS _u(0x00000001)
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#define ADC_INTR_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ADC_INTR_FIFO
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// Description : Triggered when the sample FIFO reaches a certain level.
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// This level can be programmed via the FCS_THRESH field.
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#define ADC_INTR_FIFO_RESET _u(0x0)
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#define ADC_INTR_FIFO_BITS _u(0x00000001)
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#define ADC_INTR_FIFO_MSB _u(0)
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#define ADC_INTR_FIFO_LSB _u(0)
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#define ADC_INTR_FIFO_ACCESS "RO"
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// =============================================================================
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// Register : ADC_INTE
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// Description : Interrupt Enable
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#define ADC_INTE_OFFSET _u(0x00000018)
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#define ADC_INTE_BITS _u(0x00000001)
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#define ADC_INTE_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ADC_INTE_FIFO
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// Description : Triggered when the sample FIFO reaches a certain level.
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// This level can be programmed via the FCS_THRESH field.
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#define ADC_INTE_FIFO_RESET _u(0x0)
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#define ADC_INTE_FIFO_BITS _u(0x00000001)
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#define ADC_INTE_FIFO_MSB _u(0)
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#define ADC_INTE_FIFO_LSB _u(0)
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#define ADC_INTE_FIFO_ACCESS "RW"
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// =============================================================================
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// Register : ADC_INTF
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// Description : Interrupt Force
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#define ADC_INTF_OFFSET _u(0x0000001c)
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#define ADC_INTF_BITS _u(0x00000001)
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#define ADC_INTF_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ADC_INTF_FIFO
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// Description : Triggered when the sample FIFO reaches a certain level.
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// This level can be programmed via the FCS_THRESH field.
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#define ADC_INTF_FIFO_RESET _u(0x0)
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#define ADC_INTF_FIFO_BITS _u(0x00000001)
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#define ADC_INTF_FIFO_MSB _u(0)
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#define ADC_INTF_FIFO_LSB _u(0)
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#define ADC_INTF_FIFO_ACCESS "RW"
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// =============================================================================
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// Register : ADC_INTS
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// Description : Interrupt status after masking & forcing
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#define ADC_INTS_OFFSET _u(0x00000020)
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#define ADC_INTS_BITS _u(0x00000001)
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#define ADC_INTS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : ADC_INTS_FIFO
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// Description : Triggered when the sample FIFO reaches a certain level.
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// This level can be programmed via the FCS_THRESH field.
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#define ADC_INTS_FIFO_RESET _u(0x0)
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#define ADC_INTS_FIFO_BITS _u(0x00000001)
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#define ADC_INTS_FIFO_MSB _u(0)
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#define ADC_INTS_FIFO_LSB _u(0)
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#define ADC_INTS_FIFO_ACCESS "RO"
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// =============================================================================
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#endif // _HARDWARE_REGS_ADC_H
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