mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
198 lines
8.6 KiB
C
198 lines
8.6 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_M0PLUS_H
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#define _HARDWARE_STRUCTS_M0PLUS_H
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/**
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* \file rp2040/m0plus.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/m0plus.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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uint32_t _pad0[14340];
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_REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
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// SysTick Control and Status Register
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// 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read
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// 0x00000004 [2] CLKSOURCE (0) SysTick clock source
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// 0x00000002 [1] TICKINT (0) Enables SysTick exception request: +
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// 0x00000001 [0] ENABLE (0) Enable SysTick counter: +
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io_rw_32 syst_csr;
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_REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
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// SysTick Reload Value Register
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// 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register...
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io_rw_32 syst_rvr;
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_REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
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// SysTick Current Value Register
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// 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter
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io_rw_32 syst_cvr;
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_REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
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// SysTick Calibration Value Register
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// 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the...
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// 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact...
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// 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)...
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io_ro_32 syst_calib;
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uint32_t _pad1[56];
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_REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
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// Interrupt Set-Enable Register
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// 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits
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io_rw_32 nvic_iser;
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uint32_t _pad2[31];
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_REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
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// Interrupt Clear-Enable Register
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// 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits
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io_rw_32 nvic_icer;
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uint32_t _pad3[31];
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_REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
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// Interrupt Set-Pending Register
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// 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits
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io_rw_32 nvic_ispr;
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uint32_t _pad4[31];
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_REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
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// Interrupt Clear-Pending Register
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// 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits
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io_rw_32 nvic_icpr;
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uint32_t _pad5[95];
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// (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
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_REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
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// Interrupt Priority Register 0
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// 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3
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// 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2
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// 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1
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// 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0
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io_rw_32 nvic_ipr[8];
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uint32_t _pad6[568];
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_REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
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// CPUID Base Register
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// 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM
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// 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: +
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// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +
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// 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+
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// 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: +
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io_ro_32 cpuid;
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_REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
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// Interrupt Control and State Register
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// 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI
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// 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit
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// 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit
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// 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit
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// 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit
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// 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted
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// 0x00400000 [22] ISRPENDING (0) External interrupt pending flag
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// 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority...
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// 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field
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io_rw_32 icsr;
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_REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
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// Vector Table Offset Register
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// 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address
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io_rw_32 vtor;
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_REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
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// Application Interrupt and Reset Control Register
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// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
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// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
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// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
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// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
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io_rw_32 aircr;
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_REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
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// System Control Register
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// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
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// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
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// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
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io_rw_32 scr;
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_REG_(M0PLUS_CCR_OFFSET) // M0PLUS_CCR
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// Configuration and Control Register
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// 0x00000200 [9] STKALIGN (0) Always reads as one, indicates 8-byte stack alignment on...
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// 0x00000008 [3] UNALIGN_TRP (0) Always reads as one, indicates that all unaligned...
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io_ro_32 ccr;
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uint32_t _pad7;
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// (Description copied from array index 0 register M0PLUS_SHPR2 applies similarly to other array indexes)
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_REG_(M0PLUS_SHPR2_OFFSET) // M0PLUS_SHPR2
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// System Handler Priority Register 2
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// 0xc0000000 [31:30] PRI_11 (0x0) Priority of system handler 11, SVCall
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io_rw_32 shpr[2];
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_REG_(M0PLUS_SHCSR_OFFSET) // M0PLUS_SHCSR
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// System Handler Control and State Register
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// 0x00008000 [15] SVCALLPENDED (0) Reads as 1 if SVCall is Pending
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io_rw_32 shcsr;
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uint32_t _pad8[26];
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_REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
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// MPU Type Register
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// 0x00ff0000 [23:16] IREGION (0x00) Instruction region
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// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
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// 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps
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io_ro_32 mpu_type;
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_REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
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// MPU Control Register
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// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a...
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// 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs
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// 0x00000001 [0] ENABLE (0) Enables the MPU
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io_rw_32 mpu_ctrl;
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_REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
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// MPU Region Number Register
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// 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and...
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io_rw_32 mpu_rnr;
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_REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
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// MPU Region Base Address Register
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// 0xffffff00 [31:8] ADDR (0x000000) Base address of the region
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// 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the...
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// 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base...
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io_rw_32 mpu_rbar;
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_REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
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// MPU Region Attribute and Size Register
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// 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field
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// 0x0000ff00 [15:8] SRD (0x00) Subregion Disable
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// 0x0000003e [5:1] SIZE (0x00) Indicates the region size
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// 0x00000001 [0] ENABLE (0) Enables the region
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io_rw_32 mpu_rasr;
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} m0plus_hw_t;
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#define ppb_hw ((m0plus_hw_t *)PPB_BASE)
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static_assert(sizeof (m0plus_hw_t) == 0xeda4, "");
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#endif // _HARDWARE_STRUCTS_M0PLUS_H
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