mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
87 lines
4.2 KiB
C
87 lines
4.2 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_INTERP_H
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#define _HARDWARE_STRUCTS_INTERP_H
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/**
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* \file rp2040/interp.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/sio.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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// (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
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_REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
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// Read/write access to accumulator 0
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// 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000)
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io_rw_32 accum[2];
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// (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
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_REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
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// Read/write access to BASE0 register
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// 0xffffffff [31:0] INTERP0_BASE0 (0x00000000)
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io_rw_32 base[3];
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// (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
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_REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
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// Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
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// 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000)
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io_ro_32 pop[3];
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// (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
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_REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
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// Read LANE0 result, without altering any internal state (PEEK)
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// 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000)
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io_ro_32 peek[3];
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// (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
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_REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
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// Control register for lane 0
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// 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set
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// 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set
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// 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set
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// 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core
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// 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the...
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// 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result
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// 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's...
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// 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this...
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// 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator...
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// 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask...
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// 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive)
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// 0x0000001f [4:0] SHIFT (0x00) Logical right-shift applied to accumulator before masking
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io_rw_32 ctrl[2];
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// (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
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_REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
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// Values written here are atomically added to ACCUM0
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// 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000)
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io_rw_32 add_raw[2];
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_REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
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// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
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// 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000)
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io_wo_32 base01;
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} interp_hw_t;
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#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET))
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static_assert(sizeof (interp_hw_t) == 0x0040, "");
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#define interp0_hw (&interp_hw_array[0])
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#define interp1_hw (&interp_hw_array[1])
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#endif // _HARDWARE_STRUCTS_INTERP_H
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