mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
344 lines
16 KiB
C
344 lines
16 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_PIO_H
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#define _HARDWARE_STRUCTS_PIO_H
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/**
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* \file rp2040/pio.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/pio.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/pio.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV
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// Clock divisor register for state machine 0 +
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// 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256)
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// 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor
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io_rw_32 clkdiv;
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_REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL
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// Execution/behavioural settings for state machine 0
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// 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,...
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// 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is...
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// 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,...
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// 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN
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// 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable
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// 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable +
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// 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins
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// 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom
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// 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address
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// 0x00000010 [4] STATUS_SEL (0) Comparison used for the MOV x, STATUS instruction
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// 0x0000000f [3:0] STATUS_N (0x0) Comparison level for the MOV x, STATUS instruction
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io_rw_32 execctrl;
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_REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL
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// Control behaviour of the input/output shift registers for state machine 0
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// 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and...
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// 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and...
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// 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or...
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// 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or...
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// 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right
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// 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left)
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// 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i
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// 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i
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io_rw_32 shiftctrl;
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_REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR
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// Current instruction address of state machine 0
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// 0x0000001f [4:0] SM0_ADDR (0x00)
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io_ro_32 addr;
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_REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR
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// Read to see the instruction currently addressed by state machine 0's program counter +
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// 0x0000ffff [15:0] SM0_INSTR (-)
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io_rw_32 instr;
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_REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL
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// State machine pin control
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// 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction...
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// 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET
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// 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS...
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// 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of...
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// 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a...
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// 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET...
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// 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT...
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io_rw_32 pinctrl;
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} pio_sm_hw_t;
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typedef struct {
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_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
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// Interrupt Enable for irq0
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_rw_32 inte;
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_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
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// Interrupt Force for irq0
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_rw_32 intf;
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_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
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// Interrupt status after masking & forcing for irq0
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_ro_32 ints;
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} pio_irq_ctrl_hw_t;
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typedef struct {
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_REG_(PIO_CTRL_OFFSET) // PIO_CTRL
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// PIO control register
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// 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial...
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// 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may...
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// 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by...
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io_rw_32 ctrl;
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_REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT
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// FIFO status register
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// 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty
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// 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full
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// 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty
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// 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full
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io_ro_32 fstat;
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_REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG
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// FIFO debug register
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// 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a...
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// 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i
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// 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i
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// 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a...
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io_rw_32 fdebug;
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_REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL
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// FIFO levels
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// 0xf0000000 [31:28] RX3 (0x0)
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// 0x0f000000 [27:24] TX3 (0x0)
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// 0x00f00000 [23:20] RX2 (0x0)
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// 0x000f0000 [19:16] TX2 (0x0)
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// 0x0000f000 [15:12] RX1 (0x0)
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// 0x00000f00 [11:8] TX1 (0x0)
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// 0x000000f0 [7:4] RX0 (0x0)
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// 0x0000000f [3:0] TX0 (0x0)
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io_ro_32 flevel;
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// (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)
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_REG_(PIO_TXF0_OFFSET) // PIO_TXF0
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// Direct write access to the TX FIFO for this state machine
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// 0xffffffff [31:0] TXF0 (0x00000000)
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io_wo_32 txf[4];
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// (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)
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_REG_(PIO_RXF0_OFFSET) // PIO_RXF0
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// Direct read access to the RX FIFO for this state machine
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// 0xffffffff [31:0] RXF0 (-)
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io_ro_32 rxf[4];
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_REG_(PIO_IRQ_OFFSET) // PIO_IRQ
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// State machine IRQ flags register
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// 0x000000ff [7:0] IRQ (0x00)
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io_rw_32 irq;
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_REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE
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// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ
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// 0x000000ff [7:0] IRQ_FORCE (0x00)
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io_wo_32 irq_force;
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_REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS
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// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities
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// 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000)
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io_rw_32 input_sync_bypass;
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_REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT
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// Read to sample the pad output values PIO is currently driving to the GPIOs
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// 0xffffffff [31:0] DBG_PADOUT (0x00000000)
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io_ro_32 dbg_padout;
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_REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE
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// Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs
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// 0xffffffff [31:0] DBG_PADOE (0x00000000)
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io_ro_32 dbg_padoe;
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_REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO
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// The PIO hardware has some free parameters that may vary between chip products
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// 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of...
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// 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with
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// 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words
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io_ro_32 dbg_cfginfo;
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// (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)
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_REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0
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// Write-only access to instruction memory location 0
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// 0x0000ffff [15:0] INSTR_MEM0 (0x0000)
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io_wo_32 instr_mem[32];
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pio_sm_hw_t sm[4];
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_REG_(PIO_INTR_OFFSET) // PIO_INTR
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// Raw Interrupts
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_ro_32 intr;
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union {
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struct {
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_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
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// Interrupt Enable for irq0
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_rw_32 inte0;
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_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
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// Interrupt Force for irq0
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_rw_32 intf0;
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_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
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// Interrupt status after masking & forcing for irq0
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_ro_32 ints0;
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_REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE
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// Interrupt Enable for irq1
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_rw_32 inte1;
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_REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF
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// Interrupt Force for irq1
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_rw_32 intf1;
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_REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS
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// Interrupt status after masking & forcing for irq1
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// 0x00000800 [11] SM3 (0)
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// 0x00000400 [10] SM2 (0)
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// 0x00000200 [9] SM1 (0)
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// 0x00000100 [8] SM0 (0)
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// 0x00000080 [7] SM3_TXNFULL (0)
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// 0x00000040 [6] SM2_TXNFULL (0)
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// 0x00000020 [5] SM1_TXNFULL (0)
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// 0x00000010 [4] SM0_TXNFULL (0)
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// 0x00000008 [3] SM3_RXNEMPTY (0)
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// 0x00000004 [2] SM2_RXNEMPTY (0)
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// 0x00000002 [1] SM1_RXNEMPTY (0)
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// 0x00000001 [0] SM0_RXNEMPTY (0)
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io_ro_32 ints1;
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};
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pio_irq_ctrl_hw_t irq_ctrl[2];
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};
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} pio_hw_t;
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#define pio0_hw ((pio_hw_t *)PIO0_BASE)
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#define pio1_hw ((pio_hw_t *)PIO1_BASE)
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static_assert(sizeof (pio_hw_t) == 0x0144, "");
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#endif // _HARDWARE_STRUCTS_PIO_H
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