mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
93 lines
3.6 KiB
C
93 lines
3.6 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_ROSC_H
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#define _HARDWARE_STRUCTS_ROSC_H
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/**
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* \file rp2040/rosc.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/rosc.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
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// Ring Oscillator control
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// 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE +
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// 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring +
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io_rw_32 ctrl;
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_REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
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// Ring Oscillator frequency control A
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// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
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// 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength
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// 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength
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// 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength
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// 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength
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io_rw_32 freqa;
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_REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
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// Ring Oscillator frequency control B
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// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
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// 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength
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// 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength
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// 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength
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// 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength
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io_rw_32 freqb;
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_REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
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// Ring Oscillator pause control
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// 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC +
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io_rw_32 dormant;
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_REG_(ROSC_DIV_OFFSET) // ROSC_DIV
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// Controls the output divider
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// 0x00000fff [11:0] DIV (-) set to 0xaa0 + div where +
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io_rw_32 div;
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_REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
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// Controls the phase shifted output
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// 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa +
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// 0x00000008 [3] ENABLE (1) enable the phase-shifted output +
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// 0x00000004 [2] FLIP (0) invert the phase-shifted output +
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// 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks +
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io_rw_32 phase;
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_REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
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// Ring Oscillator Status
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// 0x80000000 [31] STABLE (0) Oscillator is running and stable
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// 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or...
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// 0x00010000 [16] DIV_RUNNING (-) post-divider is running +
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// 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable +
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io_rw_32 status;
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_REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
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// Returns a 1 bit random value
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// 0x00000001 [0] RANDOMBIT (1)
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io_ro_32 randombit;
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_REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
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// A down counter running at the ROSC frequency which counts to zero and stops.
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// 0x000000ff [7:0] COUNT (0x00)
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io_rw_32 count;
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} rosc_hw_t;
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#define rosc_hw ((rosc_hw_t *)ROSC_BASE)
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static_assert(sizeof (rosc_hw_t) == 0x0024, "");
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#endif // _HARDWARE_STRUCTS_ROSC_H
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