mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
565 lines
27 KiB
C
565 lines
27 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : RESETS
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// Version : 1
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// Bus type : apb
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// =============================================================================
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#ifndef _HARDWARE_REGS_RESETS_H
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#define _HARDWARE_REGS_RESETS_H
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// =============================================================================
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// Register : RESETS_RESET
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// Description : Reset control. If a bit is set it means the peripheral is in
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// reset. 0 means the peripheral's reset is deasserted.
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#define RESETS_RESET_OFFSET _u(0x00000000)
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#define RESETS_RESET_BITS _u(0x01ffffff)
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#define RESETS_RESET_RESET _u(0x01ffffff)
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_USBCTRL
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#define RESETS_RESET_USBCTRL_RESET _u(0x1)
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#define RESETS_RESET_USBCTRL_BITS _u(0x01000000)
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#define RESETS_RESET_USBCTRL_MSB _u(24)
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#define RESETS_RESET_USBCTRL_LSB _u(24)
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#define RESETS_RESET_USBCTRL_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_UART1
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#define RESETS_RESET_UART1_RESET _u(0x1)
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#define RESETS_RESET_UART1_BITS _u(0x00800000)
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#define RESETS_RESET_UART1_MSB _u(23)
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#define RESETS_RESET_UART1_LSB _u(23)
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#define RESETS_RESET_UART1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_UART0
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#define RESETS_RESET_UART0_RESET _u(0x1)
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#define RESETS_RESET_UART0_BITS _u(0x00400000)
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#define RESETS_RESET_UART0_MSB _u(22)
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#define RESETS_RESET_UART0_LSB _u(22)
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#define RESETS_RESET_UART0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_TIMER
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#define RESETS_RESET_TIMER_RESET _u(0x1)
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#define RESETS_RESET_TIMER_BITS _u(0x00200000)
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#define RESETS_RESET_TIMER_MSB _u(21)
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#define RESETS_RESET_TIMER_LSB _u(21)
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#define RESETS_RESET_TIMER_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_TBMAN
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#define RESETS_RESET_TBMAN_RESET _u(0x1)
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#define RESETS_RESET_TBMAN_BITS _u(0x00100000)
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#define RESETS_RESET_TBMAN_MSB _u(20)
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#define RESETS_RESET_TBMAN_LSB _u(20)
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#define RESETS_RESET_TBMAN_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_SYSINFO
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#define RESETS_RESET_SYSINFO_RESET _u(0x1)
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#define RESETS_RESET_SYSINFO_BITS _u(0x00080000)
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#define RESETS_RESET_SYSINFO_MSB _u(19)
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#define RESETS_RESET_SYSINFO_LSB _u(19)
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#define RESETS_RESET_SYSINFO_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_SYSCFG
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#define RESETS_RESET_SYSCFG_RESET _u(0x1)
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#define RESETS_RESET_SYSCFG_BITS _u(0x00040000)
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#define RESETS_RESET_SYSCFG_MSB _u(18)
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#define RESETS_RESET_SYSCFG_LSB _u(18)
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#define RESETS_RESET_SYSCFG_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_SPI1
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#define RESETS_RESET_SPI1_RESET _u(0x1)
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#define RESETS_RESET_SPI1_BITS _u(0x00020000)
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#define RESETS_RESET_SPI1_MSB _u(17)
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#define RESETS_RESET_SPI1_LSB _u(17)
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#define RESETS_RESET_SPI1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_SPI0
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#define RESETS_RESET_SPI0_RESET _u(0x1)
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#define RESETS_RESET_SPI0_BITS _u(0x00010000)
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#define RESETS_RESET_SPI0_MSB _u(16)
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#define RESETS_RESET_SPI0_LSB _u(16)
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#define RESETS_RESET_SPI0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_RTC
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#define RESETS_RESET_RTC_RESET _u(0x1)
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#define RESETS_RESET_RTC_BITS _u(0x00008000)
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#define RESETS_RESET_RTC_MSB _u(15)
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#define RESETS_RESET_RTC_LSB _u(15)
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#define RESETS_RESET_RTC_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_PWM
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#define RESETS_RESET_PWM_RESET _u(0x1)
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#define RESETS_RESET_PWM_BITS _u(0x00004000)
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#define RESETS_RESET_PWM_MSB _u(14)
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#define RESETS_RESET_PWM_LSB _u(14)
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#define RESETS_RESET_PWM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_PLL_USB
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#define RESETS_RESET_PLL_USB_RESET _u(0x1)
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#define RESETS_RESET_PLL_USB_BITS _u(0x00002000)
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#define RESETS_RESET_PLL_USB_MSB _u(13)
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#define RESETS_RESET_PLL_USB_LSB _u(13)
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#define RESETS_RESET_PLL_USB_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_PLL_SYS
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#define RESETS_RESET_PLL_SYS_RESET _u(0x1)
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#define RESETS_RESET_PLL_SYS_BITS _u(0x00001000)
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#define RESETS_RESET_PLL_SYS_MSB _u(12)
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#define RESETS_RESET_PLL_SYS_LSB _u(12)
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#define RESETS_RESET_PLL_SYS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_PIO1
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#define RESETS_RESET_PIO1_RESET _u(0x1)
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#define RESETS_RESET_PIO1_BITS _u(0x00000800)
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#define RESETS_RESET_PIO1_MSB _u(11)
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#define RESETS_RESET_PIO1_LSB _u(11)
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#define RESETS_RESET_PIO1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_PIO0
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#define RESETS_RESET_PIO0_RESET _u(0x1)
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#define RESETS_RESET_PIO0_BITS _u(0x00000400)
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#define RESETS_RESET_PIO0_MSB _u(10)
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#define RESETS_RESET_PIO0_LSB _u(10)
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#define RESETS_RESET_PIO0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_PADS_QSPI
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#define RESETS_RESET_PADS_QSPI_RESET _u(0x1)
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#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200)
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#define RESETS_RESET_PADS_QSPI_MSB _u(9)
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#define RESETS_RESET_PADS_QSPI_LSB _u(9)
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#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_PADS_BANK0
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#define RESETS_RESET_PADS_BANK0_RESET _u(0x1)
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#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100)
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#define RESETS_RESET_PADS_BANK0_MSB _u(8)
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#define RESETS_RESET_PADS_BANK0_LSB _u(8)
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#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_JTAG
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#define RESETS_RESET_JTAG_RESET _u(0x1)
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#define RESETS_RESET_JTAG_BITS _u(0x00000080)
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#define RESETS_RESET_JTAG_MSB _u(7)
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#define RESETS_RESET_JTAG_LSB _u(7)
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#define RESETS_RESET_JTAG_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_IO_QSPI
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#define RESETS_RESET_IO_QSPI_RESET _u(0x1)
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#define RESETS_RESET_IO_QSPI_BITS _u(0x00000040)
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#define RESETS_RESET_IO_QSPI_MSB _u(6)
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#define RESETS_RESET_IO_QSPI_LSB _u(6)
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#define RESETS_RESET_IO_QSPI_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_IO_BANK0
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#define RESETS_RESET_IO_BANK0_RESET _u(0x1)
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#define RESETS_RESET_IO_BANK0_BITS _u(0x00000020)
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#define RESETS_RESET_IO_BANK0_MSB _u(5)
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#define RESETS_RESET_IO_BANK0_LSB _u(5)
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#define RESETS_RESET_IO_BANK0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_I2C1
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#define RESETS_RESET_I2C1_RESET _u(0x1)
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#define RESETS_RESET_I2C1_BITS _u(0x00000010)
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#define RESETS_RESET_I2C1_MSB _u(4)
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#define RESETS_RESET_I2C1_LSB _u(4)
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#define RESETS_RESET_I2C1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_I2C0
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#define RESETS_RESET_I2C0_RESET _u(0x1)
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#define RESETS_RESET_I2C0_BITS _u(0x00000008)
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#define RESETS_RESET_I2C0_MSB _u(3)
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#define RESETS_RESET_I2C0_LSB _u(3)
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#define RESETS_RESET_I2C0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_DMA
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#define RESETS_RESET_DMA_RESET _u(0x1)
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#define RESETS_RESET_DMA_BITS _u(0x00000004)
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#define RESETS_RESET_DMA_MSB _u(2)
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#define RESETS_RESET_DMA_LSB _u(2)
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#define RESETS_RESET_DMA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_BUSCTRL
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#define RESETS_RESET_BUSCTRL_RESET _u(0x1)
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#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002)
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#define RESETS_RESET_BUSCTRL_MSB _u(1)
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#define RESETS_RESET_BUSCTRL_LSB _u(1)
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#define RESETS_RESET_BUSCTRL_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_ADC
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#define RESETS_RESET_ADC_RESET _u(0x1)
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#define RESETS_RESET_ADC_BITS _u(0x00000001)
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#define RESETS_RESET_ADC_MSB _u(0)
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#define RESETS_RESET_ADC_LSB _u(0)
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#define RESETS_RESET_ADC_ACCESS "RW"
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// =============================================================================
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// Register : RESETS_WDSEL
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// Description : Watchdog select. If a bit is set then the watchdog will reset
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// this peripheral when the watchdog fires.
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#define RESETS_WDSEL_OFFSET _u(0x00000004)
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#define RESETS_WDSEL_BITS _u(0x01ffffff)
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#define RESETS_WDSEL_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_USBCTRL
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#define RESETS_WDSEL_USBCTRL_RESET _u(0x0)
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#define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000)
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#define RESETS_WDSEL_USBCTRL_MSB _u(24)
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#define RESETS_WDSEL_USBCTRL_LSB _u(24)
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#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_UART1
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#define RESETS_WDSEL_UART1_RESET _u(0x0)
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#define RESETS_WDSEL_UART1_BITS _u(0x00800000)
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#define RESETS_WDSEL_UART1_MSB _u(23)
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#define RESETS_WDSEL_UART1_LSB _u(23)
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#define RESETS_WDSEL_UART1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_UART0
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#define RESETS_WDSEL_UART0_RESET _u(0x0)
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#define RESETS_WDSEL_UART0_BITS _u(0x00400000)
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#define RESETS_WDSEL_UART0_MSB _u(22)
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#define RESETS_WDSEL_UART0_LSB _u(22)
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#define RESETS_WDSEL_UART0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_TIMER
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#define RESETS_WDSEL_TIMER_RESET _u(0x0)
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#define RESETS_WDSEL_TIMER_BITS _u(0x00200000)
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#define RESETS_WDSEL_TIMER_MSB _u(21)
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#define RESETS_WDSEL_TIMER_LSB _u(21)
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#define RESETS_WDSEL_TIMER_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_TBMAN
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#define RESETS_WDSEL_TBMAN_RESET _u(0x0)
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#define RESETS_WDSEL_TBMAN_BITS _u(0x00100000)
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#define RESETS_WDSEL_TBMAN_MSB _u(20)
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#define RESETS_WDSEL_TBMAN_LSB _u(20)
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#define RESETS_WDSEL_TBMAN_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_SYSINFO
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#define RESETS_WDSEL_SYSINFO_RESET _u(0x0)
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#define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000)
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#define RESETS_WDSEL_SYSINFO_MSB _u(19)
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#define RESETS_WDSEL_SYSINFO_LSB _u(19)
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#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_SYSCFG
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#define RESETS_WDSEL_SYSCFG_RESET _u(0x0)
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#define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000)
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#define RESETS_WDSEL_SYSCFG_MSB _u(18)
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#define RESETS_WDSEL_SYSCFG_LSB _u(18)
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#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_SPI1
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#define RESETS_WDSEL_SPI1_RESET _u(0x0)
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#define RESETS_WDSEL_SPI1_BITS _u(0x00020000)
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#define RESETS_WDSEL_SPI1_MSB _u(17)
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#define RESETS_WDSEL_SPI1_LSB _u(17)
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#define RESETS_WDSEL_SPI1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_SPI0
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#define RESETS_WDSEL_SPI0_RESET _u(0x0)
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#define RESETS_WDSEL_SPI0_BITS _u(0x00010000)
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#define RESETS_WDSEL_SPI0_MSB _u(16)
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#define RESETS_WDSEL_SPI0_LSB _u(16)
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#define RESETS_WDSEL_SPI0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_RTC
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#define RESETS_WDSEL_RTC_RESET _u(0x0)
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#define RESETS_WDSEL_RTC_BITS _u(0x00008000)
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#define RESETS_WDSEL_RTC_MSB _u(15)
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#define RESETS_WDSEL_RTC_LSB _u(15)
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#define RESETS_WDSEL_RTC_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_PWM
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#define RESETS_WDSEL_PWM_RESET _u(0x0)
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#define RESETS_WDSEL_PWM_BITS _u(0x00004000)
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#define RESETS_WDSEL_PWM_MSB _u(14)
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#define RESETS_WDSEL_PWM_LSB _u(14)
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#define RESETS_WDSEL_PWM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_PLL_USB
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#define RESETS_WDSEL_PLL_USB_RESET _u(0x0)
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#define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000)
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#define RESETS_WDSEL_PLL_USB_MSB _u(13)
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#define RESETS_WDSEL_PLL_USB_LSB _u(13)
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#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_PLL_SYS
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#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0)
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#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000)
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#define RESETS_WDSEL_PLL_SYS_MSB _u(12)
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#define RESETS_WDSEL_PLL_SYS_LSB _u(12)
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#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_PIO1
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#define RESETS_WDSEL_PIO1_RESET _u(0x0)
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#define RESETS_WDSEL_PIO1_BITS _u(0x00000800)
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#define RESETS_WDSEL_PIO1_MSB _u(11)
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#define RESETS_WDSEL_PIO1_LSB _u(11)
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#define RESETS_WDSEL_PIO1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_PIO0
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#define RESETS_WDSEL_PIO0_RESET _u(0x0)
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#define RESETS_WDSEL_PIO0_BITS _u(0x00000400)
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#define RESETS_WDSEL_PIO0_MSB _u(10)
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#define RESETS_WDSEL_PIO0_LSB _u(10)
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#define RESETS_WDSEL_PIO0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_PADS_QSPI
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#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0)
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#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200)
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#define RESETS_WDSEL_PADS_QSPI_MSB _u(9)
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#define RESETS_WDSEL_PADS_QSPI_LSB _u(9)
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#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_PADS_BANK0
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#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0)
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#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100)
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#define RESETS_WDSEL_PADS_BANK0_MSB _u(8)
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#define RESETS_WDSEL_PADS_BANK0_LSB _u(8)
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#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_JTAG
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#define RESETS_WDSEL_JTAG_RESET _u(0x0)
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#define RESETS_WDSEL_JTAG_BITS _u(0x00000080)
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#define RESETS_WDSEL_JTAG_MSB _u(7)
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#define RESETS_WDSEL_JTAG_LSB _u(7)
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#define RESETS_WDSEL_JTAG_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_IO_QSPI
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#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0)
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#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040)
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#define RESETS_WDSEL_IO_QSPI_MSB _u(6)
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#define RESETS_WDSEL_IO_QSPI_LSB _u(6)
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#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_IO_BANK0
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#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0)
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#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020)
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#define RESETS_WDSEL_IO_BANK0_MSB _u(5)
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#define RESETS_WDSEL_IO_BANK0_LSB _u(5)
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#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_I2C1
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#define RESETS_WDSEL_I2C1_RESET _u(0x0)
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#define RESETS_WDSEL_I2C1_BITS _u(0x00000010)
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#define RESETS_WDSEL_I2C1_MSB _u(4)
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#define RESETS_WDSEL_I2C1_LSB _u(4)
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#define RESETS_WDSEL_I2C1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_I2C0
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#define RESETS_WDSEL_I2C0_RESET _u(0x0)
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#define RESETS_WDSEL_I2C0_BITS _u(0x00000008)
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#define RESETS_WDSEL_I2C0_MSB _u(3)
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#define RESETS_WDSEL_I2C0_LSB _u(3)
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#define RESETS_WDSEL_I2C0_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_DMA
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#define RESETS_WDSEL_DMA_RESET _u(0x0)
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#define RESETS_WDSEL_DMA_BITS _u(0x00000004)
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#define RESETS_WDSEL_DMA_MSB _u(2)
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#define RESETS_WDSEL_DMA_LSB _u(2)
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#define RESETS_WDSEL_DMA_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_BUSCTRL
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#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0)
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#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002)
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#define RESETS_WDSEL_BUSCTRL_MSB _u(1)
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#define RESETS_WDSEL_BUSCTRL_LSB _u(1)
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#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : RESETS_WDSEL_ADC
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#define RESETS_WDSEL_ADC_RESET _u(0x0)
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#define RESETS_WDSEL_ADC_BITS _u(0x00000001)
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#define RESETS_WDSEL_ADC_MSB _u(0)
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#define RESETS_WDSEL_ADC_LSB _u(0)
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#define RESETS_WDSEL_ADC_ACCESS "RW"
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// =============================================================================
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// Register : RESETS_RESET_DONE
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// Description : Reset done. If a bit is set then a reset done signal has been
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// returned by the peripheral. This indicates that the
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// peripheral's registers are ready to be accessed.
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#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
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#define RESETS_RESET_DONE_BITS _u(0x01ffffff)
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#define RESETS_RESET_DONE_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_DONE_USBCTRL
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#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0)
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#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000)
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#define RESETS_RESET_DONE_USBCTRL_MSB _u(24)
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#define RESETS_RESET_DONE_USBCTRL_LSB _u(24)
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#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_DONE_UART1
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#define RESETS_RESET_DONE_UART1_RESET _u(0x0)
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#define RESETS_RESET_DONE_UART1_BITS _u(0x00800000)
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#define RESETS_RESET_DONE_UART1_MSB _u(23)
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#define RESETS_RESET_DONE_UART1_LSB _u(23)
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#define RESETS_RESET_DONE_UART1_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_DONE_UART0
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#define RESETS_RESET_DONE_UART0_RESET _u(0x0)
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#define RESETS_RESET_DONE_UART0_BITS _u(0x00400000)
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#define RESETS_RESET_DONE_UART0_MSB _u(22)
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#define RESETS_RESET_DONE_UART0_LSB _u(22)
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#define RESETS_RESET_DONE_UART0_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_DONE_TIMER
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#define RESETS_RESET_DONE_TIMER_RESET _u(0x0)
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#define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000)
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#define RESETS_RESET_DONE_TIMER_MSB _u(21)
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#define RESETS_RESET_DONE_TIMER_LSB _u(21)
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#define RESETS_RESET_DONE_TIMER_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_DONE_TBMAN
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#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0)
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#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000)
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#define RESETS_RESET_DONE_TBMAN_MSB _u(20)
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#define RESETS_RESET_DONE_TBMAN_LSB _u(20)
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#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
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|
// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_DONE_SYSINFO
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#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0)
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#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000)
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#define RESETS_RESET_DONE_SYSINFO_MSB _u(19)
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#define RESETS_RESET_DONE_SYSINFO_LSB _u(19)
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#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
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|
// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_DONE_SYSCFG
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#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0)
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#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000)
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#define RESETS_RESET_DONE_SYSCFG_MSB _u(18)
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#define RESETS_RESET_DONE_SYSCFG_LSB _u(18)
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#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
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|
// -----------------------------------------------------------------------------
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// Field : RESETS_RESET_DONE_SPI1
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|
#define RESETS_RESET_DONE_SPI1_RESET _u(0x0)
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#define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000)
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#define RESETS_RESET_DONE_SPI1_MSB _u(17)
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|
#define RESETS_RESET_DONE_SPI1_LSB _u(17)
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#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
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|
// Field : RESETS_RESET_DONE_SPI0
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#define RESETS_RESET_DONE_SPI0_RESET _u(0x0)
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#define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000)
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#define RESETS_RESET_DONE_SPI0_MSB _u(16)
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|
#define RESETS_RESET_DONE_SPI0_LSB _u(16)
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#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_RTC
|
|
#define RESETS_RESET_DONE_RTC_RESET _u(0x0)
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|
#define RESETS_RESET_DONE_RTC_BITS _u(0x00008000)
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#define RESETS_RESET_DONE_RTC_MSB _u(15)
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|
#define RESETS_RESET_DONE_RTC_LSB _u(15)
|
|
#define RESETS_RESET_DONE_RTC_ACCESS "RO"
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|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_PWM
|
|
#define RESETS_RESET_DONE_PWM_RESET _u(0x0)
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|
#define RESETS_RESET_DONE_PWM_BITS _u(0x00004000)
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#define RESETS_RESET_DONE_PWM_MSB _u(14)
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|
#define RESETS_RESET_DONE_PWM_LSB _u(14)
|
|
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
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|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_PLL_USB
|
|
#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0)
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|
#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000)
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|
#define RESETS_RESET_DONE_PLL_USB_MSB _u(13)
|
|
#define RESETS_RESET_DONE_PLL_USB_LSB _u(13)
|
|
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_PLL_SYS
|
|
#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000)
|
|
#define RESETS_RESET_DONE_PLL_SYS_MSB _u(12)
|
|
#define RESETS_RESET_DONE_PLL_SYS_LSB _u(12)
|
|
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_PIO1
|
|
#define RESETS_RESET_DONE_PIO1_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800)
|
|
#define RESETS_RESET_DONE_PIO1_MSB _u(11)
|
|
#define RESETS_RESET_DONE_PIO1_LSB _u(11)
|
|
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_PIO0
|
|
#define RESETS_RESET_DONE_PIO0_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400)
|
|
#define RESETS_RESET_DONE_PIO0_MSB _u(10)
|
|
#define RESETS_RESET_DONE_PIO0_LSB _u(10)
|
|
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_PADS_QSPI
|
|
#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200)
|
|
#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9)
|
|
#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9)
|
|
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_PADS_BANK0
|
|
#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100)
|
|
#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8)
|
|
#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8)
|
|
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_JTAG
|
|
#define RESETS_RESET_DONE_JTAG_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080)
|
|
#define RESETS_RESET_DONE_JTAG_MSB _u(7)
|
|
#define RESETS_RESET_DONE_JTAG_LSB _u(7)
|
|
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_IO_QSPI
|
|
#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040)
|
|
#define RESETS_RESET_DONE_IO_QSPI_MSB _u(6)
|
|
#define RESETS_RESET_DONE_IO_QSPI_LSB _u(6)
|
|
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_IO_BANK0
|
|
#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020)
|
|
#define RESETS_RESET_DONE_IO_BANK0_MSB _u(5)
|
|
#define RESETS_RESET_DONE_IO_BANK0_LSB _u(5)
|
|
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_I2C1
|
|
#define RESETS_RESET_DONE_I2C1_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010)
|
|
#define RESETS_RESET_DONE_I2C1_MSB _u(4)
|
|
#define RESETS_RESET_DONE_I2C1_LSB _u(4)
|
|
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_I2C0
|
|
#define RESETS_RESET_DONE_I2C0_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008)
|
|
#define RESETS_RESET_DONE_I2C0_MSB _u(3)
|
|
#define RESETS_RESET_DONE_I2C0_LSB _u(3)
|
|
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_DMA
|
|
#define RESETS_RESET_DONE_DMA_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004)
|
|
#define RESETS_RESET_DONE_DMA_MSB _u(2)
|
|
#define RESETS_RESET_DONE_DMA_LSB _u(2)
|
|
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_BUSCTRL
|
|
#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002)
|
|
#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1)
|
|
#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1)
|
|
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : RESETS_RESET_DONE_ADC
|
|
#define RESETS_RESET_DONE_ADC_RESET _u(0x0)
|
|
#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001)
|
|
#define RESETS_RESET_DONE_ADC_MSB _u(0)
|
|
#define RESETS_RESET_DONE_ADC_LSB _u(0)
|
|
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
|
|
// =============================================================================
|
|
#endif // _HARDWARE_REGS_RESETS_H
|
|
|