mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_NVIC_H
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#define _HARDWARE_STRUCTS_NVIC_H
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/**
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* \file rp2040/nvic.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/m0plus.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
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// Interrupt Set-Enable Register
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// 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits
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io_rw_32 iser;
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uint32_t _pad0[31];
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_REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
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// Interrupt Clear-Enable Register
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// 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits
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io_rw_32 icer;
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uint32_t _pad1[31];
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_REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
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// Interrupt Set-Pending Register
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// 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits
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io_rw_32 ispr;
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uint32_t _pad2[31];
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_REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
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// Interrupt Clear-Pending Register
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// 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits
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io_rw_32 icpr;
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uint32_t _pad3[95];
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// (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
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_REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
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// Interrupt Priority Register 0
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// 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3
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// 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2
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// 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1
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// 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0
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io_rw_32 ipr[8];
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} nvic_hw_t;
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#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))
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static_assert(sizeof (nvic_hw_t) == 0x0320, "");
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#endif // _HARDWARE_STRUCTS_NVIC_H
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