mirror of
https://github.com/andreili/katapult.git
synced 2025-08-23 19:34:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
457 lines
23 KiB
C
457 lines
23 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : PADS_QSPI
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// Version : 1
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// Bus type : apb
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// =============================================================================
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#ifndef _HARDWARE_REGS_PADS_QSPI_H
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#define _HARDWARE_REGS_PADS_QSPI_H
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// =============================================================================
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// Register : PADS_QSPI_VOLTAGE_SELECT
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// Description : Voltage select. Per bank control
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// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
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// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
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#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000)
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#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001)
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#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000)
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#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0)
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#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0)
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#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
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#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
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#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
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// =============================================================================
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// Register : PADS_QSPI_GPIO_QSPI_SCLK
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// Description : Pad control register
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#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
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#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000000ff)
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#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000056)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
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// Description : Output disable. Has priority over output enable from
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// peripherals
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#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080)
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#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
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// Description : Input enable
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#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040)
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#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
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// Description : Drive strength.
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// 0x0 -> 2mA
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// 0x1 -> 4mA
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// 0x2 -> 8mA
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// 0x3 -> 12mA
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#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030)
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#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5)
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#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4)
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#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
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#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2)
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#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
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// Description : Pull up enable
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#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008)
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#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
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// Description : Pull down enable
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#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004)
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#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
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// Description : Enable schmitt trigger
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#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002)
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#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
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// Description : Slew rate control. 1 = Fast, 0 = Slow
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#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001)
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#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
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// =============================================================================
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// Register : PADS_QSPI_GPIO_QSPI_SD0
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// Description : Pad control register
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#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
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#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000000ff)
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#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000052)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
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// Description : Output disable. Has priority over output enable from
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// peripherals
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#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080)
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#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
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// Description : Input enable
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#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040)
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#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
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// Description : Drive strength.
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// 0x0 -> 2mA
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// 0x1 -> 4mA
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// 0x2 -> 8mA
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// 0x3 -> 12mA
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#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030)
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#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5)
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#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4)
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#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
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#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2)
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#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
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// Description : Pull up enable
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#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008)
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#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
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// Description : Pull down enable
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#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004)
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#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
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// Description : Enable schmitt trigger
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#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002)
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#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
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// Description : Slew rate control. 1 = Fast, 0 = Slow
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#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001)
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#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
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// =============================================================================
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// Register : PADS_QSPI_GPIO_QSPI_SD1
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// Description : Pad control register
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#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
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#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000000ff)
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#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000052)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
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// Description : Output disable. Has priority over output enable from
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// peripherals
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#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080)
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#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
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// Description : Input enable
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#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040)
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#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
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// Description : Drive strength.
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// 0x0 -> 2mA
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// 0x1 -> 4mA
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// 0x2 -> 8mA
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// 0x3 -> 12mA
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#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030)
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#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5)
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#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4)
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#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
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#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2)
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#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
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// Description : Pull up enable
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#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008)
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#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
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// Description : Pull down enable
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#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004)
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#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
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// Description : Enable schmitt trigger
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#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002)
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#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
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// Description : Slew rate control. 1 = Fast, 0 = Slow
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#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001)
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#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
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// =============================================================================
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// Register : PADS_QSPI_GPIO_QSPI_SD2
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// Description : Pad control register
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#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
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#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000000ff)
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#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x00000052)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
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// Description : Output disable. Has priority over output enable from
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// peripherals
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#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080)
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#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
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// Description : Input enable
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#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040)
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#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
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// Description : Drive strength.
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// 0x0 -> 2mA
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// 0x1 -> 4mA
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// 0x2 -> 8mA
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// 0x3 -> 12mA
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#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030)
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#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5)
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#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4)
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#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
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#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2)
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#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
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// Description : Pull up enable
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#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008)
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#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
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// Description : Pull down enable
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#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004)
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#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
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// Description : Enable schmitt trigger
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#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002)
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#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
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// Description : Slew rate control. 1 = Fast, 0 = Slow
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#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001)
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#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
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// =============================================================================
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// Register : PADS_QSPI_GPIO_QSPI_SD3
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// Description : Pad control register
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#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
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#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000000ff)
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#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x00000052)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
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// Description : Output disable. Has priority over output enable from
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// peripherals
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#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080)
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#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
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// Description : Input enable
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#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040)
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#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
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// Description : Drive strength.
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// 0x0 -> 2mA
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// 0x1 -> 4mA
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// 0x2 -> 8mA
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// 0x3 -> 12mA
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#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030)
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#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5)
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#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4)
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#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
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#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2)
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#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
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// Description : Pull up enable
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#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008)
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#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
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// Description : Pull down enable
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#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004)
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#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
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// Description : Enable schmitt trigger
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#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002)
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#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
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// Description : Slew rate control. 1 = Fast, 0 = Slow
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#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001)
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#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
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// =============================================================================
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// Register : PADS_QSPI_GPIO_QSPI_SS
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// Description : Pad control register
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#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
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#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000000ff)
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#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000005a)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SS_OD
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// Description : Output disable. Has priority over output enable from
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// peripherals
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#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080)
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#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7)
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#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SS_IE
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// Description : Input enable
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#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040)
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#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6)
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#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
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// Description : Drive strength.
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// 0x0 -> 2mA
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// 0x1 -> 4mA
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// 0x2 -> 8mA
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// 0x3 -> 12mA
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#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030)
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#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5)
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#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4)
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#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
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#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2)
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#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
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// Description : Pull up enable
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#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008)
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#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3)
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#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
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// Description : Pull down enable
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#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004)
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#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2)
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#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
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// Description : Enable schmitt trigger
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#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1)
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#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002)
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#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1)
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#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
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// Description : Slew rate control. 1 = Fast, 0 = Slow
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#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0)
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#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001)
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#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0)
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#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
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// =============================================================================
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#endif // _HARDWARE_REGS_PADS_QSPI_H
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