mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
67 lines
2.6 KiB
C
67 lines
2.6 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_MPU_H
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#define _HARDWARE_STRUCTS_MPU_H
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/**
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* \file rp2040/mpu.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/m0plus.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
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// MPU Type Register
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// 0x00ff0000 [23:16] IREGION (0x00) Instruction region
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// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
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// 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps
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io_ro_32 type;
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_REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
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// MPU Control Register
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// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a...
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// 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs
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// 0x00000001 [0] ENABLE (0) Enables the MPU
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io_rw_32 ctrl;
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_REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
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// MPU Region Number Register
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// 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and...
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io_rw_32 rnr;
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_REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
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// MPU Region Base Address Register
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// 0xffffff00 [31:8] ADDR (0x000000) Base address of the region
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// 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the...
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// 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base...
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io_rw_32 rbar;
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_REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
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// MPU Region Attribute and Size Register
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// 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field
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// 0x0000ff00 [15:8] SRD (0x00) Subregion Disable
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// 0x0000003e [5:1] SIZE (0x00) Indicates the region size
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// 0x00000001 [0] ENABLE (0) Enables the region
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io_rw_32 rasr;
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} mpu_hw_t;
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#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
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static_assert(sizeof (mpu_hw_t) == 0x0014, "");
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#endif // _HARDWARE_STRUCTS_MPU_H
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