andreil/klipper
1
0
Fork 0
mirror of https://github.com/andreili/klipper.git synced 2025-08-24 03:44:06 +02:00
Code Issues Packages Projects Releases Wiki Activity

stm32: Fix spi overflow issue on stm32h7

Browse Source 
Completely filling the spi transmit fifo could lead to a situation
where the rx fifo overflows.  Make sure not to write past the rx fifo
size.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2025-05-30 20:36:09 -04:00
parent 8e58f8fb39
commit 1f3b4cc749
1 changed files with 6 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/stm32/stm32h7_spi.c
View File

@ -124,13 +124,13 @@ spi_prepare(struct spi_config config)
; ;
} }
#define MAX_FIFO 8 // Limit tx fifo usage so rx fifo doesn't overrun
void void
spi_transfer(struct spi_config config, uint8_t receive_data, spi_transfer(struct spi_config config, uint8_t receive_data,
uint8_t len, uint8_t *data) uint8_t len, uint8_t *data)
{ {
uint8_t rdata = 0; uint8_t *wptr = data, *end = data + len;
uint8_t* wptr = data;
uint8_t* end = data + len;
SPI_TypeDef *spi = config.spi; SPI_TypeDef *spi = config.spi;
spi->CR2 = len << SPI_CR2_TSIZE_Pos; spi->CR2 = len << SPI_CR2_TSIZE_Pos;
@ -140,15 +140,13 @@ spi_transfer(struct spi_config config, uint8_t receive_data,
while (data < end) { while (data < end) {
uint32_t sr = spi->SR & (SPI_SR_TXP | SPI_SR_RXP); uint32_t sr = spi->SR & (SPI_SR_TXP | SPI_SR_RXP);
if ((sr == SPI_SR_TXP) && wptr < end) if (sr == SPI_SR_TXP && wptr < end && wptr < data + MAX_FIFO)
writeb((void*)&spi->TXDR, *wptr++); writeb((void*)&spi->TXDR, *wptr++);
if (!(sr & SPI_SR_RXP)) if (!(sr & SPI_SR_RXP))
continue; continue;
rdata = readb((void *)&spi->RXDR); uint8_t rdata = readb((void *)&spi->RXDR);
if (receive_data)
if (receive_data) {
*data = rdata; *data = rdata;
}
data++; data++;
} }