andreil/klipper
1
0
Fork 0
mirror of https://github.com/andreili/klipper.git synced 2025-08-23 19:34:06 +02:00
Code Issues Packages Projects Releases Wiki Activity

rp2040: Fix spi overflow issue

Browse Source 
Completely filling the spi transmit fifo could lead to a situation
where the rx fifo overflows.  Make sure not to write past the rx fifo
size.

Also, be sure to wait for the transmission to fully complete before
exiting spi_transfer().

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2025-05-30 15:56:12 -04:00
parent f4130aa948
commit 8e58f8fb39
1 changed files with 9 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/rp2040/spi.c
View File

@ -128,22 +128,27 @@ spi_prepare(struct spi_config config)
;
}
#define MAX_FIFO 8 // Max rx fifo size (don't tx past this size)
void
spi_transfer(struct spi_config config, uint8_t receive_data,
uint8_t len, uint8_t *data)
{
uint8_t* wptr = data;
uint8_t* end = data + len;
uint8_t *wptr = data, *end = data + len;
spi_hw_t *spi = config.spi;
while (data < end) {
uint32_t sr = spi->sr & (SPI_SSPSR_TNF_BITS | SPI_SSPSR_RNE_BITS);
if ((sr == SPI_SSPSR_TNF_BITS) && wptr < end)
if (sr == SPI_SSPSR_TNF_BITS && wptr < end && wptr < data + MAX_FIFO)
spi->dr = *wptr++;
if (!(sr & SPI_SSPSR_RNE_BITS))
continue;
uint8_t rdata = spi->dr;
if(receive_data)
if (receive_data)
*data = rdata;
data++;
}
// Wait for any remaining SCLK updates before returning
while ((spi->sr & (SPI_SSPSR_TFE_BITS|SPI_SSPSR_BSY_BITS))
!= SPI_SSPSR_TFE_BITS)
;
}