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65 lines
3.3 KiB
C
65 lines
3.3 KiB
C
/**
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* \file
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*
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* \brief Instance description for DAC
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMC21_DAC_INSTANCE_
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#define _SAMC21_DAC_INSTANCE_
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/* ========== Register definition for DAC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_DAC_CTRLA (0x42005400) /**< \brief (DAC) Control A */
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#define REG_DAC_CTRLB (0x42005401) /**< \brief (DAC) Control B */
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#define REG_DAC_EVCTRL (0x42005402) /**< \brief (DAC) Event Control */
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#define REG_DAC_INTENCLR (0x42005404) /**< \brief (DAC) Interrupt Enable Clear */
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#define REG_DAC_INTENSET (0x42005405) /**< \brief (DAC) Interrupt Enable Set */
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#define REG_DAC_INTFLAG (0x42005406) /**< \brief (DAC) Interrupt Flag Status and Clear */
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#define REG_DAC_STATUS (0x42005407) /**< \brief (DAC) Status */
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#define REG_DAC_DATA (0x42005408) /**< \brief (DAC) Data */
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#define REG_DAC_DATABUF (0x4200540C) /**< \brief (DAC) Data Buffer */
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#define REG_DAC_SYNCBUSY (0x42005410) /**< \brief (DAC) Synchronization Busy */
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#define REG_DAC_DBGCTRL (0x42005414) /**< \brief (DAC) Debug Control */
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#else
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#define REG_DAC_CTRLA (*(RwReg8 *)0x42005400UL) /**< \brief (DAC) Control A */
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#define REG_DAC_CTRLB (*(RwReg8 *)0x42005401UL) /**< \brief (DAC) Control B */
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#define REG_DAC_EVCTRL (*(RwReg8 *)0x42005402UL) /**< \brief (DAC) Event Control */
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#define REG_DAC_INTENCLR (*(RwReg8 *)0x42005404UL) /**< \brief (DAC) Interrupt Enable Clear */
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#define REG_DAC_INTENSET (*(RwReg8 *)0x42005405UL) /**< \brief (DAC) Interrupt Enable Set */
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#define REG_DAC_INTFLAG (*(RwReg8 *)0x42005406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
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#define REG_DAC_STATUS (*(RoReg8 *)0x42005407UL) /**< \brief (DAC) Status */
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#define REG_DAC_DATA (*(WoReg16*)0x42005408UL) /**< \brief (DAC) Data */
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#define REG_DAC_DATABUF (*(WoReg16*)0x4200540CUL) /**< \brief (DAC) Data Buffer */
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#define REG_DAC_SYNCBUSY (*(RoReg *)0x42005410UL) /**< \brief (DAC) Synchronization Busy */
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#define REG_DAC_DBGCTRL (*(RwReg8 *)0x42005414UL) /**< \brief (DAC) Debug Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for DAC peripheral ========== */
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#define DAC_DMAC_ID_EMPTY 45 // Index of DMA EMPTY trigger
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#define DAC_GCLK_ID 36
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#endif /* _SAMC21_DAC_INSTANCE_ */
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