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lib: Add Atmel SAM C21 headers

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Signed-off-by: Luke Vuksta <wulfstawulfsta@gmail.com>
This commit is contained in:
Wulfsta 2023-01-15 18:44:25 -05:00 committed by KevinOConnor
parent 6414e1772d
commit 06e5c577bd
107 changed files with 49462 additions and 0 deletions
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5
lib/README
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@ -21,6 +21,11 @@ Atmel.SAM4S_DFP.1.0.56.atpack zip file found at:
http://packs.download.atmel.com/
version 1.0.56 (extracted on 20181220).
The samc21 directory contains code from the
Atmel.SAMC21_DFP.1.2.176.atpack zip file found at:
http://packs.download.atmel.com/
version 1.2.176 (extracted on 20230115).
The samd21 directory contains code from the
Atmel.SAMD21_DFP.1.3.304.atpack zip file found at:
http://packs.download.atmel.com/

64
lib/samc21/samc21/include/component-version.h Normal file
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@ -0,0 +1,64 @@
/**
* \file
*
* \brief Component version header file
*
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#ifndef _COMPONENT_VERSION_H_INCLUDED
#define _COMPONENT_VERSION_H_INCLUDED
#define COMPONENT_VERSION_MAJOR 1
#define COMPONENT_VERSION_MINOR 2
//
// The COMPONENT_VERSION define is composed of the major and the minor version number.
//
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
// The rest of the COMPONENT_VERSION is the major version.
//
#define COMPONENT_VERSION 10002
//
// The build number does not refer to the component, but to the build number
// of the device pack that provides the component.
//
#define BUILD_NUMBER 176
//
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
//
#define COMPONENT_VERSION_STRING "1.2"
//
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
//
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
//
// "%Y-%m-%d %H:%M:%S"
//
//
#define COMPONENT_DATE_STRING "2018-12-18 12:46:52"
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */

652
lib/samc21/samc21/include/component/ac.h Normal file
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@ -0,0 +1,652 @@
/**
* \file
*
* \brief Component description for AC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_AC_COMPONENT_
#define _SAMC21_AC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR AC */
/* ========================================================================== */
/** \addtogroup SAMC21_AC Analog Comparators */
/*@{*/
#define AC_U2245
#define REV_AC 0x111
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */
#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */
#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */
#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos)
#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */
#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos)
#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
uint8_t START2:1; /*!< bit: 2 Comparator 2 Start Comparison */
uint8_t START3:1; /*!< bit: 3 Comparator 3 Start Comparison */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t START:4; /*!< bit: 0.. 3 Comparator x Start Comparison */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */
#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */
#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */
#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos)
#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */
#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos)
#define AC_CTRLB_START2_Pos 2 /**< \brief (AC_CTRLB) Comparator 2 Start Comparison */
#define AC_CTRLB_START2 (_U_(1) << AC_CTRLB_START2_Pos)
#define AC_CTRLB_START3_Pos 3 /**< \brief (AC_CTRLB) Comparator 3 Start Comparison */
#define AC_CTRLB_START3 (_U_(1) << AC_CTRLB_START3_Pos)
#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */
#define AC_CTRLB_START_Msk (_U_(0xF) << AC_CTRLB_START_Pos)
#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos))
#define AC_CTRLB_MASK _U_(0x0F) /**< \brief (AC_CTRLB) MASK Register */
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
uint16_t COMPEO2:1; /*!< bit: 2 Comparator 2 Event Output Enable */
uint16_t COMPEO3:1; /*!< bit: 3 Comparator 3 Event Output Enable */
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
uint16_t WINEO1:1; /*!< bit: 5 Window 1 Event Output Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */
uint16_t COMPEI2:1; /*!< bit: 10 Comparator 2 Event Input Enable */
uint16_t COMPEI3:1; /*!< bit: 11 Comparator 3 Event Input Enable */
uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */
uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */
uint16_t INVEI2:1; /*!< bit: 14 Comparator 2 Input Event Invert Enable */
uint16_t INVEI3:1; /*!< bit: 15 Comparator 3 Input Event Invert Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t COMPEO:4; /*!< bit: 0.. 3 Comparator x Event Output Enable */
uint16_t WINEO:2; /*!< bit: 4.. 5 Window x Event Output Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t COMPEI:4; /*!< bit: 8..11 Comparator x Event Input Enable */
uint16_t INVEI:4; /*!< bit: 12..15 Comparator x Input Event Invert Enable */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */
#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */
#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */
#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos)
#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */
#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos)
#define AC_EVCTRL_COMPEO2_Pos 2 /**< \brief (AC_EVCTRL) Comparator 2 Event Output Enable */
#define AC_EVCTRL_COMPEO2 (_U_(1) << AC_EVCTRL_COMPEO2_Pos)
#define AC_EVCTRL_COMPEO3_Pos 3 /**< \brief (AC_EVCTRL) Comparator 3 Event Output Enable */
#define AC_EVCTRL_COMPEO3 (_U_(1) << AC_EVCTRL_COMPEO3_Pos)
#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */
#define AC_EVCTRL_COMPEO_Msk (_U_(0xF) << AC_EVCTRL_COMPEO_Pos)
#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos))
#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */
#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos)
#define AC_EVCTRL_WINEO1_Pos 5 /**< \brief (AC_EVCTRL) Window 1 Event Output Enable */
#define AC_EVCTRL_WINEO1 (_U_(1) << AC_EVCTRL_WINEO1_Pos)
#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */
#define AC_EVCTRL_WINEO_Msk (_U_(0x3) << AC_EVCTRL_WINEO_Pos)
#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos))
#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */
#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos)
#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */
#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos)
#define AC_EVCTRL_COMPEI2_Pos 10 /**< \brief (AC_EVCTRL) Comparator 2 Event Input Enable */
#define AC_EVCTRL_COMPEI2 (_U_(1) << AC_EVCTRL_COMPEI2_Pos)
#define AC_EVCTRL_COMPEI3_Pos 11 /**< \brief (AC_EVCTRL) Comparator 3 Event Input Enable */
#define AC_EVCTRL_COMPEI3 (_U_(1) << AC_EVCTRL_COMPEI3_Pos)
#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */
#define AC_EVCTRL_COMPEI_Msk (_U_(0xF) << AC_EVCTRL_COMPEI_Pos)
#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos))
#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */
#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos)
#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */
#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos)
#define AC_EVCTRL_INVEI2_Pos 14 /**< \brief (AC_EVCTRL) Comparator 2 Input Event Invert Enable */
#define AC_EVCTRL_INVEI2 (_U_(1) << AC_EVCTRL_INVEI2_Pos)
#define AC_EVCTRL_INVEI3_Pos 15 /**< \brief (AC_EVCTRL) Comparator 3 Input Event Invert Enable */
#define AC_EVCTRL_INVEI3 (_U_(1) << AC_EVCTRL_INVEI3_Pos)
#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */
#define AC_EVCTRL_INVEI_Msk (_U_(0xF) << AC_EVCTRL_INVEI_Pos)
#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos))
#define AC_EVCTRL_MASK _U_(0xFF3F) /**< \brief (AC_EVCTRL) MASK Register */
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t COMP2:1; /*!< bit: 2 Comparator 2 Interrupt Enable */
uint8_t COMP3:1; /*!< bit: 3 Comparator 3 Interrupt Enable */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t WIN1:1; /*!< bit: 5 Window 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:4; /*!< bit: 0.. 3 Comparator x Interrupt Enable */
uint8_t WIN:2; /*!< bit: 4.. 5 Window x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */
#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */
#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */
#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos)
#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */
#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos)
#define AC_INTENCLR_COMP2_Pos 2 /**< \brief (AC_INTENCLR) Comparator 2 Interrupt Enable */
#define AC_INTENCLR_COMP2 (_U_(1) << AC_INTENCLR_COMP2_Pos)
#define AC_INTENCLR_COMP3_Pos 3 /**< \brief (AC_INTENCLR) Comparator 3 Interrupt Enable */
#define AC_INTENCLR_COMP3 (_U_(1) << AC_INTENCLR_COMP3_Pos)
#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */
#define AC_INTENCLR_COMP_Msk (_U_(0xF) << AC_INTENCLR_COMP_Pos)
#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos))
#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */
#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos)
#define AC_INTENCLR_WIN1_Pos 5 /**< \brief (AC_INTENCLR) Window 1 Interrupt Enable */
#define AC_INTENCLR_WIN1 (_U_(1) << AC_INTENCLR_WIN1_Pos)
#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */
#define AC_INTENCLR_WIN_Msk (_U_(0x3) << AC_INTENCLR_WIN_Pos)
#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos))
#define AC_INTENCLR_MASK _U_(0x3F) /**< \brief (AC_INTENCLR) MASK Register */
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t COMP2:1; /*!< bit: 2 Comparator 2 Interrupt Enable */
uint8_t COMP3:1; /*!< bit: 3 Comparator 3 Interrupt Enable */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t WIN1:1; /*!< bit: 5 Window 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:4; /*!< bit: 0.. 3 Comparator x Interrupt Enable */
uint8_t WIN:2; /*!< bit: 4.. 5 Window x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */
#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */
#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */
#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos)
#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */
#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos)
#define AC_INTENSET_COMP2_Pos 2 /**< \brief (AC_INTENSET) Comparator 2 Interrupt Enable */
#define AC_INTENSET_COMP2 (_U_(1) << AC_INTENSET_COMP2_Pos)
#define AC_INTENSET_COMP3_Pos 3 /**< \brief (AC_INTENSET) Comparator 3 Interrupt Enable */
#define AC_INTENSET_COMP3 (_U_(1) << AC_INTENSET_COMP3_Pos)
#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */
#define AC_INTENSET_COMP_Msk (_U_(0xF) << AC_INTENSET_COMP_Pos)
#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos))
#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */
#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos)
#define AC_INTENSET_WIN1_Pos 5 /**< \brief (AC_INTENSET) Window 1 Interrupt Enable */
#define AC_INTENSET_WIN1 (_U_(1) << AC_INTENSET_WIN1_Pos)
#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */
#define AC_INTENSET_WIN_Msk (_U_(0x3) << AC_INTENSET_WIN_Pos)
#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos))
#define AC_INTENSET_MASK _U_(0x3F) /**< \brief (AC_INTENSET) MASK Register */
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
__I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
__I uint8_t COMP2:1; /*!< bit: 2 Comparator 2 */
__I uint8_t COMP3:1; /*!< bit: 3 Comparator 3 */
__I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
__I uint8_t WIN1:1; /*!< bit: 5 Window 1 */
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t COMP:4; /*!< bit: 0.. 3 Comparator x */
__I uint8_t WIN:2; /*!< bit: 4.. 5 Window x */
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */
#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */
#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos)
#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */
#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos)
#define AC_INTFLAG_COMP2_Pos 2 /**< \brief (AC_INTFLAG) Comparator 2 */
#define AC_INTFLAG_COMP2 (_U_(1) << AC_INTFLAG_COMP2_Pos)
#define AC_INTFLAG_COMP3_Pos 3 /**< \brief (AC_INTFLAG) Comparator 3 */
#define AC_INTFLAG_COMP3 (_U_(1) << AC_INTFLAG_COMP3_Pos)
#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */
#define AC_INTFLAG_COMP_Msk (_U_(0xF) << AC_INTFLAG_COMP_Pos)
#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos))
#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */
#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos)
#define AC_INTFLAG_WIN1_Pos 5 /**< \brief (AC_INTFLAG) Window 1 */
#define AC_INTFLAG_WIN1 (_U_(1) << AC_INTFLAG_WIN1_Pos)
#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */
#define AC_INTFLAG_WIN_Msk (_U_(0x3) << AC_INTFLAG_WIN_Pos)
#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos))
#define AC_INTFLAG_MASK _U_(0x3F) /**< \brief (AC_INTFLAG) MASK Register */
/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t STATE2:1; /*!< bit: 2 Comparator 2 Current State */
uint8_t STATE3:1; /*!< bit: 3 Comparator 3 Current State */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t WSTATE1:2; /*!< bit: 6.. 7 Window 1 Current State */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:4; /*!< bit: 0.. 3 Comparator x Current State */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */
#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */
#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */
#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos)
#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */
#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos)
#define AC_STATUSA_STATE2_Pos 2 /**< \brief (AC_STATUSA) Comparator 2 Current State */
#define AC_STATUSA_STATE2 (_U_(1) << AC_STATUSA_STATE2_Pos)
#define AC_STATUSA_STATE3_Pos 3 /**< \brief (AC_STATUSA) Comparator 3 Current State */
#define AC_STATUSA_STATE3 (_U_(1) << AC_STATUSA_STATE3_Pos)
#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */
#define AC_STATUSA_STATE_Msk (_U_(0xF) << AC_STATUSA_STATE_Pos)
#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos))
#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */
#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos))
#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */
#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */
#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos)
#define AC_STATUSA_WSTATE1_Pos 6 /**< \brief (AC_STATUSA) Window 1 Current State */
#define AC_STATUSA_WSTATE1_Msk (_U_(0x3) << AC_STATUSA_WSTATE1_Pos)
#define AC_STATUSA_WSTATE1(value) (AC_STATUSA_WSTATE1_Msk & ((value) << AC_STATUSA_WSTATE1_Pos))
#define AC_STATUSA_WSTATE1_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */
#define AC_STATUSA_WSTATE1_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */
#define AC_STATUSA_WSTATE1_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */
#define AC_STATUSA_WSTATE1_ABOVE (AC_STATUSA_WSTATE1_ABOVE_Val << AC_STATUSA_WSTATE1_Pos)
#define AC_STATUSA_WSTATE1_INSIDE (AC_STATUSA_WSTATE1_INSIDE_Val << AC_STATUSA_WSTATE1_Pos)
#define AC_STATUSA_WSTATE1_BELOW (AC_STATUSA_WSTATE1_BELOW_Val << AC_STATUSA_WSTATE1_Pos)
#define AC_STATUSA_MASK _U_(0xFF) /**< \brief (AC_STATUSA) MASK Register */
/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
uint8_t READY2:1; /*!< bit: 2 Comparator 2 Ready */
uint8_t READY3:1; /*!< bit: 3 Comparator 3 Ready */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:4; /*!< bit: 0.. 3 Comparator x Ready */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */
#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */
#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */
#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos)
#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */
#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos)
#define AC_STATUSB_READY2_Pos 2 /**< \brief (AC_STATUSB) Comparator 2 Ready */
#define AC_STATUSB_READY2 (_U_(1) << AC_STATUSB_READY2_Pos)
#define AC_STATUSB_READY3_Pos 3 /**< \brief (AC_STATUSB) Comparator 3 Ready */
#define AC_STATUSB_READY3 (_U_(1) << AC_STATUSB_READY3_Pos)
#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */
#define AC_STATUSB_READY_Msk (_U_(0xF) << AC_STATUSB_READY_Pos)
#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos))
#define AC_STATUSB_MASK _U_(0x0F) /**< \brief (AC_STATUSB) MASK Register */
/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */
#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */
#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */
#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos)
#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */
/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t WEN1:1; /*!< bit: 4 Window 1 Mode Enable */
uint8_t WINTSEL1:2; /*!< bit: 5.. 6 Window 1 Interrupt Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */
#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */
#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */
#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos)
#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */
#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos))
#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos)
#define AC_WINCTRL_WEN1_Pos 4 /**< \brief (AC_WINCTRL) Window 1 Mode Enable */
#define AC_WINCTRL_WEN1 (_U_(0x1) << AC_WINCTRL_WEN1_Pos)
#define AC_WINCTRL_WINTSEL1_Pos 5 /**< \brief (AC_WINCTRL) Window 1 Interrupt Selection */
#define AC_WINCTRL_WINTSEL1_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL1_Pos)
#define AC_WINCTRL_WINTSEL1(value) (AC_WINCTRL_WINTSEL1_Msk & ((value) << AC_WINCTRL_WINTSEL1_Pos))
#define AC_WINCTRL_WINTSEL1_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */
#define AC_WINCTRL_WINTSEL1_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */
#define AC_WINCTRL_WINTSEL1_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */
#define AC_WINCTRL_WINTSEL1_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */
#define AC_WINCTRL_WINTSEL1_ABOVE (AC_WINCTRL_WINTSEL1_ABOVE_Val << AC_WINCTRL_WINTSEL1_Pos)
#define AC_WINCTRL_WINTSEL1_INSIDE (AC_WINCTRL_WINTSEL1_INSIDE_Val << AC_WINCTRL_WINTSEL1_Pos)
#define AC_WINCTRL_WINTSEL1_BELOW (AC_WINCTRL_WINTSEL1_BELOW_Val << AC_WINCTRL_WINTSEL1_Pos)
#define AC_WINCTRL_WINTSEL1_OUTSIDE (AC_WINCTRL_WINTSEL1_OUTSIDE_Val << AC_WINCTRL_WINTSEL1_Pos)
#define AC_WINCTRL_MASK _U_(0x77) /**< \brief (AC_WINCTRL) MASK Register */
/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */
#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */
#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */
#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos)
#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos))
#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */
uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */
uint32_t :1; /*!< bit: 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
uint32_t :1; /*!< bit: 27 Reserved */
uint32_t OUT:2; /*!< bit: 28..29 Output */
uint32_t :2; /*!< bit: 30..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */
#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */
#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */
#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos)
#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */
#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos)
#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */
#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos))
#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */
#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */
#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */
#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */
#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos)
#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */
#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos)
#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */
#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos))
#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */
#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */
#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */
#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */
#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos)
#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */
#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos))
#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */
#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */
#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */
#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */
#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */
#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos)
#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */
#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos)
#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */
#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos)
#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos))
#define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */
#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */
#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos)
#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos)
#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */
#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos)
#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */
#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos))
#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */
#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */
#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */
#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos)
#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */
#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos))
#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */
#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos)
#define AC_COMPCTRL_MASK _U_(0x370BF75E) /**< \brief (AC_COMPCTRL) MASK Register */
/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */
uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */
uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */
uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */
uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */
uint32_t COMPCTRL2:1; /*!< bit: 5 COMPCTRL 2 Synchronization Busy */
uint32_t COMPCTRL3:1; /*!< bit: 6 COMPCTRL 3 Synchronization Busy */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :3; /*!< bit: 0.. 2 Reserved */
uint32_t COMPCTRL:4; /*!< bit: 3.. 6 COMPCTRL x Synchronization Busy */
uint32_t :25; /*!< bit: 7..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} AC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */
#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */
#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */
#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos)
#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */
#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos)
#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */
#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos)
#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */
#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos)
#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */
#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos)
#define AC_SYNCBUSY_COMPCTRL2_Pos 5 /**< \brief (AC_SYNCBUSY) COMPCTRL 2 Synchronization Busy */
#define AC_SYNCBUSY_COMPCTRL2 (_U_(1) << AC_SYNCBUSY_COMPCTRL2_Pos)
#define AC_SYNCBUSY_COMPCTRL3_Pos 6 /**< \brief (AC_SYNCBUSY) COMPCTRL 3 Synchronization Busy */
#define AC_SYNCBUSY_COMPCTRL3 (_U_(1) << AC_SYNCBUSY_COMPCTRL3_Pos)
#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */
#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0xF) << AC_SYNCBUSY_COMPCTRL_Pos)
#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos))
#define AC_SYNCBUSY_MASK _U_(0x0000007F) /**< \brief (AC_SYNCBUSY) MASK Register */
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */
__IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */
RoReg8 Reserved1[0x1];
__IO AC_SCALER_Type SCALER[4]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */
__IO AC_COMPCTRL_Type COMPCTRL[4]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
__I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_AC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for ADC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_ADC_COMPONENT_
#define _SAMC21_ADC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR ADC */
/* ========================================================================== */
/** \addtogroup SAMC21_ADC Analog Digital Converter */
/*@{*/
#define ADC_U2247
#define REV_ADC 0x220
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :3; /*!< bit: 2.. 4 Reserved */
uint8_t SLAVEEN:1; /*!< bit: 5 Slave Enable */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run During Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */
#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */
#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */
#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos)
#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */
#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos)
#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */
#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos)
#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run During Standby */
#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos)
#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */
#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos)
#define ADC_CTRLA_MASK _U_(0xE3) /**< \brief (ADC_CTRLA) MASK Register */
/* -------- ADC_CTRLB : (ADC Offset: 0x01) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PRESCALER:3; /*!< bit: 0.. 2 Prescaler Configuration */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CTRLB_OFFSET 0x01 /**< \brief (ADC_CTRLB offset) Control B */
#define ADC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLB reset_value) Control B */
#define ADC_CTRLB_PRESCALER_Pos 0 /**< \brief (ADC_CTRLB) Prescaler Configuration */
#define ADC_CTRLB_PRESCALER_Msk (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))
#define ADC_CTRLB_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 2 */
#define ADC_CTRLB_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */
#define ADC_CTRLB_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */
#define ADC_CTRLB_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */
#define ADC_CTRLB_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */
#define ADC_CTRLB_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */
#define ADC_CTRLB_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */
#define ADC_CTRLB_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */
#define ADC_CTRLB_PRESCALER_DIV2 (ADC_CTRLB_PRESCALER_DIV2_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos)
#define ADC_CTRLB_MASK _U_(0x07) /**< \brief (ADC_CTRLB) MASK Register */
/* -------- ADC_REFCTRL : (ADC Offset: 0x02) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_REFCTRL_OFFSET 0x02 /**< \brief (ADC_REFCTRL offset) Reference Control */
#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */
#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */
#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))
#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */
#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x1) /**< \brief (ADC_REFCTRL) 1/1.6 VDDANA */
#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */
#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x3) /**< \brief (ADC_REFCTRL) External Reference */
#define ADC_REFCTRL_REFSEL_DAC_Val _U_(0x4) /**< \brief (ADC_REFCTRL) DAC */
#define ADC_REFCTRL_REFSEL_INTVCC2_Val _U_(0x5) /**< \brief (ADC_REFCTRL) VDDANA */
#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_DAC (ADC_REFCTRL_REFSEL_DAC_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFSEL_INTVCC2 (ADC_REFCTRL_REFSEL_INTVCC2_Val << ADC_REFCTRL_REFSEL_Pos)
#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */
#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos)
#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */
/* -------- ADC_EVCTRL : (ADC Offset: 0x03) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */
uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */
uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */
uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_EVCTRL_OFFSET 0x03 /**< \brief (ADC_EVCTRL offset) Event Control */
#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */
#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */
#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos)
#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */
#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos)
#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */
#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos)
#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Satrt Event Invert Enable */
#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos)
#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */
#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos)
#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */
#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos)
#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */
/* -------- ADC_INTENCLR : (ADC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INTENCLR_OFFSET 0x04 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */
#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */
#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */
#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos)
#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */
#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos)
#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */
#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos)
#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */
/* -------- ADC_INTENSET : (ADC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INTENSET_OFFSET 0x05 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */
#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */
#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */
#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos)
#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */
#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos)
#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */
#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos)
#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */
/* -------- ADC_INTFLAG : (ADC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INTFLAG_OFFSET 0x06 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */
#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */
#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos)
#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */
#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos)
#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */
#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos)
#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */
/* -------- ADC_SEQSTATUS : (ADC Offset: 0x07) (R/ 8) Sequence Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SEQSTATE:5; /*!< bit: 0.. 4 Sequence State */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SEQSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SEQSTATUS_OFFSET 0x07 /**< \brief (ADC_SEQSTATUS offset) Sequence Status */
#define ADC_SEQSTATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_SEQSTATUS reset_value) Sequence Status */
#define ADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (ADC_SEQSTATUS) Sequence State */
#define ADC_SEQSTATUS_SEQSTATE_Msk (_U_(0x1F) << ADC_SEQSTATUS_SEQSTATE_Pos)
#define ADC_SEQSTATUS_SEQSTATE(value) (ADC_SEQSTATUS_SEQSTATE_Msk & ((value) << ADC_SEQSTATUS_SEQSTATE_Pos))
#define ADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (ADC_SEQSTATUS) Sequence Busy */
#define ADC_SEQSTATUS_SEQBUSY (_U_(0x1) << ADC_SEQSTATUS_SEQBUSY_Pos)
#define ADC_SEQSTATUS_MASK _U_(0x9F) /**< \brief (ADC_SEQSTATUS) MASK Register */
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x08) (R/W 16) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_INPUTCTRL_OFFSET 0x08 /**< \brief (ADC_INPUTCTRL offset) Input Control */
#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */
#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */
#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))
#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */
#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */
#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */
#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) DAC Output */
#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos)
#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */
#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))
#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */
#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos)
#define ADC_INPUTCTRL_MASK _U_(0x1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */
/* -------- ADC_CTRLC : (ADC Offset: 0x0A) (R/W 16) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enable */
uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
uint16_t :1; /*!< bit: 6 Reserved */
uint16_t R2R:1; /*!< bit: 7 Rail-to-Rail mode enable */
uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */
uint16_t :1; /*!< bit: 11 Reserved */
uint16_t DUALSEL:2; /*!< bit: 12..13 Dual Mode Trigger Selection */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CTRLC_OFFSET 0x0A /**< \brief (ADC_CTRLC offset) Control C */
#define ADC_CTRLC_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLC reset_value) Control C */
#define ADC_CTRLC_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLC) Differential Mode */
#define ADC_CTRLC_DIFFMODE (_U_(0x1) << ADC_CTRLC_DIFFMODE_Pos)
#define ADC_CTRLC_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLC) Left-Adjusted Result */
#define ADC_CTRLC_LEFTADJ (_U_(0x1) << ADC_CTRLC_LEFTADJ_Pos)
#define ADC_CTRLC_FREERUN_Pos 2 /**< \brief (ADC_CTRLC) Free Running Mode */
#define ADC_CTRLC_FREERUN (_U_(0x1) << ADC_CTRLC_FREERUN_Pos)
#define ADC_CTRLC_CORREN_Pos 3 /**< \brief (ADC_CTRLC) Digital Correction Logic Enable */
#define ADC_CTRLC_CORREN (_U_(0x1) << ADC_CTRLC_CORREN_Pos)
#define ADC_CTRLC_RESSEL_Pos 4 /**< \brief (ADC_CTRLC) Conversion Result Resolution */
#define ADC_CTRLC_RESSEL_Msk (_U_(0x3) << ADC_CTRLC_RESSEL_Pos)
#define ADC_CTRLC_RESSEL(value) (ADC_CTRLC_RESSEL_Msk & ((value) << ADC_CTRLC_RESSEL_Pos))
#define ADC_CTRLC_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLC) 12-bit result */
#define ADC_CTRLC_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLC) For averaging mode output */
#define ADC_CTRLC_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLC) 10-bit result */
#define ADC_CTRLC_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLC) 8-bit result */
#define ADC_CTRLC_RESSEL_12BIT (ADC_CTRLC_RESSEL_12BIT_Val << ADC_CTRLC_RESSEL_Pos)
#define ADC_CTRLC_RESSEL_16BIT (ADC_CTRLC_RESSEL_16BIT_Val << ADC_CTRLC_RESSEL_Pos)
#define ADC_CTRLC_RESSEL_10BIT (ADC_CTRLC_RESSEL_10BIT_Val << ADC_CTRLC_RESSEL_Pos)
#define ADC_CTRLC_RESSEL_8BIT (ADC_CTRLC_RESSEL_8BIT_Val << ADC_CTRLC_RESSEL_Pos)
#define ADC_CTRLC_R2R_Pos 7 /**< \brief (ADC_CTRLC) Rail-to-Rail mode enable */
#define ADC_CTRLC_R2R (_U_(0x1) << ADC_CTRLC_R2R_Pos)
#define ADC_CTRLC_WINMODE_Pos 8 /**< \brief (ADC_CTRLC) Window Monitor Mode */
#define ADC_CTRLC_WINMODE_Msk (_U_(0x7) << ADC_CTRLC_WINMODE_Pos)
#define ADC_CTRLC_WINMODE(value) (ADC_CTRLC_WINMODE_Msk & ((value) << ADC_CTRLC_WINMODE_Pos))
#define ADC_CTRLC_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLC) No window mode (default) */
#define ADC_CTRLC_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLC) RESULT > WINLT */
#define ADC_CTRLC_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLC) RESULT < WINUT */
#define ADC_CTRLC_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLC) WINLT < RESULT < WINUT */
#define ADC_CTRLC_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLC) !(WINLT < RESULT < WINUT) */
#define ADC_CTRLC_WINMODE_DISABLE (ADC_CTRLC_WINMODE_DISABLE_Val << ADC_CTRLC_WINMODE_Pos)
#define ADC_CTRLC_WINMODE_MODE1 (ADC_CTRLC_WINMODE_MODE1_Val << ADC_CTRLC_WINMODE_Pos)
#define ADC_CTRLC_WINMODE_MODE2 (ADC_CTRLC_WINMODE_MODE2_Val << ADC_CTRLC_WINMODE_Pos)
#define ADC_CTRLC_WINMODE_MODE3 (ADC_CTRLC_WINMODE_MODE3_Val << ADC_CTRLC_WINMODE_Pos)
#define ADC_CTRLC_WINMODE_MODE4 (ADC_CTRLC_WINMODE_MODE4_Val << ADC_CTRLC_WINMODE_Pos)
#define ADC_CTRLC_DUALSEL_Pos 12 /**< \brief (ADC_CTRLC) Dual Mode Trigger Selection */
#define ADC_CTRLC_DUALSEL_Msk (_U_(0x3) << ADC_CTRLC_DUALSEL_Pos)
#define ADC_CTRLC_DUALSEL(value) (ADC_CTRLC_DUALSEL_Msk & ((value) << ADC_CTRLC_DUALSEL_Pos))
#define ADC_CTRLC_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLC) Start event or software trigger will start a conversion on both ADCs */
#define ADC_CTRLC_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLC) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */
#define ADC_CTRLC_DUALSEL_BOTH (ADC_CTRLC_DUALSEL_BOTH_Val << ADC_CTRLC_DUALSEL_Pos)
#define ADC_CTRLC_DUALSEL_INTERLEAVE (ADC_CTRLC_DUALSEL_INTERLEAVE_Val << ADC_CTRLC_DUALSEL_Pos)
#define ADC_CTRLC_MASK _U_(0x37BF) /**< \brief (ADC_CTRLC) MASK Register */
/* -------- ADC_AVGCTRL : (ADC Offset: 0x0C) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_AVGCTRL_OFFSET 0x0C /**< \brief (ADC_AVGCTRL offset) Average Control */
#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */
#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */
#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))
#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */
#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */
#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */
#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */
#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */
#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */
#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */
#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */
#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */
#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */
#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */
#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos)
#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */
#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos)
#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))
#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0D) (R/W 8) Sample Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
uint8_t :1; /*!< bit: 6 Reserved */
uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SAMPCTRL_OFFSET 0x0D /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */
#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */
#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */
#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos)
#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))
#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */
#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos)
#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */
/* -------- ADC_WINLT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_WINLT_OFFSET 0x0E /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */
#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */
#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */
#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos)
#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))
#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */
/* -------- ADC_WINUT : (ADC Offset: 0x10) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_WINUT_OFFSET 0x10 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */
#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */
#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */
#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos)
#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))
#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */
/* -------- ADC_GAINCORR : (ADC Offset: 0x12) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_GAINCORR_OFFSET 0x12 /**< \brief (ADC_GAINCORR offset) Gain Correction */
#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */
#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */
#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos)
#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))
#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x14) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_OFFSETCORR_OFFSET 0x14 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */
#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */
#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */
#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos)
#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))
#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */
/* -------- ADC_SWTRIG : (ADC Offset: 0x18) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSH:1; /*!< bit: 0 ADC Flush */
uint8_t START:1; /*!< bit: 1 Start ADC Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SWTRIG_OFFSET 0x18 /**< \brief (ADC_SWTRIG offset) Software Trigger */
#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */
#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Flush */
#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos)
#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */
#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos)
#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */
/* -------- ADC_DBGCTRL : (ADC Offset: 0x1C) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_DBGCTRL_OFFSET 0x1C /**< \brief (ADC_DBGCTRL offset) Debug Control */
#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */
#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */
#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos)
#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */
/* -------- ADC_SYNCBUSY : (ADC Offset: 0x20) (R/ 16) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */
uint16_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
uint16_t INPUTCTRL:1; /*!< bit: 2 INPUTCTRL Synchronization Busy */
uint16_t CTRLC:1; /*!< bit: 3 CTRLC Synchronization Busy */
uint16_t AVGCTRL:1; /*!< bit: 4 AVGCTRL Synchronization Busy */
uint16_t SAMPCTRL:1; /*!< bit: 5 SAMPCTRL Synchronization Busy */
uint16_t WINLT:1; /*!< bit: 6 WINLT Synchronization Busy */
uint16_t WINUT:1; /*!< bit: 7 WINUT Synchronization Busy */
uint16_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */
uint16_t OFFSETCORR:1; /*!< bit: 9 OFFSETCTRL Synchronization Busy */
uint16_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SYNCBUSY_OFFSET 0x20 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */
#define ADC_SYNCBUSY_RESETVALUE _U_(0x0000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */
#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */
#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos)
#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */
#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos)
#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) INPUTCTRL Synchronization Busy */
#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos)
#define ADC_SYNCBUSY_CTRLC_Pos 3 /**< \brief (ADC_SYNCBUSY) CTRLC Synchronization Busy */
#define ADC_SYNCBUSY_CTRLC (_U_(0x1) << ADC_SYNCBUSY_CTRLC_Pos)
#define ADC_SYNCBUSY_AVGCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) AVGCTRL Synchronization Busy */
#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos)
#define ADC_SYNCBUSY_SAMPCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) SAMPCTRL Synchronization Busy */
#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos)
#define ADC_SYNCBUSY_WINLT_Pos 6 /**< \brief (ADC_SYNCBUSY) WINLT Synchronization Busy */
#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos)
#define ADC_SYNCBUSY_WINUT_Pos 7 /**< \brief (ADC_SYNCBUSY) WINUT Synchronization Busy */
#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos)
#define ADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (ADC_SYNCBUSY) GAINCORR Synchronization Busy */
#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos)
#define ADC_SYNCBUSY_OFFSETCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */
#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos)
#define ADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (ADC_SYNCBUSY) SWTRG Synchronization Busy */
#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos)
#define ADC_SYNCBUSY_MASK _U_(0x07FF) /**< \brief (ADC_SYNCBUSY) MASK Register */
/* -------- ADC_RESULT : (ADC Offset: 0x24) (R/ 16) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Result Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_RESULT_OFFSET 0x24 /**< \brief (ADC_RESULT offset) Result */
#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result */
#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Value */
#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos)
#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))
#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */
/* -------- ADC_SEQCTRL : (ADC Offset: 0x28) (R/W 32) Sequence Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SEQEN:32; /*!< bit: 0..31 Enable Positive Input in the Sequence */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ADC_SEQCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_SEQCTRL_OFFSET 0x28 /**< \brief (ADC_SEQCTRL offset) Sequence Control */
#define ADC_SEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SEQCTRL reset_value) Sequence Control */
#define ADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (ADC_SEQCTRL) Enable Positive Input in the Sequence */
#define ADC_SEQCTRL_SEQEN_Msk (_U_(0xFFFFFFFF) << ADC_SEQCTRL_SEQEN_Pos)
#define ADC_SEQCTRL_SEQEN(value) (ADC_SEQCTRL_SEQEN_Msk & ((value) << ADC_SEQCTRL_SEQEN_Pos))
#define ADC_SEQCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_SEQCTRL) MASK Register */
/* -------- ADC_CALIB : (ADC Offset: 0x2C) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */
uint16_t :5; /*!< bit: 3.. 7 Reserved */
uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define ADC_CALIB_OFFSET 0x2C /**< \brief (ADC_CALIB offset) Calibration */
#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */
#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */
#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos)
#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos))
#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */
#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos)
#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos))
#define ADC_CALIB_MASK _U_(0x0707) /**< \brief (ADC_CALIB) MASK Register */
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x02 (R/W 8) Reference Control */
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control */
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
__I ADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x07 (R/ 8) Sequence Status */
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x08 (R/W 16) Input Control */
__IO ADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 16) Control C */
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0C (R/W 8) Average Control */
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0D (R/W 8) Sample Time Control */
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Lower Threshold */
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 16) Window Monitor Upper Threshold */
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x12 (R/W 16) Gain Correction */
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 16) Offset Correction */
RoReg8 Reserved1[0x2];
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x18 (R/W 8) Software Trigger */
RoReg8 Reserved2[0x3];
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1C (R/W 8) Debug Control */
RoReg8 Reserved3[0x3];
__I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 16) Synchronization Busy */
RoReg8 Reserved4[0x2];
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 16) Result */
RoReg8 Reserved5[0x2];
__IO ADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 32) Sequence Control */
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x2C (R/W 16) Calibration */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_ADC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for CCL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_CCL_COMPONENT_
#define _SAMC21_CCL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR CCL */
/* ========================================================================== */
/** \addtogroup SAMC21_CCL Configurable Custom Logic */
/*@{*/
#define CCL_U2225
#define REV_CCL 0x101
/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} CCL_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */
#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */
#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */
#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos)
#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */
#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */
#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */
/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} CCL_SEQCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */
#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */
#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */
#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */
#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */
#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos)
#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */
/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */
uint32_t :2; /*!< bit: 2.. 3 Reserved */
uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */
uint32_t :1; /*!< bit: 6 Reserved */
uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */
uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */
uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */
uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */
uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */
uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */
uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CCL_LUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */
#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */
#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */
#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */
#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */
#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */
#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */
#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event in put source */
#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM inout source */
#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */
#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */
#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */
#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */
#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */
#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */
#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
/** \brief CCL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
RoReg8 Reserved1[0x3];
__IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */
RoReg8 Reserved2[0x2];
__IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
} Ccl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_CCL_COMPONENT_ */

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/**
* \file
*
* \brief Component description for DAC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DAC_COMPONENT_
#define _SAMC21_DAC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR DAC */
/* ========================================================================== */
/** \addtogroup SAMC21_DAC Digital Analog Converter */
/*@{*/
#define DAC_U2214
#define REV_DAC 0x201
/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */
#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */
#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
#define DAC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (DAC_CTRLA) Run in Standby */
#define DAC_CTRLA_RUNSTDBY (_U_(0x1) << DAC_CTRLA_RUNSTDBY_Pos)
#define DAC_CTRLA_MASK _U_(0x43) /**< \brief (DAC_CTRLA) MASK Register */
/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
uint8_t :1; /*!< bit: 4 Reserved */
uint8_t DITHER:1; /*!< bit: 5 Dither Enable */
uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */
#define DAC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */
#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
#define DAC_CTRLB_EOEN (_U_(0x1) << DAC_CTRLB_EOEN_Pos)
#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
#define DAC_CTRLB_IOEN (_U_(0x1) << DAC_CTRLB_IOEN_Pos)
#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
#define DAC_CTRLB_LEFTADJ (_U_(0x1) << DAC_CTRLB_LEFTADJ_Pos)
#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
#define DAC_CTRLB_VPD (_U_(0x1) << DAC_CTRLB_VPD_Pos)
#define DAC_CTRLB_DITHER_Pos 5 /**< \brief (DAC_CTRLB) Dither Enable */
#define DAC_CTRLB_DITHER (_U_(0x1) << DAC_CTRLB_DITHER_Pos)
#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
#define DAC_CTRLB_REFSEL_INT1V_Val _U_(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */
#define DAC_CTRLB_REFSEL_AVCC_Val _U_(0x1) /**< \brief (DAC_CTRLB) AVCC */
#define DAC_CTRLB_REFSEL_VREFP_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference */
#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
#define DAC_CTRLB_MASK _U_(0xEF) /**< \brief (DAC_CTRLB) MASK Register */
/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
uint8_t INVEI:1; /*!< bit: 2 Invert Event Input */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */
#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */
#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
#define DAC_EVCTRL_STARTEI (_U_(0x1) << DAC_EVCTRL_STARTEI_Pos)
#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
#define DAC_EVCTRL_EMPTYEO (_U_(0x1) << DAC_EVCTRL_EMPTYEO_Pos)
#define DAC_EVCTRL_INVEI_Pos 2 /**< \brief (DAC_EVCTRL) Invert Event Input */
#define DAC_EVCTRL_INVEI (_U_(0x1) << DAC_EVCTRL_INVEI_Pos)
#define DAC_EVCTRL_MASK _U_(0x07) /**< \brief (DAC_EVCTRL) MASK Register */
/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
#define DAC_INTENCLR_UNDERRUN (_U_(0x1) << DAC_INTENCLR_UNDERRUN_Pos)
#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
#define DAC_INTENCLR_EMPTY (_U_(0x1) << DAC_INTENCLR_EMPTY_Pos)
#define DAC_INTENCLR_MASK _U_(0x03) /**< \brief (DAC_INTENCLR) MASK Register */
/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
#define DAC_INTENSET_UNDERRUN (_U_(0x1) << DAC_INTENSET_UNDERRUN_Pos)
#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
#define DAC_INTENSET_EMPTY (_U_(0x1) << DAC_INTENSET_EMPTY_Pos)
#define DAC_INTENSET_MASK _U_(0x03) /**< \brief (DAC_INTENSET) MASK Register */
/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
__I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
#define DAC_INTFLAG_UNDERRUN (_U_(0x1) << DAC_INTFLAG_UNDERRUN_Pos)
#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
#define DAC_INTFLAG_EMPTY (_U_(0x1) << DAC_INTFLAG_EMPTY_Pos)
#define DAC_INTFLAG_MASK _U_(0x03) /**< \brief (DAC_INTFLAG) MASK Register */
/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 Ready */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */
#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */
#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) Ready */
#define DAC_STATUS_READY (_U_(0x1) << DAC_STATUS_READY_Pos)
#define DAC_STATUS_MASK _U_(0x01) /**< \brief (DAC_STATUS) MASK Register */
/* -------- DAC_DATA : (DAC Offset: 0x08) ( /W 16) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_DATA_OFFSET 0x08 /**< \brief (DAC_DATA offset) Data */
#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) Data */
#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */
/* -------- DAC_DATABUF : (DAC Offset: 0x0C) ( /W 16) Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATABUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_DATABUF_OFFSET 0x0C /**< \brief (DAC_DATABUF offset) Data Buffer */
#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */
#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */
/* -------- DAC_SYNCBUSY : (DAC Offset: 0x10) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t DATA:1; /*!< bit: 2 Data */
uint32_t DATABUF:1; /*!< bit: 3 Data Buffer */
uint32_t :28; /*!< bit: 4..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DAC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_SYNCBUSY_OFFSET 0x10 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */
#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */
#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */
#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos)
#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) Enable */
#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos)
#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data */
#define DAC_SYNCBUSY_DATA (_U_(0x1) << DAC_SYNCBUSY_DATA_Pos)
#define DAC_SYNCBUSY_DATABUF_Pos 3 /**< \brief (DAC_SYNCBUSY) Data Buffer */
#define DAC_SYNCBUSY_DATABUF (_U_(0x1) << DAC_SYNCBUSY_DATABUF_Pos)
#define DAC_SYNCBUSY_MASK _U_(0x0000000F) /**< \brief (DAC_SYNCBUSY) MASK Register */
/* -------- DAC_DBGCTRL : (DAC Offset: 0x14) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DAC_DBGCTRL_OFFSET 0x14 /**< \brief (DAC_DBGCTRL offset) Debug Control */
#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */
#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */
#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos)
#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */
/** \brief DAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */
RoReg8 Reserved1[0x1];
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */
__O DAC_DATA_Type DATA; /**< \brief Offset: 0x08 ( /W 16) Data */
RoReg8 Reserved2[0x2];
__O DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0x0C ( /W 16) Data Buffer */
RoReg8 Reserved3[0x2];
__I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Busy */
__IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x14 (R/W 8) Debug Control */
} Dac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_DAC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for DIVAS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DIVAS_COMPONENT_
#define _SAMC21_DIVAS_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR DIVAS */
/* ========================================================================== */
/** \addtogroup SAMC21_DIVAS Divide and Square Root Accelerator */
/*@{*/
#define DIVAS_U2258
#define REV_DIVAS 0x100
/* -------- DIVAS_CTRLA : (DIVAS Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SIGNED:1; /*!< bit: 0 Signed */
uint8_t DLZ:1; /*!< bit: 1 Disable Leading Zero Optimization */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DIVAS_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DIVAS_CTRLA_OFFSET 0x00 /**< \brief (DIVAS_CTRLA offset) Control */
#define DIVAS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DIVAS_CTRLA reset_value) Control */
#define DIVAS_CTRLA_SIGNED_Pos 0 /**< \brief (DIVAS_CTRLA) Signed */
#define DIVAS_CTRLA_SIGNED (_U_(0x1) << DIVAS_CTRLA_SIGNED_Pos)
#define DIVAS_CTRLA_DLZ_Pos 1 /**< \brief (DIVAS_CTRLA) Disable Leading Zero Optimization */
#define DIVAS_CTRLA_DLZ (_U_(0x1) << DIVAS_CTRLA_DLZ_Pos)
#define DIVAS_CTRLA_MASK _U_(0x03) /**< \brief (DIVAS_CTRLA) MASK Register */
/* -------- DIVAS_STATUS : (DIVAS Offset: 0x04) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t BUSY:1; /*!< bit: 0 DIVAS Accelerator Busy */
uint8_t DBZ:1; /*!< bit: 1 Writing a one to this bit clears DBZ to zero */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DIVAS_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DIVAS_STATUS_OFFSET 0x04 /**< \brief (DIVAS_STATUS offset) Status */
#define DIVAS_STATUS_RESETVALUE _U_(0x00) /**< \brief (DIVAS_STATUS reset_value) Status */
#define DIVAS_STATUS_BUSY_Pos 0 /**< \brief (DIVAS_STATUS) DIVAS Accelerator Busy */
#define DIVAS_STATUS_BUSY (_U_(0x1) << DIVAS_STATUS_BUSY_Pos)
#define DIVAS_STATUS_DBZ_Pos 1 /**< \brief (DIVAS_STATUS) Writing a one to this bit clears DBZ to zero */
#define DIVAS_STATUS_DBZ (_U_(0x1) << DIVAS_STATUS_DBZ_Pos)
#define DIVAS_STATUS_MASK _U_(0x03) /**< \brief (DIVAS_STATUS) MASK Register */
/* -------- DIVAS_DIVIDEND : (DIVAS Offset: 0x08) (R/W 32) Dividend -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIVIDEND:32; /*!< bit: 0..31 DIVIDEND */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DIVAS_DIVIDEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DIVAS_DIVIDEND_OFFSET 0x08 /**< \brief (DIVAS_DIVIDEND offset) Dividend */
#define DIVAS_DIVIDEND_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_DIVIDEND reset_value) Dividend */
#define DIVAS_DIVIDEND_DIVIDEND_Pos 0 /**< \brief (DIVAS_DIVIDEND) DIVIDEND */
#define DIVAS_DIVIDEND_DIVIDEND_Msk (_U_(0xFFFFFFFF) << DIVAS_DIVIDEND_DIVIDEND_Pos)
#define DIVAS_DIVIDEND_DIVIDEND(value) (DIVAS_DIVIDEND_DIVIDEND_Msk & ((value) << DIVAS_DIVIDEND_DIVIDEND_Pos))
#define DIVAS_DIVIDEND_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_DIVIDEND) MASK Register */
/* -------- DIVAS_DIVISOR : (DIVAS Offset: 0x0C) (R/W 32) Divisor -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIVISOR:32; /*!< bit: 0..31 DIVISOR */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DIVAS_DIVISOR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DIVAS_DIVISOR_OFFSET 0x0C /**< \brief (DIVAS_DIVISOR offset) Divisor */
#define DIVAS_DIVISOR_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_DIVISOR reset_value) Divisor */
#define DIVAS_DIVISOR_DIVISOR_Pos 0 /**< \brief (DIVAS_DIVISOR) DIVISOR */
#define DIVAS_DIVISOR_DIVISOR_Msk (_U_(0xFFFFFFFF) << DIVAS_DIVISOR_DIVISOR_Pos)
#define DIVAS_DIVISOR_DIVISOR(value) (DIVAS_DIVISOR_DIVISOR_Msk & ((value) << DIVAS_DIVISOR_DIVISOR_Pos))
#define DIVAS_DIVISOR_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_DIVISOR) MASK Register */
/* -------- DIVAS_RESULT : (DIVAS Offset: 0x10) (R/ 32) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RESULT:32; /*!< bit: 0..31 RESULT */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DIVAS_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DIVAS_RESULT_OFFSET 0x10 /**< \brief (DIVAS_RESULT offset) Result */
#define DIVAS_RESULT_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_RESULT reset_value) Result */
#define DIVAS_RESULT_RESULT_Pos 0 /**< \brief (DIVAS_RESULT) RESULT */
#define DIVAS_RESULT_RESULT_Msk (_U_(0xFFFFFFFF) << DIVAS_RESULT_RESULT_Pos)
#define DIVAS_RESULT_RESULT(value) (DIVAS_RESULT_RESULT_Msk & ((value) << DIVAS_RESULT_RESULT_Pos))
#define DIVAS_RESULT_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_RESULT) MASK Register */
/* -------- DIVAS_REM : (DIVAS Offset: 0x14) (R/ 32) Remainder -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t REM:32; /*!< bit: 0..31 REM */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DIVAS_REM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DIVAS_REM_OFFSET 0x14 /**< \brief (DIVAS_REM offset) Remainder */
#define DIVAS_REM_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_REM reset_value) Remainder */
#define DIVAS_REM_REM_Pos 0 /**< \brief (DIVAS_REM) REM */
#define DIVAS_REM_REM_Msk (_U_(0xFFFFFFFF) << DIVAS_REM_REM_Pos)
#define DIVAS_REM_REM(value) (DIVAS_REM_REM_Msk & ((value) << DIVAS_REM_REM_Pos))
#define DIVAS_REM_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_REM) MASK Register */
/* -------- DIVAS_SQRNUM : (DIVAS Offset: 0x18) (R/W 32) Square Root Input -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SQRNUM:32; /*!< bit: 0..31 Square Root Input */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DIVAS_SQRNUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DIVAS_SQRNUM_OFFSET 0x18 /**< \brief (DIVAS_SQRNUM offset) Square Root Input */
#define DIVAS_SQRNUM_RESETVALUE _U_(0x00000000) /**< \brief (DIVAS_SQRNUM reset_value) Square Root Input */
#define DIVAS_SQRNUM_SQRNUM_Pos 0 /**< \brief (DIVAS_SQRNUM) Square Root Input */
#define DIVAS_SQRNUM_SQRNUM_Msk (_U_(0xFFFFFFFF) << DIVAS_SQRNUM_SQRNUM_Pos)
#define DIVAS_SQRNUM_SQRNUM(value) (DIVAS_SQRNUM_SQRNUM_Msk & ((value) << DIVAS_SQRNUM_SQRNUM_Pos))
#define DIVAS_SQRNUM_MASK _U_(0xFFFFFFFF) /**< \brief (DIVAS_SQRNUM) MASK Register */
/** \brief DIVAS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DIVAS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
RoReg8 Reserved1[0x3];
__IO DIVAS_STATUS_Type STATUS; /**< \brief Offset: 0x04 (R/W 8) Status */
RoReg8 Reserved2[0x3];
__IO DIVAS_DIVIDEND_Type DIVIDEND; /**< \brief Offset: 0x08 (R/W 32) Dividend */
__IO DIVAS_DIVISOR_Type DIVISOR; /**< \brief Offset: 0x0C (R/W 32) Divisor */
__I DIVAS_RESULT_Type RESULT; /**< \brief Offset: 0x10 (R/ 32) Result */
__I DIVAS_REM_Type REM; /**< \brief Offset: 0x14 (R/ 32) Remainder */
__IO DIVAS_SQRNUM_Type SQRNUM; /**< \brief Offset: 0x18 (R/W 32) Square Root Input */
} Divas;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_DIVAS_COMPONENT_ */

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/**
* \file
*
* \brief Component description for DSU
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DSU_COMPONENT_
#define _SAMC21_DSU_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR DSU */
/* ========================================================================== */
/** \addtogroup SAMC21_DSU Device Service Unit */
/*@{*/
#define DSU_U2209
#define REV_DSU 0x250
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */
uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */
uint8_t CE:1; /*!< bit: 4 Chip-Erase */
uint8_t :1; /*!< bit: 5 Reserved */
uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */
uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */
#define DSU_CTRL_RESETVALUE _U_(0x00) /**< \brief (DSU_CTRL reset_value) Control */
#define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */
#define DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos)
#define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Code */
#define DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos)
#define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory built-in self-test */
#define DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos)
#define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip-Erase */
#define DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos)
#define DSU_CTRL_ARR_Pos 6 /**< \brief (DSU_CTRL) Auxiliary Row Read */
#define DSU_CTRL_ARR (_U_(0x1) << DSU_CTRL_ARR_Pos)
#define DSU_CTRL_SMSA_Pos 7 /**< \brief (DSU_CTRL) Start Memory Stream Access */
#define DSU_CTRL_SMSA (_U_(0x1) << DSU_CTRL_SMSA_Pos)
#define DSU_CTRL_MASK _U_(0xDD) /**< \brief (DSU_CTRL) MASK Register */
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1; /*!< bit: 0 Done */
uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
uint8_t BERR:1; /*!< bit: 2 Bus Error */
uint8_t FAIL:1; /*!< bit: 3 Failure */
uint8_t PERR:1; /*!< bit: 4 Protection Error */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */
#define DSU_STATUSA_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSA reset_value) Status A */
#define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */
#define DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos)
#define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */
#define DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos)
#define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */
#define DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos)
#define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */
#define DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos)
#define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */
#define DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos)
#define DSU_STATUSA_MASK _U_(0x1F) /**< \brief (DSU_STATUSA) MASK Register */
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PROT:1; /*!< bit: 0 Protected */
uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */
#define DSU_STATUSB_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSB reset_value) Status B */
#define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */
#define DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos)
#define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */
#define DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos)
#define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */
#define DSU_STATUSB_DCCD0 (_U_(1) << DSU_STATUSB_DCCD0_Pos)
#define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */
#define DSU_STATUSB_DCCD1 (_U_(1) << DSU_STATUSB_DCCD1_Pos)
#define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */
#define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos)
#define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos))
#define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */
#define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos)
#define DSU_STATUSB_MASK _U_(0x1F) /**< \brief (DSU_STATUSB) MASK Register */
/* -------- DSU_STATUSC : (DSU Offset: 0x0003) (R/ 8) Status C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE:3; /*!< bit: 0.. 2 State */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_STATUSC_OFFSET 0x0003 /**< \brief (DSU_STATUSC offset) Status C */
#define DSU_STATUSC_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSC reset_value) Status C */
#define DSU_STATUSC_STATE_Pos 0 /**< \brief (DSU_STATUSC) State */
#define DSU_STATUSC_STATE_Msk (_U_(0x7) << DSU_STATUSC_STATE_Pos)
#define DSU_STATUSC_STATE(value) (DSU_STATUSC_STATE_Msk & ((value) << DSU_STATUSC_STATE_Pos))
#define DSU_STATUSC_MASK _U_(0x07) /**< \brief (DSU_STATUSC) MASK Register */
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */
uint32_t ADDR:30; /*!< bit: 2..31 Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */
#define DSU_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */
#define DSU_ADDR_AMOD_Pos 0 /**< \brief (DSU_ADDR) Access Mode */
#define DSU_ADDR_AMOD_Msk (_U_(0x3) << DSU_ADDR_AMOD_Pos)
#define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & ((value) << DSU_ADDR_AMOD_Pos))
#define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */
#define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos)
#define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos))
#define DSU_ADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ADDR) MASK Register */
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t LENGTH:30; /*!< bit: 2..31 Length */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */
#define DSU_LENGTH_RESETVALUE _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */
#define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */
#define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos)
#define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos))
#define DSU_LENGTH_MASK _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */
#define DSU_DATA_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */
#define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */
#define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos)
#define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos))
#define DSU_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */
#define DSU_DCC_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */
#define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */
#define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos)
#define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos))
#define DSU_DCC_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */
uint32_t DIE:4; /*!< bit: 12..15 Die Number */
uint32_t SERIES:6; /*!< bit: 16..21 Series */
uint32_t :1; /*!< bit: 22 Reserved */
uint32_t FAMILY:5; /*!< bit: 23..27 Family */
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */
#define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */
#define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos)
#define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos))
#define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision Number */
#define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos)
#define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos))
#define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Number */
#define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos)
#define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos))
#define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Series */
#define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos)
#define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos))
#define DSU_DID_SERIES_0_Val _U_(0x0) /**< \brief (DSU_DID) Cortex-M0+ processor, basic feature set */
#define DSU_DID_SERIES_1_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ processor, CAN */
#define DSU_DID_SERIES_0 (DSU_DID_SERIES_0_Val << DSU_DID_SERIES_Pos)
#define DSU_DID_SERIES_1 (DSU_DID_SERIES_1_Val << DSU_DID_SERIES_Pos)
#define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Family */
#define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos)
#define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos))
#define DSU_DID_FAMILY_0_Val _U_(0x0) /**< \brief (DSU_DID) General purpose microcontroller */
#define DSU_DID_FAMILY_1_Val _U_(0x1) /**< \brief (DSU_DID) PicoPower */
#define DSU_DID_FAMILY_2_Val _U_(0x2) /**< \brief (DSU_DID) 5V Industrial */
#define DSU_DID_FAMILY_0 (DSU_DID_FAMILY_0_Val << DSU_DID_FAMILY_Pos)
#define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos)
#define DSU_DID_FAMILY_2 (DSU_DID_FAMILY_2_Val << DSU_DID_FAMILY_Pos)
#define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */
#define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos))
#define DSU_DID_PROCESSOR_0_Val _U_(0x0) /**< \brief (DSU_DID) Cortex-M0 */
#define DSU_DID_PROCESSOR_1_Val _U_(0x1) /**< \brief (DSU_DID) Cortex-M0+ */
#define DSU_DID_PROCESSOR_2_Val _U_(0x2) /**< \brief (DSU_DID) Cortex-M3 */
#define DSU_DID_PROCESSOR_3_Val _U_(0x3) /**< \brief (DSU_DID) Cortex-M4 */
#define DSU_DID_PROCESSOR_0 (DSU_DID_PROCESSOR_0_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR_1 (DSU_DID_PROCESSOR_1_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR_2 (DSU_DID_PROCESSOR_2_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_PROCESSOR_3 (DSU_DID_PROCESSOR_3_Val << DSU_DID_PROCESSOR_Pos)
#define DSU_DID_MASK _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */
/* -------- DSU_DCFG : (DSU Offset: 0x00F0) (R/W 32) Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DCFG:32; /*!< bit: 0..31 Device Configuration */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_DCFG_OFFSET 0x00F0 /**< \brief (DSU_DCFG offset) Device Configuration */
#define DSU_DCFG_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCFG reset_value) Device Configuration */
#define DSU_DCFG_DCFG_Pos 0 /**< \brief (DSU_DCFG) Device Configuration */
#define DSU_DCFG_DCFG_Msk (_U_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos)
#define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & ((value) << DSU_DCFG_DCFG_Pos))
#define DSU_DCFG_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCFG) MASK Register */
/* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) (R/ 32) CoreSight ROM Table Entry 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EPRES:1; /*!< bit: 0 Entry Present */
uint32_t FMT:1; /*!< bit: 1 Format */
uint32_t :10; /*!< bit: 2..11 Reserved */
uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_ENTRY0_OFFSET 0x1000 /**< \brief (DSU_ENTRY0 offset) CoreSight ROM Table Entry 0 */
#define DSU_ENTRY0_RESETVALUE _U_(0x9F0FC002) /**< \brief (DSU_ENTRY0 reset_value) CoreSight ROM Table Entry 0 */
#define DSU_ENTRY0_EPRES_Pos 0 /**< \brief (DSU_ENTRY0) Entry Present */
#define DSU_ENTRY0_EPRES (_U_(0x1) << DSU_ENTRY0_EPRES_Pos)
#define DSU_ENTRY0_FMT_Pos 1 /**< \brief (DSU_ENTRY0) Format */
#define DSU_ENTRY0_FMT (_U_(0x1) << DSU_ENTRY0_FMT_Pos)
#define DSU_ENTRY0_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY0) Address Offset */
#define DSU_ENTRY0_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos)
#define DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & ((value) << DSU_ENTRY0_ADDOFF_Pos))
#define DSU_ENTRY0_MASK _U_(0xFFFFF003) /**< \brief (DSU_ENTRY0) MASK Register */
/* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) (R/ 32) CoreSight ROM Table Entry 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_ENTRY1_OFFSET 0x1004 /**< \brief (DSU_ENTRY1 offset) CoreSight ROM Table Entry 1 */
#define DSU_ENTRY1_RESETVALUE _U_(0x00005002) /**< \brief (DSU_ENTRY1 reset_value) CoreSight ROM Table Entry 1 */
#define DSU_ENTRY1_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_ENTRY1) MASK Register */
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) CoreSight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t END:32; /*!< bit: 0..31 End Marker */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) CoreSight ROM Table End */
#define DSU_END_RESETVALUE _U_(0x00000000) /**< \brief (DSU_END reset_value) CoreSight ROM Table End */
#define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */
#define DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos)
#define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos))
#define DSU_END_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) CoreSight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) CoreSight ROM Table Memory Type */
#define DSU_MEMTYPE_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) CoreSight ROM Table Memory Type */
#define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */
#define DSU_MEMTYPE_SMEMP (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos)
#define DSU_MEMTYPE_MASK _U_(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */
#define DSU_PID4_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */
#define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */
#define DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos)
#define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos))
#define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB count */
#define DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos)
#define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos))
#define DSU_PID4_MASK _U_(0x000000FF) /**< \brief (DSU_PID4) MASK Register */
/* -------- DSU_PID5 : (DSU Offset: 0x1FD4) (R/ 32) Peripheral Identification 5 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} DSU_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID5_OFFSET 0x1FD4 /**< \brief (DSU_PID5 offset) Peripheral Identification 5 */
#define DSU_PID5_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID5 reset_value) Peripheral Identification 5 */
#define DSU_PID5_MASK _U_(0x00000000) /**< \brief (DSU_PID5) MASK Register */
/* -------- DSU_PID6 : (DSU Offset: 0x1FD8) (R/ 32) Peripheral Identification 6 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} DSU_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID6_OFFSET 0x1FD8 /**< \brief (DSU_PID6 offset) Peripheral Identification 6 */
#define DSU_PID6_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID6 reset_value) Peripheral Identification 6 */
#define DSU_PID6_MASK _U_(0x00000000) /**< \brief (DSU_PID6) MASK Register */
/* -------- DSU_PID7 : (DSU Offset: 0x1FDC) (R/ 32) Peripheral Identification 7 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} DSU_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID7_OFFSET 0x1FDC /**< \brief (DSU_PID7 offset) Peripheral Identification 7 */
#define DSU_PID7_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID7 reset_value) Peripheral Identification 7 */
#define DSU_PID7_MASK _U_(0x00000000) /**< \brief (DSU_PID7) MASK Register */
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */
#define DSU_PID0_RESETVALUE _U_(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */
#define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */
#define DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos)
#define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos))
#define DSU_PID0_MASK _U_(0x000000FF) /**< \brief (DSU_PID0) MASK Register */
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */
#define DSU_PID1_RESETVALUE _U_(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */
#define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */
#define DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos)
#define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos))
#define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */
#define DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos)
#define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos))
#define DSU_PID1_MASK _U_(0x000000FF) /**< \brief (DSU_PID1) MASK Register */
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */
#define DSU_PID2_RESETVALUE _U_(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */
#define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */
#define DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos)
#define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos))
#define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */
#define DSU_PID2_JEPU (_U_(0x1) << DSU_PID2_JEPU_Pos)
#define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */
#define DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos)
#define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos))
#define DSU_PID2_MASK _U_(0x000000FF) /**< \brief (DSU_PID2) MASK Register */
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */
#define DSU_PID3_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */
#define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */
#define DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos)
#define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos))
#define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */
#define DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos)
#define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos))
#define DSU_PID3_MASK _U_(0x000000FF) /**< \brief (DSU_PID3) MASK Register */
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */
#define DSU_CID0_RESETVALUE _U_(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */
#define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */
#define DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos)
#define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos))
#define DSU_CID0_MASK _U_(0x000000FF) /**< \brief (DSU_CID0) MASK Register */
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */
#define DSU_CID1_RESETVALUE _U_(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */
#define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */
#define DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos)
#define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos))
#define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */
#define DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos)
#define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos))
#define DSU_CID1_MASK _U_(0x000000FF) /**< \brief (DSU_CID1) MASK Register */
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */
#define DSU_CID2_RESETVALUE _U_(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */
#define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */
#define DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos)
#define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos))
#define DSU_CID2_MASK _U_(0x000000FF) /**< \brief (DSU_CID2) MASK Register */
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */
#define DSU_CID3_RESETVALUE _U_(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */
#define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */
#define DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos)
#define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos))
#define DSU_CID3_MASK _U_(0x000000FF) /**< \brief (DSU_CID3) MASK Register */
/** \brief DSU hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
__IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
__I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
__I DSU_STATUSC_Type STATUSC; /**< \brief Offset: 0x0003 (R/ 8) Status C */
__IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
__IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
RoReg8 Reserved1[0xD4];
__IO DSU_DCFG_Type DCFG[2]; /**< \brief Offset: 0x00F0 (R/W 32) Device Configuration */
RoReg8 Reserved2[0xF08];
__I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */
__I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End */
RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
__I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */
__I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */
__I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
__I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
__I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
__I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
__I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
__I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_DSU_COMPONENT_ */

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lib/samc21/samc21/include/component/eic.h Normal file
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/**
* \file
*
* \brief Component description for EIC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_EIC_COMPONENT_
#define _SAMC21_EIC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR EIC */
/* ========================================================================== */
/** \addtogroup SAMC21_EIC External Interrupt Controller */
/*@{*/
#define EIC_U2254
#define REV_EIC 0x204
/* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_CTRLA_OFFSET 0x00 /**< \brief (EIC_CTRLA offset) Control */
#define EIC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EIC_CTRLA reset_value) Control */
#define EIC_CTRLA_SWRST_Pos 0 /**< \brief (EIC_CTRLA) Software Reset */
#define EIC_CTRLA_SWRST (_U_(0x1) << EIC_CTRLA_SWRST_Pos)
#define EIC_CTRLA_ENABLE_Pos 1 /**< \brief (EIC_CTRLA) Enable */
#define EIC_CTRLA_ENABLE (_U_(0x1) << EIC_CTRLA_ENABLE_Pos)
#define EIC_CTRLA_CKSEL_Pos 4 /**< \brief (EIC_CTRLA) Clock Selection */
#define EIC_CTRLA_CKSEL (_U_(0x1) << EIC_CTRLA_CKSEL_Pos)
#define EIC_CTRLA_MASK _U_(0x13) /**< \brief (EIC_CTRLA) MASK Register */
/* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) NMI Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMISENSE:3; /*!< bit: 0.. 2 NMI Input Sense Configuration */
uint8_t NMIFILTEN:1; /*!< bit: 3 NMI Filter Enable */
uint8_t NMIASYNCH:1; /*!< bit: 4 NMI Asynchronous edge Detection Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_NMICTRL_OFFSET 0x01 /**< \brief (EIC_NMICTRL offset) NMI Control */
#define EIC_NMICTRL_RESETVALUE _U_(0x00) /**< \brief (EIC_NMICTRL reset_value) NMI Control */
#define EIC_NMICTRL_NMISENSE_Pos 0 /**< \brief (EIC_NMICTRL) NMI Input Sense Configuration */
#define EIC_NMICTRL_NMISENSE_Msk (_U_(0x7) << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE(value) (EIC_NMICTRL_NMISENSE_Msk & ((value) << EIC_NMICTRL_NMISENSE_Pos))
#define EIC_NMICTRL_NMISENSE_NONE_Val _U_(0x0) /**< \brief (EIC_NMICTRL) No detection */
#define EIC_NMICTRL_NMISENSE_RISE_Val _U_(0x1) /**< \brief (EIC_NMICTRL) Rising edge detection */
#define EIC_NMICTRL_NMISENSE_FALL_Val _U_(0x2) /**< \brief (EIC_NMICTRL) Falling edge detection */
#define EIC_NMICTRL_NMISENSE_BOTH_Val _U_(0x3) /**< \brief (EIC_NMICTRL) Both edges detection */
#define EIC_NMICTRL_NMISENSE_HIGH_Val _U_(0x4) /**< \brief (EIC_NMICTRL) High level detection */
#define EIC_NMICTRL_NMISENSE_LOW_Val _U_(0x5) /**< \brief (EIC_NMICTRL) Low level detection */
#define EIC_NMICTRL_NMISENSE_NONE (EIC_NMICTRL_NMISENSE_NONE_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_RISE (EIC_NMICTRL_NMISENSE_RISE_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_FALL (EIC_NMICTRL_NMISENSE_FALL_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_BOTH (EIC_NMICTRL_NMISENSE_BOTH_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_HIGH (EIC_NMICTRL_NMISENSE_HIGH_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMISENSE_LOW (EIC_NMICTRL_NMISENSE_LOW_Val << EIC_NMICTRL_NMISENSE_Pos)
#define EIC_NMICTRL_NMIFILTEN_Pos 3 /**< \brief (EIC_NMICTRL) NMI Filter Enable */
#define EIC_NMICTRL_NMIFILTEN (_U_(0x1) << EIC_NMICTRL_NMIFILTEN_Pos)
#define EIC_NMICTRL_NMIASYNCH_Pos 4 /**< \brief (EIC_NMICTRL) NMI Asynchronous edge Detection Enable */
#define EIC_NMICTRL_NMIASYNCH (_U_(0x1) << EIC_NMICTRL_NMIASYNCH_Pos)
#define EIC_NMICTRL_MASK _U_(0x1F) /**< \brief (EIC_NMICTRL) MASK Register */
/* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) NMI Interrupt Flag -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t NMI:1; /*!< bit: 0 NMI Interrupt Flag */
uint16_t :15; /*!< bit: 1..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_NMIFLAG_OFFSET 0x02 /**< \brief (EIC_NMIFLAG offset) NMI Interrupt Flag */
#define EIC_NMIFLAG_RESETVALUE _U_(0x0000) /**< \brief (EIC_NMIFLAG reset_value) NMI Interrupt Flag */
#define EIC_NMIFLAG_NMI_Pos 0 /**< \brief (EIC_NMIFLAG) NMI Interrupt Flag */
#define EIC_NMIFLAG_NMI (_U_(0x1) << EIC_NMIFLAG_NMI_Pos)
#define EIC_NMIFLAG_MASK _U_(0x0001) /**< \brief (EIC_NMIFLAG) MASK Register */
/* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) (R/ 32) Syncbusy register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software reset synchronisation */
uint32_t ENABLE:1; /*!< bit: 1 Enable synchronisation */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_SYNCBUSY_OFFSET 0x04 /**< \brief (EIC_SYNCBUSY offset) Syncbusy register */
#define EIC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (EIC_SYNCBUSY reset_value) Syncbusy register */
#define EIC_SYNCBUSY_SWRST_Pos 0 /**< \brief (EIC_SYNCBUSY) Software reset synchronisation */
#define EIC_SYNCBUSY_SWRST (_U_(0x1) << EIC_SYNCBUSY_SWRST_Pos)
#define EIC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (EIC_SYNCBUSY) Enable synchronisation */
#define EIC_SYNCBUSY_ENABLE (_U_(0x1) << EIC_SYNCBUSY_ENABLE_Pos)
#define EIC_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (EIC_SYNCBUSY) MASK Register */
/* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_EVCTRL_OFFSET 0x08 /**< \brief (EIC_EVCTRL offset) Event Control */
#define EIC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (EIC_EVCTRL reset_value) Event Control */
#define EIC_EVCTRL_EXTINTEO_Pos 0 /**< \brief (EIC_EVCTRL) External Interrupt Event Output Enable */
#define EIC_EVCTRL_EXTINTEO_Msk (_U_(0xFFFF) << EIC_EVCTRL_EXTINTEO_Pos)
#define EIC_EVCTRL_EXTINTEO(value) (EIC_EVCTRL_EXTINTEO_Msk & ((value) << EIC_EVCTRL_EXTINTEO_Pos))
#define EIC_EVCTRL_MASK _U_(0x0000FFFF) /**< \brief (EIC_EVCTRL) MASK Register */
/* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_INTENCLR_OFFSET 0x0C /**< \brief (EIC_INTENCLR offset) Interrupt Enable Clear */
#define EIC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENCLR reset_value) Interrupt Enable Clear */
#define EIC_INTENCLR_EXTINT_Pos 0 /**< \brief (EIC_INTENCLR) External Interrupt Disable */
#define EIC_INTENCLR_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENCLR_EXTINT_Pos)
#define EIC_INTENCLR_EXTINT(value) (EIC_INTENCLR_EXTINT_Msk & ((value) << EIC_INTENCLR_EXTINT_Pos))
#define EIC_INTENCLR_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENCLR) MASK Register */
/* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Disable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_INTENSET_OFFSET 0x10 /**< \brief (EIC_INTENSET offset) Interrupt Enable Set */
#define EIC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTENSET reset_value) Interrupt Enable Set */
#define EIC_INTENSET_EXTINT_Pos 0 /**< \brief (EIC_INTENSET) External Interrupt Disable */
#define EIC_INTENSET_EXTINT_Msk (_U_(0xFFFF) << EIC_INTENSET_EXTINT_Pos)
#define EIC_INTENSET_EXTINT(value) (EIC_INTENSET_EXTINT_Msk & ((value) << EIC_INTENSET_EXTINT_Pos))
#define EIC_INTENSET_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTENSET) MASK Register */
/* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Flag */
__I uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_INTFLAG_OFFSET 0x14 /**< \brief (EIC_INTFLAG offset) Interrupt Flag Status and Clear */
#define EIC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define EIC_INTFLAG_EXTINT_Pos 0 /**< \brief (EIC_INTFLAG) External Interrupt Flag */
#define EIC_INTFLAG_EXTINT_Msk (_U_(0xFFFF) << EIC_INTFLAG_EXTINT_Pos)
#define EIC_INTFLAG_EXTINT(value) (EIC_INTFLAG_EXTINT_Msk & ((value) << EIC_INTFLAG_EXTINT_Pos))
#define EIC_INTFLAG_MASK _U_(0x0000FFFF) /**< \brief (EIC_INTFLAG) MASK Register */
/* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) EIC Asynchronous edge Detection Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ASYNCH:16; /*!< bit: 0..15 EIC Asynchronous edge Detection Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_ASYNCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_ASYNCH_OFFSET 0x18 /**< \brief (EIC_ASYNCH offset) EIC Asynchronous edge Detection Enable */
#define EIC_ASYNCH_RESETVALUE _U_(0x00000000) /**< \brief (EIC_ASYNCH reset_value) EIC Asynchronous edge Detection Enable */
#define EIC_ASYNCH_ASYNCH_Pos 0 /**< \brief (EIC_ASYNCH) EIC Asynchronous edge Detection Enable */
#define EIC_ASYNCH_ASYNCH_Msk (_U_(0xFFFF) << EIC_ASYNCH_ASYNCH_Pos)
#define EIC_ASYNCH_ASYNCH(value) (EIC_ASYNCH_ASYNCH_Msk & ((value) << EIC_ASYNCH_ASYNCH_Pos))
#define EIC_ASYNCH_MASK _U_(0x0000FFFF) /**< \brief (EIC_ASYNCH) MASK Register */
/* -------- EIC_CONFIG : (EIC Offset: 0x1C) (R/W 32) Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */
uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */
uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */
uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */
uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */
uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */
uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */
uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */
uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EIC_CONFIG_OFFSET 0x1C /**< \brief (EIC_CONFIG offset) Configuration n */
#define EIC_CONFIG_RESETVALUE _U_(0x00000000) /**< \brief (EIC_CONFIG reset_value) Configuration n */
#define EIC_CONFIG_SENSE0_Pos 0 /**< \brief (EIC_CONFIG) Input Sense Configuration 0 */
#define EIC_CONFIG_SENSE0_Msk (_U_(0x7) << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0(value) (EIC_CONFIG_SENSE0_Msk & ((value) << EIC_CONFIG_SENSE0_Pos))
#define EIC_CONFIG_SENSE0_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE0_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE0_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE0_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE0_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE0_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG_SENSE0_NONE_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG_SENSE0_RISE_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG_SENSE0_FALL_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG_SENSE0_BOTH_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG_SENSE0_HIGH_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG_SENSE0_LOW_Val << EIC_CONFIG_SENSE0_Pos)
#define EIC_CONFIG_FILTEN0_Pos 3 /**< \brief (EIC_CONFIG) Filter Enable 0 */
#define EIC_CONFIG_FILTEN0 (_U_(0x1) << EIC_CONFIG_FILTEN0_Pos)
#define EIC_CONFIG_SENSE1_Pos 4 /**< \brief (EIC_CONFIG) Input Sense Configuration 1 */
#define EIC_CONFIG_SENSE1_Msk (_U_(0x7) << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1(value) (EIC_CONFIG_SENSE1_Msk & ((value) << EIC_CONFIG_SENSE1_Pos))
#define EIC_CONFIG_SENSE1_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE1_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE1_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE1_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE1_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE1_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE1_NONE (EIC_CONFIG_SENSE1_NONE_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_RISE (EIC_CONFIG_SENSE1_RISE_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_FALL (EIC_CONFIG_SENSE1_FALL_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_BOTH (EIC_CONFIG_SENSE1_BOTH_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_HIGH (EIC_CONFIG_SENSE1_HIGH_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_SENSE1_LOW (EIC_CONFIG_SENSE1_LOW_Val << EIC_CONFIG_SENSE1_Pos)
#define EIC_CONFIG_FILTEN1_Pos 7 /**< \brief (EIC_CONFIG) Filter Enable 1 */
#define EIC_CONFIG_FILTEN1 (_U_(0x1) << EIC_CONFIG_FILTEN1_Pos)
#define EIC_CONFIG_SENSE2_Pos 8 /**< \brief (EIC_CONFIG) Input Sense Configuration 2 */
#define EIC_CONFIG_SENSE2_Msk (_U_(0x7) << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2(value) (EIC_CONFIG_SENSE2_Msk & ((value) << EIC_CONFIG_SENSE2_Pos))
#define EIC_CONFIG_SENSE2_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE2_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE2_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE2_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE2_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE2_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE2_NONE (EIC_CONFIG_SENSE2_NONE_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_RISE (EIC_CONFIG_SENSE2_RISE_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_FALL (EIC_CONFIG_SENSE2_FALL_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_BOTH (EIC_CONFIG_SENSE2_BOTH_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_HIGH (EIC_CONFIG_SENSE2_HIGH_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_SENSE2_LOW (EIC_CONFIG_SENSE2_LOW_Val << EIC_CONFIG_SENSE2_Pos)
#define EIC_CONFIG_FILTEN2_Pos 11 /**< \brief (EIC_CONFIG) Filter Enable 2 */
#define EIC_CONFIG_FILTEN2 (_U_(0x1) << EIC_CONFIG_FILTEN2_Pos)
#define EIC_CONFIG_SENSE3_Pos 12 /**< \brief (EIC_CONFIG) Input Sense Configuration 3 */
#define EIC_CONFIG_SENSE3_Msk (_U_(0x7) << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3(value) (EIC_CONFIG_SENSE3_Msk & ((value) << EIC_CONFIG_SENSE3_Pos))
#define EIC_CONFIG_SENSE3_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE3_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE3_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE3_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE3_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE3_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE3_NONE (EIC_CONFIG_SENSE3_NONE_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_RISE (EIC_CONFIG_SENSE3_RISE_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_FALL (EIC_CONFIG_SENSE3_FALL_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_BOTH (EIC_CONFIG_SENSE3_BOTH_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_HIGH (EIC_CONFIG_SENSE3_HIGH_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_SENSE3_LOW (EIC_CONFIG_SENSE3_LOW_Val << EIC_CONFIG_SENSE3_Pos)
#define EIC_CONFIG_FILTEN3_Pos 15 /**< \brief (EIC_CONFIG) Filter Enable 3 */
#define EIC_CONFIG_FILTEN3 (_U_(0x1) << EIC_CONFIG_FILTEN3_Pos)
#define EIC_CONFIG_SENSE4_Pos 16 /**< \brief (EIC_CONFIG) Input Sense Configuration 4 */
#define EIC_CONFIG_SENSE4_Msk (_U_(0x7) << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4(value) (EIC_CONFIG_SENSE4_Msk & ((value) << EIC_CONFIG_SENSE4_Pos))
#define EIC_CONFIG_SENSE4_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE4_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE4_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE4_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE4_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE4_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE4_NONE (EIC_CONFIG_SENSE4_NONE_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_RISE (EIC_CONFIG_SENSE4_RISE_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_FALL (EIC_CONFIG_SENSE4_FALL_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_BOTH (EIC_CONFIG_SENSE4_BOTH_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_HIGH (EIC_CONFIG_SENSE4_HIGH_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_SENSE4_LOW (EIC_CONFIG_SENSE4_LOW_Val << EIC_CONFIG_SENSE4_Pos)
#define EIC_CONFIG_FILTEN4_Pos 19 /**< \brief (EIC_CONFIG) Filter Enable 4 */
#define EIC_CONFIG_FILTEN4 (_U_(0x1) << EIC_CONFIG_FILTEN4_Pos)
#define EIC_CONFIG_SENSE5_Pos 20 /**< \brief (EIC_CONFIG) Input Sense Configuration 5 */
#define EIC_CONFIG_SENSE5_Msk (_U_(0x7) << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5(value) (EIC_CONFIG_SENSE5_Msk & ((value) << EIC_CONFIG_SENSE5_Pos))
#define EIC_CONFIG_SENSE5_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE5_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE5_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE5_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE5_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE5_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE5_NONE (EIC_CONFIG_SENSE5_NONE_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_RISE (EIC_CONFIG_SENSE5_RISE_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_FALL (EIC_CONFIG_SENSE5_FALL_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_BOTH (EIC_CONFIG_SENSE5_BOTH_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_HIGH (EIC_CONFIG_SENSE5_HIGH_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_SENSE5_LOW (EIC_CONFIG_SENSE5_LOW_Val << EIC_CONFIG_SENSE5_Pos)
#define EIC_CONFIG_FILTEN5_Pos 23 /**< \brief (EIC_CONFIG) Filter Enable 5 */
#define EIC_CONFIG_FILTEN5 (_U_(0x1) << EIC_CONFIG_FILTEN5_Pos)
#define EIC_CONFIG_SENSE6_Pos 24 /**< \brief (EIC_CONFIG) Input Sense Configuration 6 */
#define EIC_CONFIG_SENSE6_Msk (_U_(0x7) << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6(value) (EIC_CONFIG_SENSE6_Msk & ((value) << EIC_CONFIG_SENSE6_Pos))
#define EIC_CONFIG_SENSE6_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE6_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE6_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE6_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE6_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE6_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE6_NONE (EIC_CONFIG_SENSE6_NONE_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_RISE (EIC_CONFIG_SENSE6_RISE_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_FALL (EIC_CONFIG_SENSE6_FALL_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_BOTH (EIC_CONFIG_SENSE6_BOTH_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_HIGH (EIC_CONFIG_SENSE6_HIGH_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_SENSE6_LOW (EIC_CONFIG_SENSE6_LOW_Val << EIC_CONFIG_SENSE6_Pos)
#define EIC_CONFIG_FILTEN6_Pos 27 /**< \brief (EIC_CONFIG) Filter Enable 6 */
#define EIC_CONFIG_FILTEN6 (_U_(0x1) << EIC_CONFIG_FILTEN6_Pos)
#define EIC_CONFIG_SENSE7_Pos 28 /**< \brief (EIC_CONFIG) Input Sense Configuration 7 */
#define EIC_CONFIG_SENSE7_Msk (_U_(0x7) << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7(value) (EIC_CONFIG_SENSE7_Msk & ((value) << EIC_CONFIG_SENSE7_Pos))
#define EIC_CONFIG_SENSE7_NONE_Val _U_(0x0) /**< \brief (EIC_CONFIG) No detection */
#define EIC_CONFIG_SENSE7_RISE_Val _U_(0x1) /**< \brief (EIC_CONFIG) Rising edge detection */
#define EIC_CONFIG_SENSE7_FALL_Val _U_(0x2) /**< \brief (EIC_CONFIG) Falling edge detection */
#define EIC_CONFIG_SENSE7_BOTH_Val _U_(0x3) /**< \brief (EIC_CONFIG) Both edges detection */
#define EIC_CONFIG_SENSE7_HIGH_Val _U_(0x4) /**< \brief (EIC_CONFIG) High level detection */
#define EIC_CONFIG_SENSE7_LOW_Val _U_(0x5) /**< \brief (EIC_CONFIG) Low level detection */
#define EIC_CONFIG_SENSE7_NONE (EIC_CONFIG_SENSE7_NONE_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_RISE (EIC_CONFIG_SENSE7_RISE_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_FALL (EIC_CONFIG_SENSE7_FALL_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_BOTH (EIC_CONFIG_SENSE7_BOTH_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_HIGH (EIC_CONFIG_SENSE7_HIGH_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_SENSE7_LOW (EIC_CONFIG_SENSE7_LOW_Val << EIC_CONFIG_SENSE7_Pos)
#define EIC_CONFIG_FILTEN7_Pos 31 /**< \brief (EIC_CONFIG) Filter Enable 7 */
#define EIC_CONFIG_FILTEN7 (_U_(0x1) << EIC_CONFIG_FILTEN7_Pos)
#define EIC_CONFIG_MASK _U_(0xFFFFFFFF) /**< \brief (EIC_CONFIG) MASK Register */
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) NMI Control */
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) NMI Interrupt Flag */
__I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Syncbusy register */
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */
__IO EIC_ASYNCH_Type ASYNCH; /**< \brief Offset: 0x18 (R/W 32) EIC Asynchronous edge Detection Enable */
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) Configuration n */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_EIC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for EVSYS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_EVSYS_COMPONENT_
#define _SAMC21_EVSYS_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR EVSYS */
/* ========================================================================== */
/** \addtogroup SAMC21_EVSYS Event System Interface */
/*@{*/
#define EVSYS_U2256
#define REV_EVSYS 0x102
/* -------- EVSYS_CTRLA : (EVSYS Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CTRLA_OFFSET 0x00 /**< \brief (EVSYS_CTRLA offset) Control */
#define EVSYS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (EVSYS_CTRLA reset_value) Control */
#define EVSYS_CTRLA_SWRST_Pos 0 /**< \brief (EVSYS_CTRLA) Software Reset */
#define EVSYS_CTRLA_SWRST (_U_(0x1) << EVSYS_CTRLA_SWRST_Pos)
#define EVSYS_CTRLA_MASK _U_(0x01) /**< \brief (EVSYS_CTRLA) MASK Register */
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
uint32_t USRRDY8:1; /*!< bit: 8 Channel 8 User Ready */
uint32_t USRRDY9:1; /*!< bit: 9 Channel 9 User Ready */
uint32_t USRRDY10:1; /*!< bit: 10 Channel 10 User Ready */
uint32_t USRRDY11:1; /*!< bit: 11 Channel 11 User Ready */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t CHBUSY0:1; /*!< bit: 16 Channel 0 Busy */
uint32_t CHBUSY1:1; /*!< bit: 17 Channel 1 Busy */
uint32_t CHBUSY2:1; /*!< bit: 18 Channel 2 Busy */
uint32_t CHBUSY3:1; /*!< bit: 19 Channel 3 Busy */
uint32_t CHBUSY4:1; /*!< bit: 20 Channel 4 Busy */
uint32_t CHBUSY5:1; /*!< bit: 21 Channel 5 Busy */
uint32_t CHBUSY6:1; /*!< bit: 22 Channel 6 Busy */
uint32_t CHBUSY7:1; /*!< bit: 23 Channel 7 Busy */
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t USRRDY:12; /*!< bit: 0..11 Channel x User Ready */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t CHBUSY:12; /*!< bit: 16..27 Channel x Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */
#define EVSYS_CHSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */
#define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */
#define EVSYS_CHSTATUS_USRRDY0 (_U_(1) << EVSYS_CHSTATUS_USRRDY0_Pos)
#define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */
#define EVSYS_CHSTATUS_USRRDY1 (_U_(1) << EVSYS_CHSTATUS_USRRDY1_Pos)
#define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */
#define EVSYS_CHSTATUS_USRRDY2 (_U_(1) << EVSYS_CHSTATUS_USRRDY2_Pos)
#define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */
#define EVSYS_CHSTATUS_USRRDY3 (_U_(1) << EVSYS_CHSTATUS_USRRDY3_Pos)
#define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */
#define EVSYS_CHSTATUS_USRRDY4 (_U_(1) << EVSYS_CHSTATUS_USRRDY4_Pos)
#define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */
#define EVSYS_CHSTATUS_USRRDY5 (_U_(1) << EVSYS_CHSTATUS_USRRDY5_Pos)
#define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */
#define EVSYS_CHSTATUS_USRRDY6 (_U_(1) << EVSYS_CHSTATUS_USRRDY6_Pos)
#define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */
#define EVSYS_CHSTATUS_USRRDY7 (_U_(1) << EVSYS_CHSTATUS_USRRDY7_Pos)
#define EVSYS_CHSTATUS_USRRDY8_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */
#define EVSYS_CHSTATUS_USRRDY8 (_U_(1) << EVSYS_CHSTATUS_USRRDY8_Pos)
#define EVSYS_CHSTATUS_USRRDY9_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */
#define EVSYS_CHSTATUS_USRRDY9 (_U_(1) << EVSYS_CHSTATUS_USRRDY9_Pos)
#define EVSYS_CHSTATUS_USRRDY10_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */
#define EVSYS_CHSTATUS_USRRDY10 (_U_(1) << EVSYS_CHSTATUS_USRRDY10_Pos)
#define EVSYS_CHSTATUS_USRRDY11_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */
#define EVSYS_CHSTATUS_USRRDY11 (_U_(1) << EVSYS_CHSTATUS_USRRDY11_Pos)
#define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */
#define EVSYS_CHSTATUS_USRRDY_Msk (_U_(0xFFF) << EVSYS_CHSTATUS_USRRDY_Pos)
#define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos))
#define EVSYS_CHSTATUS_CHBUSY0_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */
#define EVSYS_CHSTATUS_CHBUSY0 (_U_(1) << EVSYS_CHSTATUS_CHBUSY0_Pos)
#define EVSYS_CHSTATUS_CHBUSY1_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */
#define EVSYS_CHSTATUS_CHBUSY1 (_U_(1) << EVSYS_CHSTATUS_CHBUSY1_Pos)
#define EVSYS_CHSTATUS_CHBUSY2_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */
#define EVSYS_CHSTATUS_CHBUSY2 (_U_(1) << EVSYS_CHSTATUS_CHBUSY2_Pos)
#define EVSYS_CHSTATUS_CHBUSY3_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */
#define EVSYS_CHSTATUS_CHBUSY3 (_U_(1) << EVSYS_CHSTATUS_CHBUSY3_Pos)
#define EVSYS_CHSTATUS_CHBUSY4_Pos 20 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */
#define EVSYS_CHSTATUS_CHBUSY4 (_U_(1) << EVSYS_CHSTATUS_CHBUSY4_Pos)
#define EVSYS_CHSTATUS_CHBUSY5_Pos 21 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */
#define EVSYS_CHSTATUS_CHBUSY5 (_U_(1) << EVSYS_CHSTATUS_CHBUSY5_Pos)
#define EVSYS_CHSTATUS_CHBUSY6_Pos 22 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */
#define EVSYS_CHSTATUS_CHBUSY6 (_U_(1) << EVSYS_CHSTATUS_CHBUSY6_Pos)
#define EVSYS_CHSTATUS_CHBUSY7_Pos 23 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */
#define EVSYS_CHSTATUS_CHBUSY7 (_U_(1) << EVSYS_CHSTATUS_CHBUSY7_Pos)
#define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */
#define EVSYS_CHSTATUS_CHBUSY8 (_U_(1) << EVSYS_CHSTATUS_CHBUSY8_Pos)
#define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */
#define EVSYS_CHSTATUS_CHBUSY9 (_U_(1) << EVSYS_CHSTATUS_CHBUSY9_Pos)
#define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */
#define EVSYS_CHSTATUS_CHBUSY10 (_U_(1) << EVSYS_CHSTATUS_CHBUSY10_Pos)
#define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */
#define EVSYS_CHSTATUS_CHBUSY11 (_U_(1) << EVSYS_CHSTATUS_CHBUSY11_Pos)
#define EVSYS_CHSTATUS_CHBUSY_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */
#define EVSYS_CHSTATUS_CHBUSY_Msk (_U_(0xFFF) << EVSYS_CHSTATUS_CHBUSY_Pos)
#define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos))
#define EVSYS_CHSTATUS_MASK _U_(0x0FFF0FFF) /**< \brief (EVSYS_CHSTATUS) MASK Register */
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection Interrupt Enable */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */
#define EVSYS_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */
#define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR0 (_U_(1) << EVSYS_INTENCLR_OVR0_Pos)
#define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR1 (_U_(1) << EVSYS_INTENCLR_OVR1_Pos)
#define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR2 (_U_(1) << EVSYS_INTENCLR_OVR2_Pos)
#define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR3 (_U_(1) << EVSYS_INTENCLR_OVR3_Pos)
#define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR4 (_U_(1) << EVSYS_INTENCLR_OVR4_Pos)
#define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR5 (_U_(1) << EVSYS_INTENCLR_OVR5_Pos)
#define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR6 (_U_(1) << EVSYS_INTENCLR_OVR6_Pos)
#define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR7 (_U_(1) << EVSYS_INTENCLR_OVR7_Pos)
#define EVSYS_INTENCLR_OVR8_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR8 (_U_(1) << EVSYS_INTENCLR_OVR8_Pos)
#define EVSYS_INTENCLR_OVR9_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR9 (_U_(1) << EVSYS_INTENCLR_OVR9_Pos)
#define EVSYS_INTENCLR_OVR10_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR10 (_U_(1) << EVSYS_INTENCLR_OVR10_Pos)
#define EVSYS_INTENCLR_OVR11_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR11 (_U_(1) << EVSYS_INTENCLR_OVR11_Pos)
#define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */
#define EVSYS_INTENCLR_OVR_Msk (_U_(0xFFF) << EVSYS_INTENCLR_OVR_Pos)
#define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos))
#define EVSYS_INTENCLR_EVD0_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD0 (_U_(1) << EVSYS_INTENCLR_EVD0_Pos)
#define EVSYS_INTENCLR_EVD1_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD1 (_U_(1) << EVSYS_INTENCLR_EVD1_Pos)
#define EVSYS_INTENCLR_EVD2_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD2 (_U_(1) << EVSYS_INTENCLR_EVD2_Pos)
#define EVSYS_INTENCLR_EVD3_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD3 (_U_(1) << EVSYS_INTENCLR_EVD3_Pos)
#define EVSYS_INTENCLR_EVD4_Pos 20 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD4 (_U_(1) << EVSYS_INTENCLR_EVD4_Pos)
#define EVSYS_INTENCLR_EVD5_Pos 21 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD5 (_U_(1) << EVSYS_INTENCLR_EVD5_Pos)
#define EVSYS_INTENCLR_EVD6_Pos 22 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD6 (_U_(1) << EVSYS_INTENCLR_EVD6_Pos)
#define EVSYS_INTENCLR_EVD7_Pos 23 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD7 (_U_(1) << EVSYS_INTENCLR_EVD7_Pos)
#define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD8 (_U_(1) << EVSYS_INTENCLR_EVD8_Pos)
#define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD9 (_U_(1) << EVSYS_INTENCLR_EVD9_Pos)
#define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD10 (_U_(1) << EVSYS_INTENCLR_EVD10_Pos)
#define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD11 (_U_(1) << EVSYS_INTENCLR_EVD11_Pos)
#define EVSYS_INTENCLR_EVD_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */
#define EVSYS_INTENCLR_EVD_Msk (_U_(0xFFF) << EVSYS_INTENCLR_EVD_Pos)
#define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos))
#define EVSYS_INTENCLR_MASK _U_(0x0FFF0FFF) /**< \brief (EVSYS_INTENCLR) MASK Register */
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection Interrupt Enable */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */
#define EVSYS_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */
#define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR0 (_U_(1) << EVSYS_INTENSET_OVR0_Pos)
#define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR1 (_U_(1) << EVSYS_INTENSET_OVR1_Pos)
#define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR2 (_U_(1) << EVSYS_INTENSET_OVR2_Pos)
#define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR3 (_U_(1) << EVSYS_INTENSET_OVR3_Pos)
#define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR4 (_U_(1) << EVSYS_INTENSET_OVR4_Pos)
#define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR5 (_U_(1) << EVSYS_INTENSET_OVR5_Pos)
#define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR6 (_U_(1) << EVSYS_INTENSET_OVR6_Pos)
#define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR7 (_U_(1) << EVSYS_INTENSET_OVR7_Pos)
#define EVSYS_INTENSET_OVR8_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR8 (_U_(1) << EVSYS_INTENSET_OVR8_Pos)
#define EVSYS_INTENSET_OVR9_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR9 (_U_(1) << EVSYS_INTENSET_OVR9_Pos)
#define EVSYS_INTENSET_OVR10_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR10 (_U_(1) << EVSYS_INTENSET_OVR10_Pos)
#define EVSYS_INTENSET_OVR11_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR11 (_U_(1) << EVSYS_INTENSET_OVR11_Pos)
#define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */
#define EVSYS_INTENSET_OVR_Msk (_U_(0xFFF) << EVSYS_INTENSET_OVR_Pos)
#define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos))
#define EVSYS_INTENSET_EVD0_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD0 (_U_(1) << EVSYS_INTENSET_EVD0_Pos)
#define EVSYS_INTENSET_EVD1_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD1 (_U_(1) << EVSYS_INTENSET_EVD1_Pos)
#define EVSYS_INTENSET_EVD2_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD2 (_U_(1) << EVSYS_INTENSET_EVD2_Pos)
#define EVSYS_INTENSET_EVD3_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD3 (_U_(1) << EVSYS_INTENSET_EVD3_Pos)
#define EVSYS_INTENSET_EVD4_Pos 20 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD4 (_U_(1) << EVSYS_INTENSET_EVD4_Pos)
#define EVSYS_INTENSET_EVD5_Pos 21 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD5 (_U_(1) << EVSYS_INTENSET_EVD5_Pos)
#define EVSYS_INTENSET_EVD6_Pos 22 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD6 (_U_(1) << EVSYS_INTENSET_EVD6_Pos)
#define EVSYS_INTENSET_EVD7_Pos 23 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD7 (_U_(1) << EVSYS_INTENSET_EVD7_Pos)
#define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD8 (_U_(1) << EVSYS_INTENSET_EVD8_Pos)
#define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD9 (_U_(1) << EVSYS_INTENSET_EVD9_Pos)
#define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD10 (_U_(1) << EVSYS_INTENSET_EVD10_Pos)
#define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD11 (_U_(1) << EVSYS_INTENSET_EVD11_Pos)
#define EVSYS_INTENSET_EVD_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */
#define EVSYS_INTENSET_EVD_Msk (_U_(0xFFF) << EVSYS_INTENSET_EVD_Pos)
#define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos))
#define EVSYS_INTENSET_MASK _U_(0x0FFF0FFF) /**< \brief (EVSYS_INTENSET) MASK Register */
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
__I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
__I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
__I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
__I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
__I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
__I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
__I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
__I uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun */
__I uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun */
__I uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun */
__I uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun */
__I uint32_t :4; /*!< bit: 12..15 Reserved */
__I uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection */
__I uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection */
__I uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection */
__I uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection */
__I uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection */
__I uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection */
__I uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection */
__I uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection */
__I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
__I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
__I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
__I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
__I uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun */
__I uint32_t :4; /*!< bit: 12..15 Reserved */
__I uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection */
__I uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */
#define EVSYS_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */
#define EVSYS_INTFLAG_OVR0 (_U_(1) << EVSYS_INTFLAG_OVR0_Pos)
#define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */
#define EVSYS_INTFLAG_OVR1 (_U_(1) << EVSYS_INTFLAG_OVR1_Pos)
#define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */
#define EVSYS_INTFLAG_OVR2 (_U_(1) << EVSYS_INTFLAG_OVR2_Pos)
#define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */
#define EVSYS_INTFLAG_OVR3 (_U_(1) << EVSYS_INTFLAG_OVR3_Pos)
#define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */
#define EVSYS_INTFLAG_OVR4 (_U_(1) << EVSYS_INTFLAG_OVR4_Pos)
#define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */
#define EVSYS_INTFLAG_OVR5 (_U_(1) << EVSYS_INTFLAG_OVR5_Pos)
#define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */
#define EVSYS_INTFLAG_OVR6 (_U_(1) << EVSYS_INTFLAG_OVR6_Pos)
#define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */
#define EVSYS_INTFLAG_OVR7 (_U_(1) << EVSYS_INTFLAG_OVR7_Pos)
#define EVSYS_INTFLAG_OVR8_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */
#define EVSYS_INTFLAG_OVR8 (_U_(1) << EVSYS_INTFLAG_OVR8_Pos)
#define EVSYS_INTFLAG_OVR9_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */
#define EVSYS_INTFLAG_OVR9 (_U_(1) << EVSYS_INTFLAG_OVR9_Pos)
#define EVSYS_INTFLAG_OVR10_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */
#define EVSYS_INTFLAG_OVR10 (_U_(1) << EVSYS_INTFLAG_OVR10_Pos)
#define EVSYS_INTFLAG_OVR11_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */
#define EVSYS_INTFLAG_OVR11 (_U_(1) << EVSYS_INTFLAG_OVR11_Pos)
#define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */
#define EVSYS_INTFLAG_OVR_Msk (_U_(0xFFF) << EVSYS_INTFLAG_OVR_Pos)
#define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos))
#define EVSYS_INTFLAG_EVD0_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */
#define EVSYS_INTFLAG_EVD0 (_U_(1) << EVSYS_INTFLAG_EVD0_Pos)
#define EVSYS_INTFLAG_EVD1_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */
#define EVSYS_INTFLAG_EVD1 (_U_(1) << EVSYS_INTFLAG_EVD1_Pos)
#define EVSYS_INTFLAG_EVD2_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */
#define EVSYS_INTFLAG_EVD2 (_U_(1) << EVSYS_INTFLAG_EVD2_Pos)
#define EVSYS_INTFLAG_EVD3_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */
#define EVSYS_INTFLAG_EVD3 (_U_(1) << EVSYS_INTFLAG_EVD3_Pos)
#define EVSYS_INTFLAG_EVD4_Pos 20 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */
#define EVSYS_INTFLAG_EVD4 (_U_(1) << EVSYS_INTFLAG_EVD4_Pos)
#define EVSYS_INTFLAG_EVD5_Pos 21 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */
#define EVSYS_INTFLAG_EVD5 (_U_(1) << EVSYS_INTFLAG_EVD5_Pos)
#define EVSYS_INTFLAG_EVD6_Pos 22 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */
#define EVSYS_INTFLAG_EVD6 (_U_(1) << EVSYS_INTFLAG_EVD6_Pos)
#define EVSYS_INTFLAG_EVD7_Pos 23 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */
#define EVSYS_INTFLAG_EVD7 (_U_(1) << EVSYS_INTFLAG_EVD7_Pos)
#define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */
#define EVSYS_INTFLAG_EVD8 (_U_(1) << EVSYS_INTFLAG_EVD8_Pos)
#define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */
#define EVSYS_INTFLAG_EVD9 (_U_(1) << EVSYS_INTFLAG_EVD9_Pos)
#define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */
#define EVSYS_INTFLAG_EVD10 (_U_(1) << EVSYS_INTFLAG_EVD10_Pos)
#define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */
#define EVSYS_INTFLAG_EVD11 (_U_(1) << EVSYS_INTFLAG_EVD11_Pos)
#define EVSYS_INTFLAG_EVD_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */
#define EVSYS_INTFLAG_EVD_Msk (_U_(0xFFF) << EVSYS_INTFLAG_EVD_Pos)
#define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos))
#define EVSYS_INTFLAG_MASK _U_(0x0FFF0FFF) /**< \brief (EVSYS_INTFLAG) MASK Register */
/* -------- EVSYS_SWEVT : (EVSYS Offset: 0x1C) ( /W 32) Software Event -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */
uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */
uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */
uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */
uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */
uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */
uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */
uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */
uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */
uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */
uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */
uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t CHANNEL:12; /*!< bit: 0..11 Channel x Software Selection */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_SWEVT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_SWEVT_OFFSET 0x1C /**< \brief (EVSYS_SWEVT offset) Software Event */
#define EVSYS_SWEVT_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */
#define EVSYS_SWEVT_CHANNEL0_Pos 0 /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */
#define EVSYS_SWEVT_CHANNEL0 (_U_(1) << EVSYS_SWEVT_CHANNEL0_Pos)
#define EVSYS_SWEVT_CHANNEL1_Pos 1 /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */
#define EVSYS_SWEVT_CHANNEL1 (_U_(1) << EVSYS_SWEVT_CHANNEL1_Pos)
#define EVSYS_SWEVT_CHANNEL2_Pos 2 /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */
#define EVSYS_SWEVT_CHANNEL2 (_U_(1) << EVSYS_SWEVT_CHANNEL2_Pos)
#define EVSYS_SWEVT_CHANNEL3_Pos 3 /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */
#define EVSYS_SWEVT_CHANNEL3 (_U_(1) << EVSYS_SWEVT_CHANNEL3_Pos)
#define EVSYS_SWEVT_CHANNEL4_Pos 4 /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */
#define EVSYS_SWEVT_CHANNEL4 (_U_(1) << EVSYS_SWEVT_CHANNEL4_Pos)
#define EVSYS_SWEVT_CHANNEL5_Pos 5 /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */
#define EVSYS_SWEVT_CHANNEL5 (_U_(1) << EVSYS_SWEVT_CHANNEL5_Pos)
#define EVSYS_SWEVT_CHANNEL6_Pos 6 /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */
#define EVSYS_SWEVT_CHANNEL6 (_U_(1) << EVSYS_SWEVT_CHANNEL6_Pos)
#define EVSYS_SWEVT_CHANNEL7_Pos 7 /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */
#define EVSYS_SWEVT_CHANNEL7 (_U_(1) << EVSYS_SWEVT_CHANNEL7_Pos)
#define EVSYS_SWEVT_CHANNEL8_Pos 8 /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */
#define EVSYS_SWEVT_CHANNEL8 (_U_(1) << EVSYS_SWEVT_CHANNEL8_Pos)
#define EVSYS_SWEVT_CHANNEL9_Pos 9 /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */
#define EVSYS_SWEVT_CHANNEL9 (_U_(1) << EVSYS_SWEVT_CHANNEL9_Pos)
#define EVSYS_SWEVT_CHANNEL10_Pos 10 /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */
#define EVSYS_SWEVT_CHANNEL10 (_U_(1) << EVSYS_SWEVT_CHANNEL10_Pos)
#define EVSYS_SWEVT_CHANNEL11_Pos 11 /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */
#define EVSYS_SWEVT_CHANNEL11 (_U_(1) << EVSYS_SWEVT_CHANNEL11_Pos)
#define EVSYS_SWEVT_CHANNEL_Pos 0 /**< \brief (EVSYS_SWEVT) Channel x Software Selection */
#define EVSYS_SWEVT_CHANNEL_Msk (_U_(0xFFF) << EVSYS_SWEVT_CHANNEL_Pos)
#define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos))
#define EVSYS_SWEVT_MASK _U_(0x00000FFF) /**< \brief (EVSYS_SWEVT) MASK Register */
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x20) (R/W 32) Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */
uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */
uint32_t :2; /*!< bit: 12..13 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */
uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_CHANNEL_OFFSET 0x20 /**< \brief (EVSYS_CHANNEL offset) Channel n */
#define EVSYS_CHANNEL_RESETVALUE _U_(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n */
#define EVSYS_CHANNEL_EVGEN_Pos 0 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */
#define EVSYS_CHANNEL_EVGEN_Msk (_U_(0x7F) << EVSYS_CHANNEL_EVGEN_Pos)
#define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos))
#define EVSYS_CHANNEL_PATH_Pos 8 /**< \brief (EVSYS_CHANNEL) Path Selection */
#define EVSYS_CHANNEL_PATH_Msk (_U_(0x3) << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos))
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) Synchronous path */
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Resynchronized path */
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Asynchronous path */
#define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos)
#define EVSYS_CHANNEL_EDGSEL_Pos 10 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */
#define EVSYS_CHANNEL_EDGSEL_Msk (_U_(0x3) << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos))
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U_(0x0) /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U_(0x1) /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U_(0x2) /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U_(0x3) /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */
#define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos)
#define EVSYS_CHANNEL_RUNSTDBY_Pos 14 /**< \brief (EVSYS_CHANNEL) Run in standby */
#define EVSYS_CHANNEL_RUNSTDBY (_U_(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos)
#define EVSYS_CHANNEL_ONDEMAND_Pos 15 /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */
#define EVSYS_CHANNEL_ONDEMAND (_U_(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos)
#define EVSYS_CHANNEL_MASK _U_(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */
/* -------- EVSYS_USER : (EVSYS Offset: 0x80) (R/W 32) User Multiplexer n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL:5; /*!< bit: 0.. 4 Channel Event Selection */
uint32_t :27; /*!< bit: 5..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define EVSYS_USER_OFFSET 0x80 /**< \brief (EVSYS_USER offset) User Multiplexer n */
#define EVSYS_USER_RESETVALUE _U_(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */
#define EVSYS_USER_CHANNEL_Pos 0 /**< \brief (EVSYS_USER) Channel Event Selection */
#define EVSYS_USER_CHANNEL_Msk (_U_(0x1F) << EVSYS_USER_CHANNEL_Pos)
#define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos))
#define EVSYS_USER_MASK _U_(0x0000001F) /**< \brief (EVSYS_USER) MASK Register */
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
RoReg8 Reserved1[0xB];
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
__O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x1C ( /W 32) Software Event */
__IO EVSYS_CHANNEL_Type CHANNEL[12]; /**< \brief Offset: 0x20 (R/W 32) Channel n */
RoReg8 Reserved2[0x30];
__IO EVSYS_USER_Type USER[47]; /**< \brief Offset: 0x80 (R/W 32) User Multiplexer n */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_EVSYS_COMPONENT_ */

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lib/samc21/samc21/include/component/freqm.h Normal file
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/**
* \file
*
* \brief Component description for FREQM
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_FREQM_COMPONENT_
#define _SAMC21_FREQM_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR FREQM */
/* ========================================================================== */
/** \addtogroup SAMC21_FREQM Frequency Meter */
/*@{*/
#define FREQM_U2257
#define REV_FREQM 0x101
/* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_CTRLA_OFFSET 0x00 /**< \brief (FREQM_CTRLA offset) Control A Register */
#define FREQM_CTRLA_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLA reset_value) Control A Register */
#define FREQM_CTRLA_SWRST_Pos 0 /**< \brief (FREQM_CTRLA) Software Reset */
#define FREQM_CTRLA_SWRST (_U_(0x1) << FREQM_CTRLA_SWRST_Pos)
#define FREQM_CTRLA_ENABLE_Pos 1 /**< \brief (FREQM_CTRLA) Enable */
#define FREQM_CTRLA_ENABLE (_U_(0x1) << FREQM_CTRLA_ENABLE_Pos)
#define FREQM_CTRLA_MASK _U_(0x03) /**< \brief (FREQM_CTRLA) MASK Register */
/* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START:1; /*!< bit: 0 Start Measurement */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_CTRLB_OFFSET 0x01 /**< \brief (FREQM_CTRLB offset) Control B Register */
#define FREQM_CTRLB_RESETVALUE _U_(0x00) /**< \brief (FREQM_CTRLB reset_value) Control B Register */
#define FREQM_CTRLB_START_Pos 0 /**< \brief (FREQM_CTRLB) Start Measurement */
#define FREQM_CTRLB_START (_U_(0x1) << FREQM_CTRLB_START_Pos)
#define FREQM_CTRLB_MASK _U_(0x01) /**< \brief (FREQM_CTRLB) MASK Register */
/* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t REFNUM:8; /*!< bit: 0.. 7 Number of Reference Clock Cycles */
uint16_t :8; /*!< bit: 8..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} FREQM_CFGA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_CFGA_OFFSET 0x02 /**< \brief (FREQM_CFGA offset) Config A register */
#define FREQM_CFGA_RESETVALUE _U_(0x0000) /**< \brief (FREQM_CFGA reset_value) Config A register */
#define FREQM_CFGA_REFNUM_Pos 0 /**< \brief (FREQM_CFGA) Number of Reference Clock Cycles */
#define FREQM_CFGA_REFNUM_Msk (_U_(0xFF) << FREQM_CFGA_REFNUM_Pos)
#define FREQM_CFGA_REFNUM(value) (FREQM_CFGA_REFNUM_Msk & ((value) << FREQM_CFGA_REFNUM_Pos))
#define FREQM_CFGA_MASK _U_(0x00FF) /**< \brief (FREQM_CFGA) MASK Register */
/* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_INTENCLR_OFFSET 0x08 /**< \brief (FREQM_INTENCLR offset) Interrupt Enable Clear Register */
#define FREQM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENCLR reset_value) Interrupt Enable Clear Register */
#define FREQM_INTENCLR_DONE_Pos 0 /**< \brief (FREQM_INTENCLR) Measurement Done Interrupt Enable */
#define FREQM_INTENCLR_DONE (_U_(0x1) << FREQM_INTENCLR_DONE_Pos)
#define FREQM_INTENCLR_MASK _U_(0x01) /**< \brief (FREQM_INTENCLR) MASK Register */
/* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_INTENSET_OFFSET 0x09 /**< \brief (FREQM_INTENSET offset) Interrupt Enable Set Register */
#define FREQM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTENSET reset_value) Interrupt Enable Set Register */
#define FREQM_INTENSET_DONE_Pos 0 /**< \brief (FREQM_INTENSET) Measurement Done Interrupt Enable */
#define FREQM_INTENSET_DONE (_U_(0x1) << FREQM_INTENSET_DONE_Pos)
#define FREQM_INTENSET_MASK _U_(0x01) /**< \brief (FREQM_INTENSET) MASK Register */
/* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t DONE:1; /*!< bit: 0 Measurement Done */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_INTFLAG_OFFSET 0x0A /**< \brief (FREQM_INTFLAG offset) Interrupt Flag Register */
#define FREQM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (FREQM_INTFLAG reset_value) Interrupt Flag Register */
#define FREQM_INTFLAG_DONE_Pos 0 /**< \brief (FREQM_INTFLAG) Measurement Done */
#define FREQM_INTFLAG_DONE (_U_(0x1) << FREQM_INTFLAG_DONE_Pos)
#define FREQM_INTFLAG_MASK _U_(0x01) /**< \brief (FREQM_INTFLAG) MASK Register */
/* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t BUSY:1; /*!< bit: 0 FREQM Status */
uint8_t OVF:1; /*!< bit: 1 Sticky Count Value Overflow */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} FREQM_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_STATUS_OFFSET 0x0B /**< \brief (FREQM_STATUS offset) Status Register */
#define FREQM_STATUS_RESETVALUE _U_(0x00) /**< \brief (FREQM_STATUS reset_value) Status Register */
#define FREQM_STATUS_BUSY_Pos 0 /**< \brief (FREQM_STATUS) FREQM Status */
#define FREQM_STATUS_BUSY (_U_(0x1) << FREQM_STATUS_BUSY_Pos)
#define FREQM_STATUS_OVF_Pos 1 /**< \brief (FREQM_STATUS) Sticky Count Value Overflow */
#define FREQM_STATUS_OVF (_U_(0x1) << FREQM_STATUS_OVF_Pos)
#define FREQM_STATUS_MASK _U_(0x03) /**< \brief (FREQM_STATUS) MASK Register */
/* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) (R/ 32) Synchronization Busy Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} FREQM_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_SYNCBUSY_OFFSET 0x0C /**< \brief (FREQM_SYNCBUSY offset) Synchronization Busy Register */
#define FREQM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_SYNCBUSY reset_value) Synchronization Busy Register */
#define FREQM_SYNCBUSY_SWRST_Pos 0 /**< \brief (FREQM_SYNCBUSY) Software Reset */
#define FREQM_SYNCBUSY_SWRST (_U_(0x1) << FREQM_SYNCBUSY_SWRST_Pos)
#define FREQM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (FREQM_SYNCBUSY) Enable */
#define FREQM_SYNCBUSY_ENABLE (_U_(0x1) << FREQM_SYNCBUSY_ENABLE_Pos)
#define FREQM_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (FREQM_SYNCBUSY) MASK Register */
/* -------- FREQM_VALUE : (FREQM Offset: 0x10) (R/ 32) Count Value Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} FREQM_VALUE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define FREQM_VALUE_OFFSET 0x10 /**< \brief (FREQM_VALUE offset) Count Value Register */
#define FREQM_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (FREQM_VALUE reset_value) Count Value Register */
#define FREQM_VALUE_VALUE_Pos 0 /**< \brief (FREQM_VALUE) Measurement Value */
#define FREQM_VALUE_VALUE_Msk (_U_(0xFFFFFF) << FREQM_VALUE_VALUE_Pos)
#define FREQM_VALUE_VALUE(value) (FREQM_VALUE_VALUE_Msk & ((value) << FREQM_VALUE_VALUE_Pos))
#define FREQM_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (FREQM_VALUE) MASK Register */
/** \brief FREQM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO FREQM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */
__O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */
__IO FREQM_CFGA_Type CFGA; /**< \brief Offset: 0x02 (R/W 16) Config A register */
RoReg8 Reserved1[0x4];
__IO FREQM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */
__IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set Register */
__IO FREQM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Register */
__IO FREQM_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status Register */
__I FREQM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) Synchronization Busy Register */
__I FREQM_VALUE_Type VALUE; /**< \brief Offset: 0x10 (R/ 32) Count Value Register */
} Freqm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_FREQM_COMPONENT_ */

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/**
* \file
*
* \brief Component description for GCLK
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_GCLK_COMPONENT_
#define _SAMC21_GCLK_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR GCLK */
/* ========================================================================== */
/** \addtogroup SAMC21_GCLK Generic Clock Generator */
/*@{*/
#define GCLK_U2122
#define REV_GCLK 0x111
/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */
#define GCLK_CTRLA_RESETVALUE _U_(0x00) /**< \brief (GCLK_CTRLA reset_value) Control */
#define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */
#define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos)
#define GCLK_CTRLA_MASK _U_(0x01) /**< \brief (GCLK_CTRLA) MASK Register */
/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */
uint32_t :1; /*!< bit: 1 Reserved */
uint32_t GENCTRL0:1; /*!< bit: 2 Generic Clock Generator Control 0 Synchronization Busy bits */
uint32_t GENCTRL1:1; /*!< bit: 3 Generic Clock Generator Control 1 Synchronization Busy bits */
uint32_t GENCTRL2:1; /*!< bit: 4 Generic Clock Generator Control 2 Synchronization Busy bits */
uint32_t GENCTRL3:1; /*!< bit: 5 Generic Clock Generator Control 3 Synchronization Busy bits */
uint32_t GENCTRL4:1; /*!< bit: 6 Generic Clock Generator Control 4 Synchronization Busy bits */
uint32_t GENCTRL5:1; /*!< bit: 7 Generic Clock Generator Control 5 Synchronization Busy bits */
uint32_t GENCTRL6:1; /*!< bit: 8 Generic Clock Generator Control 6 Synchronization Busy bits */
uint32_t GENCTRL7:1; /*!< bit: 9 Generic Clock Generator Control 7 Synchronization Busy bits */
uint32_t GENCTRL8:1; /*!< bit: 10 Generic Clock Generator Control 8 Synchronization Busy bits */
uint32_t :21; /*!< bit: 11..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t GENCTRL:9; /*!< bit: 2..10 Generic Clock Generator Control x Synchronization Busy bits */
uint32_t :21; /*!< bit: 11..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} GCLK_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
#define GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
#define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
#define GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos)
#define GCLK_SYNCBUSY_GENCTRL0_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos)
#define GCLK_SYNCBUSY_GENCTRL1_Pos 3 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos)
#define GCLK_SYNCBUSY_GENCTRL2_Pos 4 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos)
#define GCLK_SYNCBUSY_GENCTRL3_Pos 5 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos)
#define GCLK_SYNCBUSY_GENCTRL4_Pos 6 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos)
#define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos)
#define GCLK_SYNCBUSY_GENCTRL6_Pos 8 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos)
#define GCLK_SYNCBUSY_GENCTRL7_Pos 9 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos)
#define GCLK_SYNCBUSY_GENCTRL8_Pos 10 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos)
#define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */
#define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0x1FF) << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos))
#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
#define GCLK_SYNCBUSY_MASK _U_(0x000007FD) /**< \brief (GCLK_SYNCBUSY) MASK Register */
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SRC:3; /*!< bit: 0.. 2 Source Select */
uint32_t :5; /*!< bit: 3.. 7 Reserved */
uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */
uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */
uint32_t OOV:1; /*!< bit: 10 Output Off Value */
uint32_t OE:1; /*!< bit: 11 Output Enable */
uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */
uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */
uint32_t :2; /*!< bit: 14..15 Reserved */
uint32_t DIV:16; /*!< bit: 16..31 Division Factor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
#define GCLK_GENCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
#define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */
#define GCLK_GENCTRL_SRC_Msk (_U_(0x7) << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
#define GCLK_GENCTRL_SRC_XOSC_Val _U_(0x0) /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x1) /**< \brief (GCLK_GENCTRL) Generator input pad */
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x2) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x3) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
#define GCLK_GENCTRL_SRC_OSC32K_Val _U_(0x4) /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
#define GCLK_GENCTRL_SRC_OSC48M_Val _U_(0x6) /**< \brief (GCLK_GENCTRL) OSC48M oscillator output */
#define GCLK_GENCTRL_SRC_DPLL96M_Val _U_(0x7) /**< \brief (GCLK_GENCTRL) DPLL96M output */
#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_OSC48M (GCLK_GENCTRL_SRC_OSC48M_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_SRC_DPLL96M (GCLK_GENCTRL_SRC_DPLL96M_Val << GCLK_GENCTRL_SRC_Pos)
#define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
#define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
#define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
#define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
#define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */
#define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
#define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */
#define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
#define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */
#define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
#define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */
#define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
#define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */
#define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos)
#define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos))
#define GCLK_GENCTRL_MASK _U_(0xFFFF3F07) /**< \brief (GCLK_GENCTRL) MASK Register */
/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t CHEN:1; /*!< bit: 6 Channel Enable */
uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_PCHCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
#define GCLK_PCHCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
#define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
#define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos))
#define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0) /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
#define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1) /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
#define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2) /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
#define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3) /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
#define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4) /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
#define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5) /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
#define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6) /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
#define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7) /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
#define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8) /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */
#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos)
#define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */
#define GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos)
#define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */
#define GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos)
#define GCLK_PCHCTRL_MASK _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
RoReg8 Reserved1[0x3];
__I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
RoReg8 Reserved2[0x18];
__IO GCLK_GENCTRL_Type GENCTRL[9]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
RoReg8 Reserved3[0x3C];
__IO GCLK_PCHCTRL_Type PCHCTRL[41]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_GCLK_COMPONENT_ */

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/**
* \file
*
* \brief Component description for HMATRIXB
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_HMATRIXB_COMPONENT_
#define _SAMC21_HMATRIXB_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR HMATRIXB */
/* ========================================================================== */
/** \addtogroup SAMC21_HMATRIXB HSB Matrix */
/*@{*/
#define HMATRIXB_I7638
#define REV_HMATRIXB 0x213
/* -------- HMATRIXB_MCFG : (HMATRIXB Offset: 0x000) (R/W 32) Master Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ULBT:3; /*!< bit: 0.. 2 Undefined Length Burst Type */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_MCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define HMATRIXB_MCFG_OFFSET 0x000 /**< \brief (HMATRIXB_MCFG offset) Master Configuration */
#define HMATRIXB_MCFG_RESETVALUE _U_(0x00000002) /**< \brief (HMATRIXB_MCFG reset_value) Master Configuration */
#define HMATRIXB_MCFG_ULBT_Pos 0 /**< \brief (HMATRIXB_MCFG) Undefined Length Burst Type */
#define HMATRIXB_MCFG_ULBT_Msk (_U_(0x7) << HMATRIXB_MCFG_ULBT_Pos)
#define HMATRIXB_MCFG_ULBT(value) (HMATRIXB_MCFG_ULBT_Msk & ((value) << HMATRIXB_MCFG_ULBT_Pos))
#define HMATRIXB_MCFG_ULBT_INFINITE_Val _U_(0x0) /**< \brief (HMATRIXB_MCFG) Infinite Length */
#define HMATRIXB_MCFG_ULBT_SINGLE_Val _U_(0x1) /**< \brief (HMATRIXB_MCFG) Single Access */
#define HMATRIXB_MCFG_ULBT_FOUR_BEAT_Val _U_(0x2) /**< \brief (HMATRIXB_MCFG) Four Beat Burst */
#define HMATRIXB_MCFG_ULBT_EIGHT_BEAT_Val _U_(0x3) /**< \brief (HMATRIXB_MCFG) Eight Beat Burst */
#define HMATRIXB_MCFG_ULBT_SIXTEEN_BEAT_Val _U_(0x4) /**< \brief (HMATRIXB_MCFG) Sixteen Beat Burst */
#define HMATRIXB_MCFG_ULBT_INFINITE (HMATRIXB_MCFG_ULBT_INFINITE_Val << HMATRIXB_MCFG_ULBT_Pos)
#define HMATRIXB_MCFG_ULBT_SINGLE (HMATRIXB_MCFG_ULBT_SINGLE_Val << HMATRIXB_MCFG_ULBT_Pos)
#define HMATRIXB_MCFG_ULBT_FOUR_BEAT (HMATRIXB_MCFG_ULBT_FOUR_BEAT_Val << HMATRIXB_MCFG_ULBT_Pos)
#define HMATRIXB_MCFG_ULBT_EIGHT_BEAT (HMATRIXB_MCFG_ULBT_EIGHT_BEAT_Val << HMATRIXB_MCFG_ULBT_Pos)
#define HMATRIXB_MCFG_ULBT_SIXTEEN_BEAT (HMATRIXB_MCFG_ULBT_SIXTEEN_BEAT_Val << HMATRIXB_MCFG_ULBT_Pos)
#define HMATRIXB_MCFG_MASK _U_(0x00000007) /**< \brief (HMATRIXB_MCFG) MASK Register */
/* -------- HMATRIXB_SCFG : (HMATRIXB Offset: 0x040) (R/W 32) Slave Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SLOT_CYCLE:8; /*!< bit: 0.. 7 Maximum Number of Allowed Cycles for a Burst */
uint32_t :8; /*!< bit: 8..15 Reserved */
uint32_t DEFMSTR_TYPE:2; /*!< bit: 16..17 Default Master Type */
uint32_t FIXED_DEFMSTR:4; /*!< bit: 18..21 Fixed Index of Default Master */
uint32_t :2; /*!< bit: 22..23 Reserved */
uint32_t ARBT:1; /*!< bit: 24 Arbitration Type */
uint32_t :7; /*!< bit: 25..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_SCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define HMATRIXB_SCFG_OFFSET 0x040 /**< \brief (HMATRIXB_SCFG offset) Slave Configuration */
#define HMATRIXB_SCFG_RESETVALUE _U_(0x00000010) /**< \brief (HMATRIXB_SCFG reset_value) Slave Configuration */
#define HMATRIXB_SCFG_SLOT_CYCLE_Pos 0 /**< \brief (HMATRIXB_SCFG) Maximum Number of Allowed Cycles for a Burst */
#define HMATRIXB_SCFG_SLOT_CYCLE_Msk (_U_(0xFF) << HMATRIXB_SCFG_SLOT_CYCLE_Pos)
#define HMATRIXB_SCFG_SLOT_CYCLE(value) (HMATRIXB_SCFG_SLOT_CYCLE_Msk & ((value) << HMATRIXB_SCFG_SLOT_CYCLE_Pos))
#define HMATRIXB_SCFG_DEFMSTR_TYPE_Pos 16 /**< \brief (HMATRIXB_SCFG) Default Master Type */
#define HMATRIXB_SCFG_DEFMSTR_TYPE_Msk (_U_(0x3) << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos)
#define HMATRIXB_SCFG_DEFMSTR_TYPE(value) (HMATRIXB_SCFG_DEFMSTR_TYPE_Msk & ((value) << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos))
#define HMATRIXB_SCFG_DEFMSTR_TYPE_NO_DEFAULT_Val _U_(0x0) /**< \brief (HMATRIXB_SCFG) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. */
#define HMATRIXB_SCFG_DEFMSTR_TYPE_LAST_DEFAULT_Val _U_(0x1) /**< \brief (HMATRIXB_SCFG) Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. */
#define HMATRIXB_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT_Val _U_(0x2) /**< \brief (HMATRIXB_SCFG) Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave. */
#define HMATRIXB_SCFG_DEFMSTR_TYPE_NO_DEFAULT (HMATRIXB_SCFG_DEFMSTR_TYPE_NO_DEFAULT_Val << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos)
#define HMATRIXB_SCFG_DEFMSTR_TYPE_LAST_DEFAULT (HMATRIXB_SCFG_DEFMSTR_TYPE_LAST_DEFAULT_Val << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos)
#define HMATRIXB_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT (HMATRIXB_SCFG_DEFMSTR_TYPE_FIXED_DEFAULT_Val << HMATRIXB_SCFG_DEFMSTR_TYPE_Pos)
#define HMATRIXB_SCFG_FIXED_DEFMSTR_Pos 18 /**< \brief (HMATRIXB_SCFG) Fixed Index of Default Master */
#define HMATRIXB_SCFG_FIXED_DEFMSTR_Msk (_U_(0xF) << HMATRIXB_SCFG_FIXED_DEFMSTR_Pos)
#define HMATRIXB_SCFG_FIXED_DEFMSTR(value) (HMATRIXB_SCFG_FIXED_DEFMSTR_Msk & ((value) << HMATRIXB_SCFG_FIXED_DEFMSTR_Pos))
#define HMATRIXB_SCFG_ARBT_Pos 24 /**< \brief (HMATRIXB_SCFG) Arbitration Type */
#define HMATRIXB_SCFG_ARBT (_U_(0x1) << HMATRIXB_SCFG_ARBT_Pos)
#define HMATRIXB_SCFG_ARBT_ROUND_ROBIN_Val _U_(0x0) /**< \brief (HMATRIXB_SCFG) Round-Robin Arbitration */
#define HMATRIXB_SCFG_ARBT_FIXED_PRIORITY_Val _U_(0x1) /**< \brief (HMATRIXB_SCFG) Fixed Priority Arbitration */
#define HMATRIXB_SCFG_ARBT_ROUND_ROBIN (HMATRIXB_SCFG_ARBT_ROUND_ROBIN_Val << HMATRIXB_SCFG_ARBT_Pos)
#define HMATRIXB_SCFG_ARBT_FIXED_PRIORITY (HMATRIXB_SCFG_ARBT_FIXED_PRIORITY_Val << HMATRIXB_SCFG_ARBT_Pos)
#define HMATRIXB_SCFG_MASK _U_(0x013F00FF) /**< \brief (HMATRIXB_SCFG) MASK Register */
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t M0PR:4; /*!< bit: 0.. 3 Master 0 Priority */
uint32_t M1PR:4; /*!< bit: 4.. 7 Master 1 Priority */
uint32_t M2PR:4; /*!< bit: 8..11 Master 2 Priority */
uint32_t M3PR:4; /*!< bit: 12..15 Master 3 Priority */
uint32_t M4PR:4; /*!< bit: 16..19 Master 4 Priority */
uint32_t M5PR:4; /*!< bit: 20..23 Master 5 Priority */
uint32_t M6PR:4; /*!< bit: 24..27 Master 6 Priority */
uint32_t M7PR:4; /*!< bit: 28..31 Master 7 Priority */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRAS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
#define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
#define HMATRIXB_PRAS_M0PR_Pos 0 /**< \brief (HMATRIXB_PRAS) Master 0 Priority */
#define HMATRIXB_PRAS_M0PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M0PR_Pos)
#define HMATRIXB_PRAS_M0PR(value) (HMATRIXB_PRAS_M0PR_Msk & ((value) << HMATRIXB_PRAS_M0PR_Pos))
#define HMATRIXB_PRAS_M1PR_Pos 4 /**< \brief (HMATRIXB_PRAS) Master 1 Priority */
#define HMATRIXB_PRAS_M1PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M1PR_Pos)
#define HMATRIXB_PRAS_M1PR(value) (HMATRIXB_PRAS_M1PR_Msk & ((value) << HMATRIXB_PRAS_M1PR_Pos))
#define HMATRIXB_PRAS_M2PR_Pos 8 /**< \brief (HMATRIXB_PRAS) Master 2 Priority */
#define HMATRIXB_PRAS_M2PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M2PR_Pos)
#define HMATRIXB_PRAS_M2PR(value) (HMATRIXB_PRAS_M2PR_Msk & ((value) << HMATRIXB_PRAS_M2PR_Pos))
#define HMATRIXB_PRAS_M3PR_Pos 12 /**< \brief (HMATRIXB_PRAS) Master 3 Priority */
#define HMATRIXB_PRAS_M3PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M3PR_Pos)
#define HMATRIXB_PRAS_M3PR(value) (HMATRIXB_PRAS_M3PR_Msk & ((value) << HMATRIXB_PRAS_M3PR_Pos))
#define HMATRIXB_PRAS_M4PR_Pos 16 /**< \brief (HMATRIXB_PRAS) Master 4 Priority */
#define HMATRIXB_PRAS_M4PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M4PR_Pos)
#define HMATRIXB_PRAS_M4PR(value) (HMATRIXB_PRAS_M4PR_Msk & ((value) << HMATRIXB_PRAS_M4PR_Pos))
#define HMATRIXB_PRAS_M5PR_Pos 20 /**< \brief (HMATRIXB_PRAS) Master 5 Priority */
#define HMATRIXB_PRAS_M5PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M5PR_Pos)
#define HMATRIXB_PRAS_M5PR(value) (HMATRIXB_PRAS_M5PR_Msk & ((value) << HMATRIXB_PRAS_M5PR_Pos))
#define HMATRIXB_PRAS_M6PR_Pos 24 /**< \brief (HMATRIXB_PRAS) Master 6 Priority */
#define HMATRIXB_PRAS_M6PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M6PR_Pos)
#define HMATRIXB_PRAS_M6PR(value) (HMATRIXB_PRAS_M6PR_Msk & ((value) << HMATRIXB_PRAS_M6PR_Pos))
#define HMATRIXB_PRAS_M7PR_Pos 28 /**< \brief (HMATRIXB_PRAS) Master 7 Priority */
#define HMATRIXB_PRAS_M7PR_Msk (_U_(0xF) << HMATRIXB_PRAS_M7PR_Pos)
#define HMATRIXB_PRAS_M7PR(value) (HMATRIXB_PRAS_M7PR_Msk & ((value) << HMATRIXB_PRAS_M7PR_Pos))
#define HMATRIXB_PRAS_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_PRAS) MASK Register */
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t M8PR:4; /*!< bit: 0.. 3 Master 8 Priority */
uint32_t M9PR:4; /*!< bit: 4.. 7 Master 9 Priority */
uint32_t M10PR:4; /*!< bit: 8..11 Master 10 Priority */
uint32_t M11PR:4; /*!< bit: 12..15 Master 11 Priority */
uint32_t M12PR:4; /*!< bit: 16..19 Master 12 Priority */
uint32_t M13PR:4; /*!< bit: 20..23 Master 13 Priority */
uint32_t M14PR:4; /*!< bit: 24..27 Master 14 Priority */
uint32_t M15PR:4; /*!< bit: 28..31 Master 15 Priority */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRBS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
#define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
#define HMATRIXB_PRBS_M8PR_Pos 0 /**< \brief (HMATRIXB_PRBS) Master 8 Priority */
#define HMATRIXB_PRBS_M8PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M8PR_Pos)
#define HMATRIXB_PRBS_M8PR(value) (HMATRIXB_PRBS_M8PR_Msk & ((value) << HMATRIXB_PRBS_M8PR_Pos))
#define HMATRIXB_PRBS_M9PR_Pos 4 /**< \brief (HMATRIXB_PRBS) Master 9 Priority */
#define HMATRIXB_PRBS_M9PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M9PR_Pos)
#define HMATRIXB_PRBS_M9PR(value) (HMATRIXB_PRBS_M9PR_Msk & ((value) << HMATRIXB_PRBS_M9PR_Pos))
#define HMATRIXB_PRBS_M10PR_Pos 8 /**< \brief (HMATRIXB_PRBS) Master 10 Priority */
#define HMATRIXB_PRBS_M10PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M10PR_Pos)
#define HMATRIXB_PRBS_M10PR(value) (HMATRIXB_PRBS_M10PR_Msk & ((value) << HMATRIXB_PRBS_M10PR_Pos))
#define HMATRIXB_PRBS_M11PR_Pos 12 /**< \brief (HMATRIXB_PRBS) Master 11 Priority */
#define HMATRIXB_PRBS_M11PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M11PR_Pos)
#define HMATRIXB_PRBS_M11PR(value) (HMATRIXB_PRBS_M11PR_Msk & ((value) << HMATRIXB_PRBS_M11PR_Pos))
#define HMATRIXB_PRBS_M12PR_Pos 16 /**< \brief (HMATRIXB_PRBS) Master 12 Priority */
#define HMATRIXB_PRBS_M12PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M12PR_Pos)
#define HMATRIXB_PRBS_M12PR(value) (HMATRIXB_PRBS_M12PR_Msk & ((value) << HMATRIXB_PRBS_M12PR_Pos))
#define HMATRIXB_PRBS_M13PR_Pos 20 /**< \brief (HMATRIXB_PRBS) Master 13 Priority */
#define HMATRIXB_PRBS_M13PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M13PR_Pos)
#define HMATRIXB_PRBS_M13PR(value) (HMATRIXB_PRBS_M13PR_Msk & ((value) << HMATRIXB_PRBS_M13PR_Pos))
#define HMATRIXB_PRBS_M14PR_Pos 24 /**< \brief (HMATRIXB_PRBS) Master 14 Priority */
#define HMATRIXB_PRBS_M14PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M14PR_Pos)
#define HMATRIXB_PRBS_M14PR(value) (HMATRIXB_PRBS_M14PR_Msk & ((value) << HMATRIXB_PRBS_M14PR_Pos))
#define HMATRIXB_PRBS_M15PR_Pos 28 /**< \brief (HMATRIXB_PRBS) Master 15 Priority */
#define HMATRIXB_PRBS_M15PR_Msk (_U_(0xF) << HMATRIXB_PRBS_M15PR_Pos)
#define HMATRIXB_PRBS_M15PR(value) (HMATRIXB_PRBS_M15PR_Msk & ((value) << HMATRIXB_PRBS_M15PR_Pos))
#define HMATRIXB_PRBS_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_PRBS) MASK Register */
/* -------- HMATRIXB_MRCR : (HMATRIXB Offset: 0x100) (R/W 32) Master Remap Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RCB0:1; /*!< bit: 0 Remap Command Bit for Master 0 */
uint32_t RCB1:1; /*!< bit: 1 Remap Command Bit for Master 1 */
uint32_t RCB2:1; /*!< bit: 2 Remap Command Bit for Master 2 */
uint32_t RCB3:1; /*!< bit: 3 Remap Command Bit for Master 3 */
uint32_t RCB4:1; /*!< bit: 4 Remap Command Bit for Master 4 */
uint32_t RCB5:1; /*!< bit: 5 Remap Command Bit for Master 5 */
uint32_t RCB6:1; /*!< bit: 6 Remap Command Bit for Master 6 */
uint32_t RCB7:1; /*!< bit: 7 Remap Command Bit for Master 7 */
uint32_t RCB8:1; /*!< bit: 8 Remap Command Bit for Master 8 */
uint32_t RCB9:1; /*!< bit: 9 Remap Command Bit for Master 9 */
uint32_t RCB10:1; /*!< bit: 10 Remap Command Bit for Master 10 */
uint32_t RCB11:1; /*!< bit: 11 Remap Command Bit for Master 11 */
uint32_t RCB12:1; /*!< bit: 12 Remap Command Bit for Master 12 */
uint32_t RCB13:1; /*!< bit: 13 Remap Command Bit for Master 13 */
uint32_t RCB14:1; /*!< bit: 14 Remap Command Bit for Master 14 */
uint32_t RCB15:1; /*!< bit: 15 Remap Command Bit for Master 15 */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_MRCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define HMATRIXB_MRCR_OFFSET 0x100 /**< \brief (HMATRIXB_MRCR offset) Master Remap Control */
#define HMATRIXB_MRCR_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_MRCR reset_value) Master Remap Control */
#define HMATRIXB_MRCR_RCB0_Pos 0 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 0 */
#define HMATRIXB_MRCR_RCB0 (_U_(0x1) << HMATRIXB_MRCR_RCB0_Pos)
#define HMATRIXB_MRCR_RCB0_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB0_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB0_DIS (HMATRIXB_MRCR_RCB0_DIS_Val << HMATRIXB_MRCR_RCB0_Pos)
#define HMATRIXB_MRCR_RCB0_ENA (HMATRIXB_MRCR_RCB0_ENA_Val << HMATRIXB_MRCR_RCB0_Pos)
#define HMATRIXB_MRCR_RCB1_Pos 1 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 1 */
#define HMATRIXB_MRCR_RCB1 (_U_(0x1) << HMATRIXB_MRCR_RCB1_Pos)
#define HMATRIXB_MRCR_RCB1_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB1_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB1_DIS (HMATRIXB_MRCR_RCB1_DIS_Val << HMATRIXB_MRCR_RCB1_Pos)
#define HMATRIXB_MRCR_RCB1_ENA (HMATRIXB_MRCR_RCB1_ENA_Val << HMATRIXB_MRCR_RCB1_Pos)
#define HMATRIXB_MRCR_RCB2_Pos 2 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 2 */
#define HMATRIXB_MRCR_RCB2 (_U_(0x1) << HMATRIXB_MRCR_RCB2_Pos)
#define HMATRIXB_MRCR_RCB2_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB2_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB2_DIS (HMATRIXB_MRCR_RCB2_DIS_Val << HMATRIXB_MRCR_RCB2_Pos)
#define HMATRIXB_MRCR_RCB2_ENA (HMATRIXB_MRCR_RCB2_ENA_Val << HMATRIXB_MRCR_RCB2_Pos)
#define HMATRIXB_MRCR_RCB3_Pos 3 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 3 */
#define HMATRIXB_MRCR_RCB3 (_U_(0x1) << HMATRIXB_MRCR_RCB3_Pos)
#define HMATRIXB_MRCR_RCB3_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB3_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB3_DIS (HMATRIXB_MRCR_RCB3_DIS_Val << HMATRIXB_MRCR_RCB3_Pos)
#define HMATRIXB_MRCR_RCB3_ENA (HMATRIXB_MRCR_RCB3_ENA_Val << HMATRIXB_MRCR_RCB3_Pos)
#define HMATRIXB_MRCR_RCB4_Pos 4 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 4 */
#define HMATRIXB_MRCR_RCB4 (_U_(0x1) << HMATRIXB_MRCR_RCB4_Pos)
#define HMATRIXB_MRCR_RCB4_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB4_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB4_DIS (HMATRIXB_MRCR_RCB4_DIS_Val << HMATRIXB_MRCR_RCB4_Pos)
#define HMATRIXB_MRCR_RCB4_ENA (HMATRIXB_MRCR_RCB4_ENA_Val << HMATRIXB_MRCR_RCB4_Pos)
#define HMATRIXB_MRCR_RCB5_Pos 5 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 5 */
#define HMATRIXB_MRCR_RCB5 (_U_(0x1) << HMATRIXB_MRCR_RCB5_Pos)
#define HMATRIXB_MRCR_RCB5_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB5_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB5_DIS (HMATRIXB_MRCR_RCB5_DIS_Val << HMATRIXB_MRCR_RCB5_Pos)
#define HMATRIXB_MRCR_RCB5_ENA (HMATRIXB_MRCR_RCB5_ENA_Val << HMATRIXB_MRCR_RCB5_Pos)
#define HMATRIXB_MRCR_RCB6_Pos 6 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 6 */
#define HMATRIXB_MRCR_RCB6 (_U_(0x1) << HMATRIXB_MRCR_RCB6_Pos)
#define HMATRIXB_MRCR_RCB6_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB6_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB6_DIS (HMATRIXB_MRCR_RCB6_DIS_Val << HMATRIXB_MRCR_RCB6_Pos)
#define HMATRIXB_MRCR_RCB6_ENA (HMATRIXB_MRCR_RCB6_ENA_Val << HMATRIXB_MRCR_RCB6_Pos)
#define HMATRIXB_MRCR_RCB7_Pos 7 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 7 */
#define HMATRIXB_MRCR_RCB7 (_U_(0x1) << HMATRIXB_MRCR_RCB7_Pos)
#define HMATRIXB_MRCR_RCB7_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB7_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB7_DIS (HMATRIXB_MRCR_RCB7_DIS_Val << HMATRIXB_MRCR_RCB7_Pos)
#define HMATRIXB_MRCR_RCB7_ENA (HMATRIXB_MRCR_RCB7_ENA_Val << HMATRIXB_MRCR_RCB7_Pos)
#define HMATRIXB_MRCR_RCB8_Pos 8 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 8 */
#define HMATRIXB_MRCR_RCB8 (_U_(0x1) << HMATRIXB_MRCR_RCB8_Pos)
#define HMATRIXB_MRCR_RCB8_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB8_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB8_DIS (HMATRIXB_MRCR_RCB8_DIS_Val << HMATRIXB_MRCR_RCB8_Pos)
#define HMATRIXB_MRCR_RCB8_ENA (HMATRIXB_MRCR_RCB8_ENA_Val << HMATRIXB_MRCR_RCB8_Pos)
#define HMATRIXB_MRCR_RCB9_Pos 9 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 9 */
#define HMATRIXB_MRCR_RCB9 (_U_(0x1) << HMATRIXB_MRCR_RCB9_Pos)
#define HMATRIXB_MRCR_RCB9_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB9_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB9_DIS (HMATRIXB_MRCR_RCB9_DIS_Val << HMATRIXB_MRCR_RCB9_Pos)
#define HMATRIXB_MRCR_RCB9_ENA (HMATRIXB_MRCR_RCB9_ENA_Val << HMATRIXB_MRCR_RCB9_Pos)
#define HMATRIXB_MRCR_RCB10_Pos 10 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 10 */
#define HMATRIXB_MRCR_RCB10 (_U_(0x1) << HMATRIXB_MRCR_RCB10_Pos)
#define HMATRIXB_MRCR_RCB10_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB10_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB10_DIS (HMATRIXB_MRCR_RCB10_DIS_Val << HMATRIXB_MRCR_RCB10_Pos)
#define HMATRIXB_MRCR_RCB10_ENA (HMATRIXB_MRCR_RCB10_ENA_Val << HMATRIXB_MRCR_RCB10_Pos)
#define HMATRIXB_MRCR_RCB11_Pos 11 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 11 */
#define HMATRIXB_MRCR_RCB11 (_U_(0x1) << HMATRIXB_MRCR_RCB11_Pos)
#define HMATRIXB_MRCR_RCB11_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB11_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB11_DIS (HMATRIXB_MRCR_RCB11_DIS_Val << HMATRIXB_MRCR_RCB11_Pos)
#define HMATRIXB_MRCR_RCB11_ENA (HMATRIXB_MRCR_RCB11_ENA_Val << HMATRIXB_MRCR_RCB11_Pos)
#define HMATRIXB_MRCR_RCB12_Pos 12 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 12 */
#define HMATRIXB_MRCR_RCB12 (_U_(0x1) << HMATRIXB_MRCR_RCB12_Pos)
#define HMATRIXB_MRCR_RCB12_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB12_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB12_DIS (HMATRIXB_MRCR_RCB12_DIS_Val << HMATRIXB_MRCR_RCB12_Pos)
#define HMATRIXB_MRCR_RCB12_ENA (HMATRIXB_MRCR_RCB12_ENA_Val << HMATRIXB_MRCR_RCB12_Pos)
#define HMATRIXB_MRCR_RCB13_Pos 13 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 13 */
#define HMATRIXB_MRCR_RCB13 (_U_(0x1) << HMATRIXB_MRCR_RCB13_Pos)
#define HMATRIXB_MRCR_RCB13_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB13_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB13_DIS (HMATRIXB_MRCR_RCB13_DIS_Val << HMATRIXB_MRCR_RCB13_Pos)
#define HMATRIXB_MRCR_RCB13_ENA (HMATRIXB_MRCR_RCB13_ENA_Val << HMATRIXB_MRCR_RCB13_Pos)
#define HMATRIXB_MRCR_RCB14_Pos 14 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 14 */
#define HMATRIXB_MRCR_RCB14 (_U_(0x1) << HMATRIXB_MRCR_RCB14_Pos)
#define HMATRIXB_MRCR_RCB14_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB14_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB14_DIS (HMATRIXB_MRCR_RCB14_DIS_Val << HMATRIXB_MRCR_RCB14_Pos)
#define HMATRIXB_MRCR_RCB14_ENA (HMATRIXB_MRCR_RCB14_ENA_Val << HMATRIXB_MRCR_RCB14_Pos)
#define HMATRIXB_MRCR_RCB15_Pos 15 /**< \brief (HMATRIXB_MRCR) Remap Command Bit for Master 15 */
#define HMATRIXB_MRCR_RCB15 (_U_(0x1) << HMATRIXB_MRCR_RCB15_Pos)
#define HMATRIXB_MRCR_RCB15_DIS_Val _U_(0x0) /**< \brief (HMATRIXB_MRCR) Disable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB15_ENA_Val _U_(0x1) /**< \brief (HMATRIXB_MRCR) Enable remapped address decoding for master */
#define HMATRIXB_MRCR_RCB15_DIS (HMATRIXB_MRCR_RCB15_DIS_Val << HMATRIXB_MRCR_RCB15_Pos)
#define HMATRIXB_MRCR_RCB15_ENA (HMATRIXB_MRCR_RCB15_ENA_Val << HMATRIXB_MRCR_RCB15_Pos)
#define HMATRIXB_MRCR_MASK _U_(0x0000FFFF) /**< \brief (HMATRIXB_MRCR) MASK Register */
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_SFR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */
#define HMATRIXB_SFR_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_SFR reset_value) Special Function */
#define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */
#define HMATRIXB_SFR_SFR_Msk (_U_(0xFFFFFFFF) << HMATRIXB_SFR_SFR_Pos)
#define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
#define HMATRIXB_SFR_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_SFR) MASK Register */
/** \brief HmatrixbPrs hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
} HmatrixbPrs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief HMATRIXB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO HMATRIXB_MCFG_Type MCFG[16]; /**< \brief Offset: 0x000 (R/W 32) Master Configuration */
__IO HMATRIXB_SCFG_Type SCFG[16]; /**< \brief Offset: 0x040 (R/W 32) Slave Configuration */
HmatrixbPrs Prs[4]; /**< \brief Offset: 0x080 HmatrixbPrs groups [CLK_AHB_ID] */
RoReg8 Reserved1[0x60];
__IO HMATRIXB_MRCR_Type MRCR; /**< \brief Offset: 0x100 (R/W 32) Master Remap Control */
RoReg8 Reserved2[0xC];
__IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
} Hmatrixb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_HMATRIXB_COMPONENT_ */

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/**
* \file
*
* \brief Component description for MCLK
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_MCLK_COMPONENT_
#define _SAMC21_MCLK_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR MCLK */
/* ========================================================================== */
/** \addtogroup SAMC21_MCLK Main Clock */
/*@{*/
#define MCLK_U2234
#define REV_MCLK 0x200
/* -------- MCLK_INTENCLR : (MCLK Offset: 0x01) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} MCLK_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_INTENCLR_OFFSET 0x01 /**< \brief (MCLK_INTENCLR offset) Interrupt Enable Clear */
#define MCLK_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENCLR reset_value) Interrupt Enable Clear */
#define MCLK_INTENCLR_CKRDY_Pos 0 /**< \brief (MCLK_INTENCLR) Clock Ready Interrupt Enable */
#define MCLK_INTENCLR_CKRDY (_U_(0x1) << MCLK_INTENCLR_CKRDY_Pos)
#define MCLK_INTENCLR_MASK _U_(0x01) /**< \brief (MCLK_INTENCLR) MASK Register */
/* -------- MCLK_INTENSET : (MCLK Offset: 0x02) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} MCLK_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_INTENSET_OFFSET 0x02 /**< \brief (MCLK_INTENSET offset) Interrupt Enable Set */
#define MCLK_INTENSET_RESETVALUE _U_(0x00) /**< \brief (MCLK_INTENSET reset_value) Interrupt Enable Set */
#define MCLK_INTENSET_CKRDY_Pos 0 /**< \brief (MCLK_INTENSET) Clock Ready Interrupt Enable */
#define MCLK_INTENSET_CKRDY (_U_(0x1) << MCLK_INTENSET_CKRDY_Pos)
#define MCLK_INTENSET_MASK _U_(0x01) /**< \brief (MCLK_INTENSET) MASK Register */
/* -------- MCLK_INTFLAG : (MCLK Offset: 0x03) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} MCLK_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_INTFLAG_OFFSET 0x03 /**< \brief (MCLK_INTFLAG offset) Interrupt Flag Status and Clear */
#define MCLK_INTFLAG_RESETVALUE _U_(0x01) /**< \brief (MCLK_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define MCLK_INTFLAG_CKRDY_Pos 0 /**< \brief (MCLK_INTFLAG) Clock Ready */
#define MCLK_INTFLAG_CKRDY (_U_(0x1) << MCLK_INTFLAG_CKRDY_Pos)
#define MCLK_INTFLAG_MASK _U_(0x01) /**< \brief (MCLK_INTFLAG) MASK Register */
/* -------- MCLK_CPUDIV : (MCLK Offset: 0x04) (R/W 8) CPU Clock Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CPUDIV:8; /*!< bit: 0.. 7 CPU Clock Division Factor */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} MCLK_CPUDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_CPUDIV_OFFSET 0x04 /**< \brief (MCLK_CPUDIV offset) CPU Clock Division */
#define MCLK_CPUDIV_RESETVALUE _U_(0x01) /**< \brief (MCLK_CPUDIV reset_value) CPU Clock Division */
#define MCLK_CPUDIV_CPUDIV_Pos 0 /**< \brief (MCLK_CPUDIV) CPU Clock Division Factor */
#define MCLK_CPUDIV_CPUDIV_Msk (_U_(0xFF) << MCLK_CPUDIV_CPUDIV_Pos)
#define MCLK_CPUDIV_CPUDIV(value) (MCLK_CPUDIV_CPUDIV_Msk & ((value) << MCLK_CPUDIV_CPUDIV_Pos))
#define MCLK_CPUDIV_CPUDIV_DIV1_Val _U_(0x1) /**< \brief (MCLK_CPUDIV) Divide by 1 */
#define MCLK_CPUDIV_CPUDIV_DIV2_Val _U_(0x2) /**< \brief (MCLK_CPUDIV) Divide by 2 */
#define MCLK_CPUDIV_CPUDIV_DIV4_Val _U_(0x4) /**< \brief (MCLK_CPUDIV) Divide by 4 */
#define MCLK_CPUDIV_CPUDIV_DIV8_Val _U_(0x8) /**< \brief (MCLK_CPUDIV) Divide by 8 */
#define MCLK_CPUDIV_CPUDIV_DIV16_Val _U_(0x10) /**< \brief (MCLK_CPUDIV) Divide by 16 */
#define MCLK_CPUDIV_CPUDIV_DIV32_Val _U_(0x20) /**< \brief (MCLK_CPUDIV) Divide by 32 */
#define MCLK_CPUDIV_CPUDIV_DIV64_Val _U_(0x40) /**< \brief (MCLK_CPUDIV) Divide by 64 */
#define MCLK_CPUDIV_CPUDIV_DIV128_Val _U_(0x80) /**< \brief (MCLK_CPUDIV) Divide by 128 */
#define MCLK_CPUDIV_CPUDIV_DIV1 (MCLK_CPUDIV_CPUDIV_DIV1_Val << MCLK_CPUDIV_CPUDIV_Pos)
#define MCLK_CPUDIV_CPUDIV_DIV2 (MCLK_CPUDIV_CPUDIV_DIV2_Val << MCLK_CPUDIV_CPUDIV_Pos)
#define MCLK_CPUDIV_CPUDIV_DIV4 (MCLK_CPUDIV_CPUDIV_DIV4_Val << MCLK_CPUDIV_CPUDIV_Pos)
#define MCLK_CPUDIV_CPUDIV_DIV8 (MCLK_CPUDIV_CPUDIV_DIV8_Val << MCLK_CPUDIV_CPUDIV_Pos)
#define MCLK_CPUDIV_CPUDIV_DIV16 (MCLK_CPUDIV_CPUDIV_DIV16_Val << MCLK_CPUDIV_CPUDIV_Pos)
#define MCLK_CPUDIV_CPUDIV_DIV32 (MCLK_CPUDIV_CPUDIV_DIV32_Val << MCLK_CPUDIV_CPUDIV_Pos)
#define MCLK_CPUDIV_CPUDIV_DIV64 (MCLK_CPUDIV_CPUDIV_DIV64_Val << MCLK_CPUDIV_CPUDIV_Pos)
#define MCLK_CPUDIV_CPUDIV_DIV128 (MCLK_CPUDIV_CPUDIV_DIV128_Val << MCLK_CPUDIV_CPUDIV_Pos)
#define MCLK_CPUDIV_MASK _U_(0xFF) /**< \brief (MCLK_CPUDIV) MASK Register */
/* -------- MCLK_AHBMASK : (MCLK Offset: 0x10) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
uint32_t HMATRIXHS_:1; /*!< bit: 4 HMATRIXHS AHB Clock Mask */
uint32_t NVMCTRL_:1; /*!< bit: 5 NVMCTRL AHB Clock Mask */
uint32_t HSRAM_:1; /*!< bit: 6 HSRAM AHB Clock Mask */
uint32_t DMAC_:1; /*!< bit: 7 DMAC AHB Clock Mask */
uint32_t CAN0_:1; /*!< bit: 8 CAN0 AHB Clock Mask */
uint32_t CAN1_:1; /*!< bit: 9 CAN1 AHB Clock Mask */
uint32_t PAC_:1; /*!< bit: 10 PAC AHB Clock Mask */
uint32_t NVMCTRL_PICACHU_:1; /*!< bit: 11 NVMCTRL_PICACHU AHB Clock Mask */
uint32_t DIVAS_:1; /*!< bit: 12 DIVAS AHB Clock Mask */
uint32_t :19; /*!< bit: 13..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MCLK_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_AHBMASK_OFFSET 0x10 /**< \brief (MCLK_AHBMASK offset) AHB Mask */
#define MCLK_AHBMASK_RESETVALUE _U_(0x00001CFF) /**< \brief (MCLK_AHBMASK reset_value) AHB Mask */
#define MCLK_AHBMASK_HPB0_Pos 0 /**< \brief (MCLK_AHBMASK) HPB0 AHB Clock Mask */
#define MCLK_AHBMASK_HPB0 (_U_(0x1) << MCLK_AHBMASK_HPB0_Pos)
#define MCLK_AHBMASK_HPB1_Pos 1 /**< \brief (MCLK_AHBMASK) HPB1 AHB Clock Mask */
#define MCLK_AHBMASK_HPB1 (_U_(0x1) << MCLK_AHBMASK_HPB1_Pos)
#define MCLK_AHBMASK_HPB2_Pos 2 /**< \brief (MCLK_AHBMASK) HPB2 AHB Clock Mask */
#define MCLK_AHBMASK_HPB2 (_U_(0x1) << MCLK_AHBMASK_HPB2_Pos)
#define MCLK_AHBMASK_DSU_Pos 3 /**< \brief (MCLK_AHBMASK) DSU AHB Clock Mask */
#define MCLK_AHBMASK_DSU (_U_(0x1) << MCLK_AHBMASK_DSU_Pos)
#define MCLK_AHBMASK_HMATRIXHS_Pos 4 /**< \brief (MCLK_AHBMASK) HMATRIXHS AHB Clock Mask */
#define MCLK_AHBMASK_HMATRIXHS (_U_(0x1) << MCLK_AHBMASK_HMATRIXHS_Pos)
#define MCLK_AHBMASK_NVMCTRL_Pos 5 /**< \brief (MCLK_AHBMASK) NVMCTRL AHB Clock Mask */
#define MCLK_AHBMASK_NVMCTRL (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_Pos)
#define MCLK_AHBMASK_HSRAM_Pos 6 /**< \brief (MCLK_AHBMASK) HSRAM AHB Clock Mask */
#define MCLK_AHBMASK_HSRAM (_U_(0x1) << MCLK_AHBMASK_HSRAM_Pos)
#define MCLK_AHBMASK_DMAC_Pos 7 /**< \brief (MCLK_AHBMASK) DMAC AHB Clock Mask */
#define MCLK_AHBMASK_DMAC (_U_(0x1) << MCLK_AHBMASK_DMAC_Pos)
#define MCLK_AHBMASK_CAN0_Pos 8 /**< \brief (MCLK_AHBMASK) CAN0 AHB Clock Mask */
#define MCLK_AHBMASK_CAN0 (_U_(0x1) << MCLK_AHBMASK_CAN0_Pos)
#define MCLK_AHBMASK_CAN1_Pos 9 /**< \brief (MCLK_AHBMASK) CAN1 AHB Clock Mask */
#define MCLK_AHBMASK_CAN1 (_U_(0x1) << MCLK_AHBMASK_CAN1_Pos)
#define MCLK_AHBMASK_PAC_Pos 10 /**< \brief (MCLK_AHBMASK) PAC AHB Clock Mask */
#define MCLK_AHBMASK_PAC (_U_(0x1) << MCLK_AHBMASK_PAC_Pos)
#define MCLK_AHBMASK_NVMCTRL_PICACHU_Pos 11 /**< \brief (MCLK_AHBMASK) NVMCTRL_PICACHU AHB Clock Mask */
#define MCLK_AHBMASK_NVMCTRL_PICACHU (_U_(0x1) << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos)
#define MCLK_AHBMASK_DIVAS_Pos 12 /**< \brief (MCLK_AHBMASK) DIVAS AHB Clock Mask */
#define MCLK_AHBMASK_DIVAS (_U_(0x1) << MCLK_AHBMASK_DIVAS_Pos)
#define MCLK_AHBMASK_MASK _U_(0x00001FFF) /**< \brief (MCLK_AHBMASK) MASK Register */
/* -------- MCLK_APBAMASK : (MCLK Offset: 0x14) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC_:1; /*!< bit: 0 PAC APB Clock Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Clock Enable */
uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Clock Enable */
uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Clock Enable */
uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Clock Enable */
uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Clock Enable */
uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Clock Enable */
uint32_t WDT_:1; /*!< bit: 8 WDT APB Clock Enable */
uint32_t RTC_:1; /*!< bit: 9 RTC APB Clock Enable */
uint32_t EIC_:1; /*!< bit: 10 EIC APB Clock Enable */
uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Clock Enable */
uint32_t TSENS_:1; /*!< bit: 12 TSENS APB Clock Enable */
uint32_t :19; /*!< bit: 13..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MCLK_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_APBAMASK_OFFSET 0x14 /**< \brief (MCLK_APBAMASK offset) APBA Mask */
#define MCLK_APBAMASK_RESETVALUE _U_(0x00000FFF) /**< \brief (MCLK_APBAMASK reset_value) APBA Mask */
#define MCLK_APBAMASK_PAC_Pos 0 /**< \brief (MCLK_APBAMASK) PAC APB Clock Enable */
#define MCLK_APBAMASK_PAC (_U_(0x1) << MCLK_APBAMASK_PAC_Pos)
#define MCLK_APBAMASK_PM_Pos 1 /**< \brief (MCLK_APBAMASK) PM APB Clock Enable */
#define MCLK_APBAMASK_PM (_U_(0x1) << MCLK_APBAMASK_PM_Pos)
#define MCLK_APBAMASK_MCLK_Pos 2 /**< \brief (MCLK_APBAMASK) MCLK APB Clock Enable */
#define MCLK_APBAMASK_MCLK (_U_(0x1) << MCLK_APBAMASK_MCLK_Pos)
#define MCLK_APBAMASK_RSTC_Pos 3 /**< \brief (MCLK_APBAMASK) RSTC APB Clock Enable */
#define MCLK_APBAMASK_RSTC (_U_(0x1) << MCLK_APBAMASK_RSTC_Pos)
#define MCLK_APBAMASK_OSCCTRL_Pos 4 /**< \brief (MCLK_APBAMASK) OSCCTRL APB Clock Enable */
#define MCLK_APBAMASK_OSCCTRL (_U_(0x1) << MCLK_APBAMASK_OSCCTRL_Pos)
#define MCLK_APBAMASK_OSC32KCTRL_Pos 5 /**< \brief (MCLK_APBAMASK) OSC32KCTRL APB Clock Enable */
#define MCLK_APBAMASK_OSC32KCTRL (_U_(0x1) << MCLK_APBAMASK_OSC32KCTRL_Pos)
#define MCLK_APBAMASK_SUPC_Pos 6 /**< \brief (MCLK_APBAMASK) SUPC APB Clock Enable */
#define MCLK_APBAMASK_SUPC (_U_(0x1) << MCLK_APBAMASK_SUPC_Pos)
#define MCLK_APBAMASK_GCLK_Pos 7 /**< \brief (MCLK_APBAMASK) GCLK APB Clock Enable */
#define MCLK_APBAMASK_GCLK (_U_(0x1) << MCLK_APBAMASK_GCLK_Pos)
#define MCLK_APBAMASK_WDT_Pos 8 /**< \brief (MCLK_APBAMASK) WDT APB Clock Enable */
#define MCLK_APBAMASK_WDT (_U_(0x1) << MCLK_APBAMASK_WDT_Pos)
#define MCLK_APBAMASK_RTC_Pos 9 /**< \brief (MCLK_APBAMASK) RTC APB Clock Enable */
#define MCLK_APBAMASK_RTC (_U_(0x1) << MCLK_APBAMASK_RTC_Pos)
#define MCLK_APBAMASK_EIC_Pos 10 /**< \brief (MCLK_APBAMASK) EIC APB Clock Enable */
#define MCLK_APBAMASK_EIC (_U_(0x1) << MCLK_APBAMASK_EIC_Pos)
#define MCLK_APBAMASK_FREQM_Pos 11 /**< \brief (MCLK_APBAMASK) FREQM APB Clock Enable */
#define MCLK_APBAMASK_FREQM (_U_(0x1) << MCLK_APBAMASK_FREQM_Pos)
#define MCLK_APBAMASK_TSENS_Pos 12 /**< \brief (MCLK_APBAMASK) TSENS APB Clock Enable */
#define MCLK_APBAMASK_TSENS (_U_(0x1) << MCLK_APBAMASK_TSENS_Pos)
#define MCLK_APBAMASK_MASK _U_(0x00001FFF) /**< \brief (MCLK_APBAMASK) MASK Register */
/* -------- MCLK_APBBMASK : (MCLK Offset: 0x18) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PORT_:1; /*!< bit: 0 PORT APB Clock Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
uint32_t :2; /*!< bit: 3.. 4 Reserved */
uint32_t HMATRIXHS_:1; /*!< bit: 5 HMATRIXHS APB Clock Enable */
uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MCLK_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_APBBMASK_OFFSET 0x18 /**< \brief (MCLK_APBBMASK offset) APBB Mask */
#define MCLK_APBBMASK_RESETVALUE _U_(0x00000007) /**< \brief (MCLK_APBBMASK reset_value) APBB Mask */
#define MCLK_APBBMASK_PORT_Pos 0 /**< \brief (MCLK_APBBMASK) PORT APB Clock Enable */
#define MCLK_APBBMASK_PORT (_U_(0x1) << MCLK_APBBMASK_PORT_Pos)
#define MCLK_APBBMASK_DSU_Pos 1 /**< \brief (MCLK_APBBMASK) DSU APB Clock Enable */
#define MCLK_APBBMASK_DSU (_U_(0x1) << MCLK_APBBMASK_DSU_Pos)
#define MCLK_APBBMASK_NVMCTRL_Pos 2 /**< \brief (MCLK_APBBMASK) NVMCTRL APB Clock Enable */
#define MCLK_APBBMASK_NVMCTRL (_U_(0x1) << MCLK_APBBMASK_NVMCTRL_Pos)
#define MCLK_APBBMASK_HMATRIXHS_Pos 5 /**< \brief (MCLK_APBBMASK) HMATRIXHS APB Clock Enable */
#define MCLK_APBBMASK_HMATRIXHS (_U_(0x1) << MCLK_APBBMASK_HMATRIXHS_Pos)
#define MCLK_APBBMASK_MASK _U_(0x00000027) /**< \brief (MCLK_APBBMASK) MASK Register */
/* -------- MCLK_APBCMASK : (MCLK Offset: 0x1C) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Clock Enable */
uint32_t SERCOM0_:1; /*!< bit: 1 SERCOM0 APB Clock Enable */
uint32_t SERCOM1_:1; /*!< bit: 2 SERCOM1 APB Clock Enable */
uint32_t SERCOM2_:1; /*!< bit: 3 SERCOM2 APB Clock Enable */
uint32_t SERCOM3_:1; /*!< bit: 4 SERCOM3 APB Clock Enable */
uint32_t SERCOM4_:1; /*!< bit: 5 SERCOM4 APB Clock Enable */
uint32_t SERCOM5_:1; /*!< bit: 6 SERCOM5 APB Clock Enable */
uint32_t :2; /*!< bit: 7.. 8 Reserved */
uint32_t TCC0_:1; /*!< bit: 9 TCC0 APB Clock Enable */
uint32_t TCC1_:1; /*!< bit: 10 TCC1 APB Clock Enable */
uint32_t TCC2_:1; /*!< bit: 11 TCC2 APB Clock Enable */
uint32_t TC0_:1; /*!< bit: 12 TC0 APB Clock Enable */
uint32_t TC1_:1; /*!< bit: 13 TC1 APB Clock Enable */
uint32_t TC2_:1; /*!< bit: 14 TC2 APB Clock Enable */
uint32_t TC3_:1; /*!< bit: 15 TC3 APB Clock Enable */
uint32_t TC4_:1; /*!< bit: 16 TC4 APB Clock Enable */
uint32_t ADC0_:1; /*!< bit: 17 ADC0 APB Clock Enable */
uint32_t ADC1_:1; /*!< bit: 18 ADC1 APB Clock Enable */
uint32_t SDADC_:1; /*!< bit: 19 SDADC APB Clock Enable */
uint32_t AC_:1; /*!< bit: 20 AC APB Clock Enable */
uint32_t DAC_:1; /*!< bit: 21 DAC APB Clock Enable */
uint32_t PTC_:1; /*!< bit: 22 PTC APB Clock Enable */
uint32_t CCL_:1; /*!< bit: 23 CCL APB Clock Enable */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MCLK_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MCLK_APBCMASK_OFFSET 0x1C /**< \brief (MCLK_APBCMASK offset) APBC Mask */
#define MCLK_APBCMASK_RESETVALUE _U_(0x00000000) /**< \brief (MCLK_APBCMASK reset_value) APBC Mask */
#define MCLK_APBCMASK_EVSYS_Pos 0 /**< \brief (MCLK_APBCMASK) EVSYS APB Clock Enable */
#define MCLK_APBCMASK_EVSYS (_U_(0x1) << MCLK_APBCMASK_EVSYS_Pos)
#define MCLK_APBCMASK_SERCOM0_Pos 1 /**< \brief (MCLK_APBCMASK) SERCOM0 APB Clock Enable */
#define MCLK_APBCMASK_SERCOM0 (_U_(0x1) << MCLK_APBCMASK_SERCOM0_Pos)
#define MCLK_APBCMASK_SERCOM1_Pos 2 /**< \brief (MCLK_APBCMASK) SERCOM1 APB Clock Enable */
#define MCLK_APBCMASK_SERCOM1 (_U_(0x1) << MCLK_APBCMASK_SERCOM1_Pos)
#define MCLK_APBCMASK_SERCOM2_Pos 3 /**< \brief (MCLK_APBCMASK) SERCOM2 APB Clock Enable */
#define MCLK_APBCMASK_SERCOM2 (_U_(0x1) << MCLK_APBCMASK_SERCOM2_Pos)
#define MCLK_APBCMASK_SERCOM3_Pos 4 /**< \brief (MCLK_APBCMASK) SERCOM3 APB Clock Enable */
#define MCLK_APBCMASK_SERCOM3 (_U_(0x1) << MCLK_APBCMASK_SERCOM3_Pos)
#define MCLK_APBCMASK_SERCOM4_Pos 5 /**< \brief (MCLK_APBCMASK) SERCOM4 APB Clock Enable */
#define MCLK_APBCMASK_SERCOM4 (_U_(0x1) << MCLK_APBCMASK_SERCOM4_Pos)
#define MCLK_APBCMASK_SERCOM5_Pos 6 /**< \brief (MCLK_APBCMASK) SERCOM5 APB Clock Enable */
#define MCLK_APBCMASK_SERCOM5 (_U_(0x1) << MCLK_APBCMASK_SERCOM5_Pos)
#define MCLK_APBCMASK_TCC0_Pos 9 /**< \brief (MCLK_APBCMASK) TCC0 APB Clock Enable */
#define MCLK_APBCMASK_TCC0 (_U_(0x1) << MCLK_APBCMASK_TCC0_Pos)
#define MCLK_APBCMASK_TCC1_Pos 10 /**< \brief (MCLK_APBCMASK) TCC1 APB Clock Enable */
#define MCLK_APBCMASK_TCC1 (_U_(0x1) << MCLK_APBCMASK_TCC1_Pos)
#define MCLK_APBCMASK_TCC2_Pos 11 /**< \brief (MCLK_APBCMASK) TCC2 APB Clock Enable */
#define MCLK_APBCMASK_TCC2 (_U_(0x1) << MCLK_APBCMASK_TCC2_Pos)
#define MCLK_APBCMASK_TC0_Pos 12 /**< \brief (MCLK_APBCMASK) TC0 APB Clock Enable */
#define MCLK_APBCMASK_TC0 (_U_(0x1) << MCLK_APBCMASK_TC0_Pos)
#define MCLK_APBCMASK_TC1_Pos 13 /**< \brief (MCLK_APBCMASK) TC1 APB Clock Enable */
#define MCLK_APBCMASK_TC1 (_U_(0x1) << MCLK_APBCMASK_TC1_Pos)
#define MCLK_APBCMASK_TC2_Pos 14 /**< \brief (MCLK_APBCMASK) TC2 APB Clock Enable */
#define MCLK_APBCMASK_TC2 (_U_(0x1) << MCLK_APBCMASK_TC2_Pos)
#define MCLK_APBCMASK_TC3_Pos 15 /**< \brief (MCLK_APBCMASK) TC3 APB Clock Enable */
#define MCLK_APBCMASK_TC3 (_U_(0x1) << MCLK_APBCMASK_TC3_Pos)
#define MCLK_APBCMASK_TC4_Pos 16 /**< \brief (MCLK_APBCMASK) TC4 APB Clock Enable */
#define MCLK_APBCMASK_TC4 (_U_(0x1) << MCLK_APBCMASK_TC4_Pos)
#define MCLK_APBCMASK_ADC0_Pos 17 /**< \brief (MCLK_APBCMASK) ADC0 APB Clock Enable */
#define MCLK_APBCMASK_ADC0 (_U_(0x1) << MCLK_APBCMASK_ADC0_Pos)
#define MCLK_APBCMASK_ADC1_Pos 18 /**< \brief (MCLK_APBCMASK) ADC1 APB Clock Enable */
#define MCLK_APBCMASK_ADC1 (_U_(0x1) << MCLK_APBCMASK_ADC1_Pos)
#define MCLK_APBCMASK_SDADC_Pos 19 /**< \brief (MCLK_APBCMASK) SDADC APB Clock Enable */
#define MCLK_APBCMASK_SDADC (_U_(0x1) << MCLK_APBCMASK_SDADC_Pos)
#define MCLK_APBCMASK_AC_Pos 20 /**< \brief (MCLK_APBCMASK) AC APB Clock Enable */
#define MCLK_APBCMASK_AC (_U_(0x1) << MCLK_APBCMASK_AC_Pos)
#define MCLK_APBCMASK_DAC_Pos 21 /**< \brief (MCLK_APBCMASK) DAC APB Clock Enable */
#define MCLK_APBCMASK_DAC (_U_(0x1) << MCLK_APBCMASK_DAC_Pos)
#define MCLK_APBCMASK_PTC_Pos 22 /**< \brief (MCLK_APBCMASK) PTC APB Clock Enable */
#define MCLK_APBCMASK_PTC (_U_(0x1) << MCLK_APBCMASK_PTC_Pos)
#define MCLK_APBCMASK_CCL_Pos 23 /**< \brief (MCLK_APBCMASK) CCL APB Clock Enable */
#define MCLK_APBCMASK_CCL (_U_(0x1) << MCLK_APBCMASK_CCL_Pos)
#define MCLK_APBCMASK_MASK _U_(0x00FFFE7F) /**< \brief (MCLK_APBCMASK) MASK Register */
/** \brief MCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
RoReg8 Reserved1[0x1];
__IO MCLK_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x01 (R/W 8) Interrupt Enable Clear */
__IO MCLK_INTENSET_Type INTENSET; /**< \brief Offset: 0x02 (R/W 8) Interrupt Enable Set */
__IO MCLK_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x03 (R/W 8) Interrupt Flag Status and Clear */
__IO MCLK_CPUDIV_Type CPUDIV; /**< \brief Offset: 0x04 (R/W 8) CPU Clock Division */
RoReg8 Reserved2[0xB];
__IO MCLK_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x10 (R/W 32) AHB Mask */
__IO MCLK_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x14 (R/W 32) APBA Mask */
__IO MCLK_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x18 (R/W 32) APBB Mask */
__IO MCLK_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x1C (R/W 32) APBC Mask */
} Mclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_MCLK_COMPONENT_ */

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/**
* \file
*
* \brief Component description for MTB
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_MTB_COMPONENT_
#define _SAMC21_MTB_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR MTB */
/* ========================================================================== */
/** \addtogroup SAMC21_MTB Cortex-M0+ Micro-Trace Buffer */
/*@{*/
#define MTB_U2002
#define REV_MTB 0x100
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_POSITION_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
#define MTB_POSITION_WRAP (_U_(0x1) << MTB_POSITION_WRAP_Pos)
#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
#define MTB_POSITION_POINTER_Msk (_U_(0x1FFFFFFF) << MTB_POSITION_POINTER_Pos)
#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
#define MTB_POSITION_MASK _U_(0xFFFFFFFC) /**< \brief (MTB_POSITION) MASK Register */
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
uint32_t :21; /*!< bit: 10..30 Reserved */
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_MASTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
#define MTB_MASTER_RESETVALUE _U_(0x00000000) /**< \brief (MTB_MASTER reset_value) MTB Master */
#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
#define MTB_MASTER_MASK_Msk (_U_(0x1F) << MTB_MASTER_MASK_Pos)
#define MTB_MASTER_MASK(value) (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
#define MTB_MASTER_TSTARTEN (_U_(0x1) << MTB_MASTER_TSTARTEN_Pos)
#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
#define MTB_MASTER_TSTOPEN (_U_(0x1) << MTB_MASTER_TSTOPEN_Pos)
#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
#define MTB_MASTER_SFRWPRIV (_U_(0x1) << MTB_MASTER_SFRWPRIV_Pos)
#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
#define MTB_MASTER_RAMPRIV (_U_(0x1) << MTB_MASTER_RAMPRIV_Pos)
#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
#define MTB_MASTER_HALTREQ (_U_(0x1) << MTB_MASTER_HALTREQ_Pos)
#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
#define MTB_MASTER_EN (_U_(0x1) << MTB_MASTER_EN_Pos)
#define MTB_MASTER_MASK_ _U_(0x800003FF) /**< \brief (MTB_MASTER) MASK Register */
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
uint32_t :1; /*!< bit: 2 Reserved */
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_FLOW_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
#define MTB_FLOW_RESETVALUE _U_(0x00000000) /**< \brief (MTB_FLOW reset_value) MTB Flow */
#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
#define MTB_FLOW_AUTOSTOP (_U_(0x1) << MTB_FLOW_AUTOSTOP_Pos)
#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
#define MTB_FLOW_AUTOHALT (_U_(0x1) << MTB_FLOW_AUTOHALT_Pos)
#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
#define MTB_FLOW_WATERMARK_Msk (_U_(0x1FFFFFFF) << MTB_FLOW_WATERMARK_Pos)
#define MTB_FLOW_WATERMARK(value) (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
#define MTB_FLOW_MASK _U_(0xFFFFFFFB) /**< \brief (MTB_FLOW) MASK Register */
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_BASE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
#define MTB_BASE_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_BASE) MASK Register */
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_ITCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
#define MTB_ITCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_ITCTRL) MASK Register */
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
#define MTB_CLAIMSET_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CLAIMSET) MASK Register */
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
#define MTB_CLAIMCLR_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CLAIMCLR) MASK Register */
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKACCESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
#define MTB_LOCKACCESS_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_LOCKACCESS) MASK Register */
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
#define MTB_LOCKSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_LOCKSTATUS) MASK Register */
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_AUTHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
#define MTB_AUTHSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_AUTHSTATUS) MASK Register */
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_DEVARCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
#define MTB_DEVARCH_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_DEVARCH) MASK Register */
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_DEVID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
#define MTB_DEVID_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_DEVID) MASK Register */
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_DEVTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
#define MTB_DEVTYPE_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_DEVTYPE) MASK Register */
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) Peripheral Identification 4 */
#define MTB_PID4_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID4) MASK Register */
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) Peripheral Identification 5 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) Peripheral Identification 5 */
#define MTB_PID5_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID5) MASK Register */
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) Peripheral Identification 6 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) Peripheral Identification 6 */
#define MTB_PID6_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID6) MASK Register */
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) Peripheral Identification 7 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) Peripheral Identification 7 */
#define MTB_PID7_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID7) MASK Register */
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) Peripheral Identification 0 */
#define MTB_PID0_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID0) MASK Register */
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) Peripheral Identification 1 */
#define MTB_PID1_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID1) MASK Register */
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) Peripheral Identification 2 */
#define MTB_PID2_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID2) MASK Register */
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) Peripheral Identification 3 */
#define MTB_PID3_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID3) MASK Register */
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) Component Identification 0 */
#define MTB_CID0_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID0) MASK Register */
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) Component Identification 1 */
#define MTB_CID1_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID1) MASK Register */
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) Component Identification 2 */
#define MTB_CID2_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID2) MASK Register */
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} MTB_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) Component Identification 3 */
#define MTB_CID3_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID3) MASK Register */
/** \brief MTB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
RoReg8 Reserved1[0xEF0];
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
RoReg8 Reserved2[0x9C];
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
RoReg8 Reserved3[0x8];
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
RoReg8 Reserved4[0x8];
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) Peripheral Identification 4 */
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) Peripheral Identification 5 */
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) Peripheral Identification 6 */
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) Peripheral Identification 7 */
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) Peripheral Identification 0 */
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) Peripheral Identification 1 */
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) Peripheral Identification 2 */
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) Peripheral Identification 3 */
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) Component Identification 0 */
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) Component Identification 1 */
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) Component Identification 2 */
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) Component Identification 3 */
} Mtb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_MTB_COMPONENT_ */

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/**
* \file
*
* \brief Component description for NVMCTRL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_NVMCTRL_COMPONENT_
#define _SAMC21_NVMCTRL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR NVMCTRL */
/* ========================================================================== */
/** \addtogroup SAMC21_NVMCTRL Non-Volatile Memory Controller */
/*@{*/
#define NVMCTRL_U2207
#define REV_NVMCTRL 0x401
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CMD:7; /*!< bit: 0.. 6 Command */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_CTRLA_OFFSET 0x00 /**< \brief (NVMCTRL_CTRLA offset) Control A */
#define NVMCTRL_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_CTRLA reset_value) Control A */
#define NVMCTRL_CTRLA_CMD_Pos 0 /**< \brief (NVMCTRL_CTRLA) Command */
#define NVMCTRL_CTRLA_CMD_Msk (_U_(0x7F) << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD(value) (NVMCTRL_CTRLA_CMD_Msk & ((value) << NVMCTRL_CTRLA_CMD_Pos))
#define NVMCTRL_CTRLA_CMD_ER_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLA) Erase Row - Erases the row addressed by the ADDR register. */
#define NVMCTRL_CTRLA_CMD_WP_Val _U_(0x4) /**< \brief (NVMCTRL_CTRLA) Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
#define NVMCTRL_CTRLA_CMD_EAR_Val _U_(0x5) /**< \brief (NVMCTRL_CTRLA) Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
#define NVMCTRL_CTRLA_CMD_WAP_Val _U_(0x6) /**< \brief (NVMCTRL_CTRLA) Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. */
#define NVMCTRL_CTRLA_CMD_SF_Val _U_(0xA) /**< \brief (NVMCTRL_CTRLA) Security Flow Command */
#define NVMCTRL_CTRLA_CMD_WL_Val _U_(0xF) /**< \brief (NVMCTRL_CTRLA) Write lockbits */
#define NVMCTRL_CTRLA_CMD_RWWEEER_Val _U_(0x1A) /**< \brief (NVMCTRL_CTRLA) RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. */
#define NVMCTRL_CTRLA_CMD_RWWEEWP_Val _U_(0x1C) /**< \brief (NVMCTRL_CTRLA) RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. */
#define NVMCTRL_CTRLA_CMD_LR_Val _U_(0x40) /**< \brief (NVMCTRL_CTRLA) Lock Region - Locks the region containing the address location in the ADDR register. */
#define NVMCTRL_CTRLA_CMD_UR_Val _U_(0x41) /**< \brief (NVMCTRL_CTRLA) Unlock Region - Unlocks the region containing the address location in the ADDR register. */
#define NVMCTRL_CTRLA_CMD_SPRM_Val _U_(0x42) /**< \brief (NVMCTRL_CTRLA) Sets the power reduction mode. */
#define NVMCTRL_CTRLA_CMD_CPRM_Val _U_(0x43) /**< \brief (NVMCTRL_CTRLA) Clears the power reduction mode. */
#define NVMCTRL_CTRLA_CMD_PBC_Val _U_(0x44) /**< \brief (NVMCTRL_CTRLA) Page Buffer Clear - Clears the page buffer. */
#define NVMCTRL_CTRLA_CMD_SSB_Val _U_(0x45) /**< \brief (NVMCTRL_CTRLA) Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. */
#define NVMCTRL_CTRLA_CMD_INVALL_Val _U_(0x46) /**< \brief (NVMCTRL_CTRLA) Invalidate all cache lines. */
#define NVMCTRL_CTRLA_CMD_ER (NVMCTRL_CTRLA_CMD_ER_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_WP (NVMCTRL_CTRLA_CMD_WP_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_EAR (NVMCTRL_CTRLA_CMD_EAR_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_WAP (NVMCTRL_CTRLA_CMD_WAP_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_SF (NVMCTRL_CTRLA_CMD_SF_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_WL (NVMCTRL_CTRLA_CMD_WL_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_RWWEEER (NVMCTRL_CTRLA_CMD_RWWEEER_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_RWWEEWP (NVMCTRL_CTRLA_CMD_RWWEEWP_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_LR (NVMCTRL_CTRLA_CMD_LR_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_UR (NVMCTRL_CTRLA_CMD_UR_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_SPRM (NVMCTRL_CTRLA_CMD_SPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_CPRM (NVMCTRL_CTRLA_CMD_CPRM_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_PBC (NVMCTRL_CTRLA_CMD_PBC_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_SSB (NVMCTRL_CTRLA_CMD_SSB_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMD_INVALL (NVMCTRL_CTRLA_CMD_INVALL_Val << NVMCTRL_CTRLA_CMD_Pos)
#define NVMCTRL_CTRLA_CMDEX_Pos 8 /**< \brief (NVMCTRL_CTRLA) Command Execution */
#define NVMCTRL_CTRLA_CMDEX_Msk (_U_(0xFF) << NVMCTRL_CTRLA_CMDEX_Pos)
#define NVMCTRL_CTRLA_CMDEX(value) (NVMCTRL_CTRLA_CMDEX_Msk & ((value) << NVMCTRL_CTRLA_CMDEX_Pos))
#define NVMCTRL_CTRLA_CMDEX_KEY_Val _U_(0xA5) /**< \brief (NVMCTRL_CTRLA) Execution Key */
#define NVMCTRL_CTRLA_CMDEX_KEY (NVMCTRL_CTRLA_CMDEX_KEY_Val << NVMCTRL_CTRLA_CMDEX_Pos)
#define NVMCTRL_CTRLA_MASK _U_(0xFF7F) /**< \brief (NVMCTRL_CTRLA) MASK Register */
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t MANW:1; /*!< bit: 7 Manual Write */
uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
uint32_t CACHEDIS:2; /*!< bit: 18..19 Cache Disable */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_CTRLB_OFFSET 0x04 /**< \brief (NVMCTRL_CTRLB offset) Control B */
#define NVMCTRL_CTRLB_RESETVALUE _U_(0x00000080) /**< \brief (NVMCTRL_CTRLB reset_value) Control B */
#define NVMCTRL_CTRLB_RWS_Pos 1 /**< \brief (NVMCTRL_CTRLB) NVM Read Wait States */
#define NVMCTRL_CTRLB_RWS_Msk (_U_(0xF) << NVMCTRL_CTRLB_RWS_Pos)
#define NVMCTRL_CTRLB_RWS(value) (NVMCTRL_CTRLB_RWS_Msk & ((value) << NVMCTRL_CTRLB_RWS_Pos))
#define NVMCTRL_CTRLB_RWS_SINGLE_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) Single Auto Wait State */
#define NVMCTRL_CTRLB_RWS_HALF_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) Half Auto Wait State */
#define NVMCTRL_CTRLB_RWS_DUAL_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLB) Dual Auto Wait State */
#define NVMCTRL_CTRLB_RWS_SINGLE (NVMCTRL_CTRLB_RWS_SINGLE_Val << NVMCTRL_CTRLB_RWS_Pos)
#define NVMCTRL_CTRLB_RWS_HALF (NVMCTRL_CTRLB_RWS_HALF_Val << NVMCTRL_CTRLB_RWS_Pos)
#define NVMCTRL_CTRLB_RWS_DUAL (NVMCTRL_CTRLB_RWS_DUAL_Val << NVMCTRL_CTRLB_RWS_Pos)
#define NVMCTRL_CTRLB_MANW_Pos 7 /**< \brief (NVMCTRL_CTRLB) Manual Write */
#define NVMCTRL_CTRLB_MANW (_U_(0x1) << NVMCTRL_CTRLB_MANW_Pos)
#define NVMCTRL_CTRLB_SLEEPPRM_Pos 8 /**< \brief (NVMCTRL_CTRLB) Power Reduction Mode during Sleep */
#define NVMCTRL_CTRLB_SLEEPPRM_Msk (_U_(0x3) << NVMCTRL_CTRLB_SLEEPPRM_Pos)
#define NVMCTRL_CTRLB_SLEEPPRM(value) (NVMCTRL_CTRLB_SLEEPPRM_Msk & ((value) << NVMCTRL_CTRLB_SLEEPPRM_Pos))
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. */
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. */
#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val _U_(0x3) /**< \brief (NVMCTRL_CTRLB) Auto power reduction disabled. */
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS (NVMCTRL_CTRLB_SLEEPPRM_WAKEONACCESS_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
#define NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT (NVMCTRL_CTRLB_SLEEPPRM_WAKEUPINSTANT_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
#define NVMCTRL_CTRLB_SLEEPPRM_DISABLED (NVMCTRL_CTRLB_SLEEPPRM_DISABLED_Val << NVMCTRL_CTRLB_SLEEPPRM_Pos)
#define NVMCTRL_CTRLB_READMODE_Pos 16 /**< \brief (NVMCTRL_CTRLB) NVMCTRL Read Mode */
#define NVMCTRL_CTRLB_READMODE_Msk (_U_(0x3) << NVMCTRL_CTRLB_READMODE_Pos)
#define NVMCTRL_CTRLB_READMODE(value) (NVMCTRL_CTRLB_READMODE_Msk & ((value) << NVMCTRL_CTRLB_READMODE_Pos))
#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val _U_(0x0) /**< \brief (NVMCTRL_CTRLB) The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. */
#define NVMCTRL_CTRLB_READMODE_LOW_POWER_Val _U_(0x1) /**< \brief (NVMCTRL_CTRLB) Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. */
#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val _U_(0x2) /**< \brief (NVMCTRL_CTRLB) The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. */
#define NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY (NVMCTRL_CTRLB_READMODE_NO_MISS_PENALTY_Val << NVMCTRL_CTRLB_READMODE_Pos)
#define NVMCTRL_CTRLB_READMODE_LOW_POWER (NVMCTRL_CTRLB_READMODE_LOW_POWER_Val << NVMCTRL_CTRLB_READMODE_Pos)
#define NVMCTRL_CTRLB_READMODE_DETERMINISTIC (NVMCTRL_CTRLB_READMODE_DETERMINISTIC_Val << NVMCTRL_CTRLB_READMODE_Pos)
#define NVMCTRL_CTRLB_CACHEDIS_Pos 18 /**< \brief (NVMCTRL_CTRLB) Cache Disable */
#define NVMCTRL_CTRLB_CACHEDIS_Msk (_U_(0x3) << NVMCTRL_CTRLB_CACHEDIS_Pos)
#define NVMCTRL_CTRLB_CACHEDIS(value) (NVMCTRL_CTRLB_CACHEDIS_Msk & ((value) << NVMCTRL_CTRLB_CACHEDIS_Pos))
#define NVMCTRL_CTRLB_MASK _U_(0x000F039E) /**< \brief (NVMCTRL_CTRLB) MASK Register */
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
uint32_t :1; /*!< bit: 19 Reserved */
uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_PARAM_OFFSET 0x08 /**< \brief (NVMCTRL_PARAM offset) NVM Parameter */
#define NVMCTRL_PARAM_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_PARAM reset_value) NVM Parameter */
#define NVMCTRL_PARAM_NVMP_Pos 0 /**< \brief (NVMCTRL_PARAM) NVM Pages */
#define NVMCTRL_PARAM_NVMP_Msk (_U_(0xFFFF) << NVMCTRL_PARAM_NVMP_Pos)
#define NVMCTRL_PARAM_NVMP(value) (NVMCTRL_PARAM_NVMP_Msk & ((value) << NVMCTRL_PARAM_NVMP_Pos))
#define NVMCTRL_PARAM_PSZ_Pos 16 /**< \brief (NVMCTRL_PARAM) Page Size */
#define NVMCTRL_PARAM_PSZ_Msk (_U_(0x7) << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ(value) (NVMCTRL_PARAM_PSZ_Msk & ((value) << NVMCTRL_PARAM_PSZ_Pos))
#define NVMCTRL_PARAM_PSZ_8_Val _U_(0x0) /**< \brief (NVMCTRL_PARAM) 8 bytes */
#define NVMCTRL_PARAM_PSZ_16_Val _U_(0x1) /**< \brief (NVMCTRL_PARAM) 16 bytes */
#define NVMCTRL_PARAM_PSZ_32_Val _U_(0x2) /**< \brief (NVMCTRL_PARAM) 32 bytes */
#define NVMCTRL_PARAM_PSZ_64_Val _U_(0x3) /**< \brief (NVMCTRL_PARAM) 64 bytes */
#define NVMCTRL_PARAM_PSZ_128_Val _U_(0x4) /**< \brief (NVMCTRL_PARAM) 128 bytes */
#define NVMCTRL_PARAM_PSZ_256_Val _U_(0x5) /**< \brief (NVMCTRL_PARAM) 256 bytes */
#define NVMCTRL_PARAM_PSZ_512_Val _U_(0x6) /**< \brief (NVMCTRL_PARAM) 512 bytes */
#define NVMCTRL_PARAM_PSZ_1024_Val _U_(0x7) /**< \brief (NVMCTRL_PARAM) 1024 bytes */
#define NVMCTRL_PARAM_PSZ_8 (NVMCTRL_PARAM_PSZ_8_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_16 (NVMCTRL_PARAM_PSZ_16_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_32 (NVMCTRL_PARAM_PSZ_32_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_64 (NVMCTRL_PARAM_PSZ_64_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_128 (NVMCTRL_PARAM_PSZ_128_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_256 (NVMCTRL_PARAM_PSZ_256_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_512 (NVMCTRL_PARAM_PSZ_512_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_PSZ_1024 (NVMCTRL_PARAM_PSZ_1024_Val << NVMCTRL_PARAM_PSZ_Pos)
#define NVMCTRL_PARAM_RWWEEP_Pos 20 /**< \brief (NVMCTRL_PARAM) RWW EEPROM Pages */
#define NVMCTRL_PARAM_RWWEEP_Msk (_U_(0xFFF) << NVMCTRL_PARAM_RWWEEP_Pos)
#define NVMCTRL_PARAM_RWWEEP(value) (NVMCTRL_PARAM_RWWEEP_Msk & ((value) << NVMCTRL_PARAM_RWWEEP_Pos))
#define NVMCTRL_PARAM_MASK _U_(0xFFF7FFFF) /**< \brief (NVMCTRL_PARAM) MASK Register */
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTENCLR_OFFSET 0x0C /**< \brief (NVMCTRL_INTENCLR offset) Interrupt Enable Clear */
#define NVMCTRL_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_INTENCLR reset_value) Interrupt Enable Clear */
#define NVMCTRL_INTENCLR_READY_Pos 0 /**< \brief (NVMCTRL_INTENCLR) NVM Ready Interrupt Enable */
#define NVMCTRL_INTENCLR_READY (_U_(0x1) << NVMCTRL_INTENCLR_READY_Pos)
#define NVMCTRL_INTENCLR_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENCLR) Error Interrupt Enable */
#define NVMCTRL_INTENCLR_ERROR (_U_(0x1) << NVMCTRL_INTENCLR_ERROR_Pos)
#define NVMCTRL_INTENCLR_MASK _U_(0x03) /**< \brief (NVMCTRL_INTENCLR) MASK Register */
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTENSET_OFFSET 0x10 /**< \brief (NVMCTRL_INTENSET offset) Interrupt Enable Set */
#define NVMCTRL_INTENSET_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_INTENSET reset_value) Interrupt Enable Set */
#define NVMCTRL_INTENSET_READY_Pos 0 /**< \brief (NVMCTRL_INTENSET) NVM Ready Interrupt Enable */
#define NVMCTRL_INTENSET_READY (_U_(0x1) << NVMCTRL_INTENSET_READY_Pos)
#define NVMCTRL_INTENSET_ERROR_Pos 1 /**< \brief (NVMCTRL_INTENSET) Error Interrupt Enable */
#define NVMCTRL_INTENSET_ERROR (_U_(0x1) << NVMCTRL_INTENSET_ERROR_Pos)
#define NVMCTRL_INTENSET_MASK _U_(0x03) /**< \brief (NVMCTRL_INTENSET) MASK Register */
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t READY:1; /*!< bit: 0 NVM Ready */
__I uint8_t ERROR:1; /*!< bit: 1 Error */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_INTFLAG_OFFSET 0x14 /**< \brief (NVMCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
#define NVMCTRL_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (NVMCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define NVMCTRL_INTFLAG_READY_Pos 0 /**< \brief (NVMCTRL_INTFLAG) NVM Ready */
#define NVMCTRL_INTFLAG_READY (_U_(0x1) << NVMCTRL_INTFLAG_READY_Pos)
#define NVMCTRL_INTFLAG_ERROR_Pos 1 /**< \brief (NVMCTRL_INTFLAG) Error */
#define NVMCTRL_INTFLAG_ERROR (_U_(0x1) << NVMCTRL_INTFLAG_ERROR_Pos)
#define NVMCTRL_INTFLAG_MASK _U_(0x03) /**< \brief (NVMCTRL_INTFLAG) MASK Register */
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
uint16_t NVME:1; /*!< bit: 4 NVM Error */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t SB:1; /*!< bit: 8 Security Bit Status */
uint16_t :7; /*!< bit: 9..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_STATUS_OFFSET 0x18 /**< \brief (NVMCTRL_STATUS offset) Status */
#define NVMCTRL_STATUS_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_STATUS reset_value) Status */
#define NVMCTRL_STATUS_PRM_Pos 0 /**< \brief (NVMCTRL_STATUS) Power Reduction Mode */
#define NVMCTRL_STATUS_PRM (_U_(0x1) << NVMCTRL_STATUS_PRM_Pos)
#define NVMCTRL_STATUS_LOAD_Pos 1 /**< \brief (NVMCTRL_STATUS) NVM Page Buffer Active Loading */
#define NVMCTRL_STATUS_LOAD (_U_(0x1) << NVMCTRL_STATUS_LOAD_Pos)
#define NVMCTRL_STATUS_PROGE_Pos 2 /**< \brief (NVMCTRL_STATUS) Programming Error Status */
#define NVMCTRL_STATUS_PROGE (_U_(0x1) << NVMCTRL_STATUS_PROGE_Pos)
#define NVMCTRL_STATUS_LOCKE_Pos 3 /**< \brief (NVMCTRL_STATUS) Lock Error Status */
#define NVMCTRL_STATUS_LOCKE (_U_(0x1) << NVMCTRL_STATUS_LOCKE_Pos)
#define NVMCTRL_STATUS_NVME_Pos 4 /**< \brief (NVMCTRL_STATUS) NVM Error */
#define NVMCTRL_STATUS_NVME (_U_(0x1) << NVMCTRL_STATUS_NVME_Pos)
#define NVMCTRL_STATUS_SB_Pos 8 /**< \brief (NVMCTRL_STATUS) Security Bit Status */
#define NVMCTRL_STATUS_SB (_U_(0x1) << NVMCTRL_STATUS_SB_Pos)
#define NVMCTRL_STATUS_MASK _U_(0x011F) /**< \brief (NVMCTRL_STATUS) MASK Register */
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_ADDR_OFFSET 0x1C /**< \brief (NVMCTRL_ADDR offset) Address */
#define NVMCTRL_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_ADDR reset_value) Address */
#define NVMCTRL_ADDR_ADDR_Pos 0 /**< \brief (NVMCTRL_ADDR) NVM Address */
#define NVMCTRL_ADDR_ADDR_Msk (_U_(0x3FFFFF) << NVMCTRL_ADDR_ADDR_Pos)
#define NVMCTRL_ADDR_ADDR(value) (NVMCTRL_ADDR_ADDR_Msk & ((value) << NVMCTRL_ADDR_ADDR_Pos))
#define NVMCTRL_ADDR_MASK _U_(0x003FFFFF) /**< \brief (NVMCTRL_ADDR) MASK Register */
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_LOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_LOCK_OFFSET 0x20 /**< \brief (NVMCTRL_LOCK offset) Lock Section */
#define NVMCTRL_LOCK_RESETVALUE _U_(0x0000) /**< \brief (NVMCTRL_LOCK reset_value) Lock Section */
#define NVMCTRL_LOCK_LOCK_Pos 0 /**< \brief (NVMCTRL_LOCK) Region Lock Bits */
#define NVMCTRL_LOCK_LOCK_Msk (_U_(0xFFFF) << NVMCTRL_LOCK_LOCK_Pos)
#define NVMCTRL_LOCK_LOCK(value) (NVMCTRL_LOCK_LOCK_Msk & ((value) << NVMCTRL_LOCK_LOCK_Pos))
#define NVMCTRL_LOCK_MASK _U_(0xFFFF) /**< \brief (NVMCTRL_LOCK) MASK Register */
/* -------- NVMCTRL_PBLDATA0 : (NVMCTRL Offset: 0x28) (R/ 32) Page Buffer Load Data 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PBLDATA0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_PBLDATA0_OFFSET 0x28 /**< \brief (NVMCTRL_PBLDATA0 offset) Page Buffer Load Data 0 */
#define NVMCTRL_PBLDATA0_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_PBLDATA0 reset_value) Page Buffer Load Data 0 */
#define NVMCTRL_PBLDATA0_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA0) MASK Register */
/* -------- NVMCTRL_PBLDATA1 : (NVMCTRL Offset: 0x2C) (R/ 32) Page Buffer Load Data 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PBLDATA1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define NVMCTRL_PBLDATA1_OFFSET 0x2C /**< \brief (NVMCTRL_PBLDATA1 offset) Page Buffer Load Data 1 */
#define NVMCTRL_PBLDATA1_RESETVALUE _U_(0x00000000) /**< \brief (NVMCTRL_PBLDATA1 reset_value) Page Buffer Load Data 1 */
#define NVMCTRL_PBLDATA1_MASK _U_(0xFFFFFFFF) /**< \brief (NVMCTRL_PBLDATA1) MASK Register */
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
RoReg8 Reserved1[0x2];
__IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
__IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
__IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
RoReg8 Reserved2[0x3];
__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
RoReg8 Reserved3[0x3];
__IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x3];
__IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
RoReg8 Reserved5[0x2];
__IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
__IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
RoReg8 Reserved6[0x6];
__I NVMCTRL_PBLDATA0_Type PBLDATA0; /**< \brief Offset: 0x28 (R/ 32) Page Buffer Load Data 0 */
__I NVMCTRL_PBLDATA1_Type PBLDATA1; /**< \brief Offset: 0x2C (R/ 32) Page Buffer Load Data 1 */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#ifdef __GNUC__
#define SECTION_NVMCTRL_CAL __attribute__ ((section(".flash")))
#define SECTION_NVMCTRL_LOCKBIT __attribute__ ((section(".flash")))
#define SECTION_NVMCTRL_OTP1 __attribute__ ((section(".flash")))
#define SECTION_NVMCTRL_OTP2 __attribute__ ((section(".flash")))
#define SECTION_NVMCTRL_OTP3 __attribute__ ((section(".flash")))
#define SECTION_NVMCTRL_OTP4 __attribute__ ((section(".flash")))
#define SECTION_NVMCTRL_OTP5 __attribute__ ((section(".flash")))
#define SECTION_NVMCTRL_TEMP_LOG __attribute__ ((section(".flash")))
#define SECTION_NVMCTRL_USER __attribute__ ((section(".flash")))
#elif defined(__ICCARM__)
#define SECTION_NVMCTRL_CAL @".flash"
#define SECTION_NVMCTRL_LOCKBIT @".flash"
#define SECTION_NVMCTRL_OTP1 @".flash"
#define SECTION_NVMCTRL_OTP2 @".flash"
#define SECTION_NVMCTRL_OTP3 @".flash"
#define SECTION_NVMCTRL_OTP4 @".flash"
#define SECTION_NVMCTRL_OTP5 @".flash"
#define SECTION_NVMCTRL_TEMP_LOG @".flash"
#define SECTION_NVMCTRL_USER @".flash"
#endif
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR NON-VOLATILE FUSES */
/* ************************************************************************** */
/** \addtogroup fuses_api Peripheral Software API */
/*@{*/
#define ADC0_FUSES_BIASCOMP_ADDR NVMCTRL_OTP5
#define ADC0_FUSES_BIASCOMP_Pos 3 /**< \brief (NVMCTRL_OTP5) ADC Comparator Scaling */
#define ADC0_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC0_FUSES_BIASCOMP_Pos)
#define ADC0_FUSES_BIASCOMP(value) (ADC0_FUSES_BIASCOMP_Msk & ((value) << ADC0_FUSES_BIASCOMP_Pos))
#define ADC0_FUSES_BIASREFBUF_ADDR NVMCTRL_OTP5
#define ADC0_FUSES_BIASREFBUF_Pos 0 /**< \brief (NVMCTRL_OTP5) ADC Bias Reference Buffer Scaling */
#define ADC0_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC0_FUSES_BIASREFBUF_Pos)
#define ADC0_FUSES_BIASREFBUF(value) (ADC0_FUSES_BIASREFBUF_Msk & ((value) << ADC0_FUSES_BIASREFBUF_Pos))
#define ADC1_FUSES_BIASCOMP_ADDR NVMCTRL_OTP5
#define ADC1_FUSES_BIASCOMP_Pos 9 /**< \brief (NVMCTRL_OTP5) ADC Comparator Scaling */
#define ADC1_FUSES_BIASCOMP_Msk (_U_(0x7) << ADC1_FUSES_BIASCOMP_Pos)
#define ADC1_FUSES_BIASCOMP(value) (ADC1_FUSES_BIASCOMP_Msk & ((value) << ADC1_FUSES_BIASCOMP_Pos))
#define ADC1_FUSES_BIASREFBUF_ADDR NVMCTRL_OTP5
#define ADC1_FUSES_BIASREFBUF_Pos 6 /**< \brief (NVMCTRL_OTP5) ADC Bias Reference Buffer Scaling */
#define ADC1_FUSES_BIASREFBUF_Msk (_U_(0x7) << ADC1_FUSES_BIASREFBUF_Pos)
#define ADC1_FUSES_BIASREFBUF(value) (ADC1_FUSES_BIASREFBUF_Msk & ((value) << ADC1_FUSES_BIASREFBUF_Pos))
#define FUSES_BODCOREUSERLEVEL_ADDR NVMCTRL_USER
#define FUSES_BODCOREUSERLEVEL_Pos 17 /**< \brief (NVMCTRL_USER) BODCORE User Level */
#define FUSES_BODCOREUSERLEVEL_Msk (_U_(0x3F) << FUSES_BODCOREUSERLEVEL_Pos)
#define FUSES_BODCOREUSERLEVEL(value) (FUSES_BODCOREUSERLEVEL_Msk & ((value) << FUSES_BODCOREUSERLEVEL_Pos))
#define FUSES_BODCORE_ACTION_ADDR NVMCTRL_USER
#define FUSES_BODCORE_ACTION_Pos 24 /**< \brief (NVMCTRL_USER) BODCORE Action */
#define FUSES_BODCORE_ACTION_Msk (_U_(0x3) << FUSES_BODCORE_ACTION_Pos)
#define FUSES_BODCORE_ACTION(value) (FUSES_BODCORE_ACTION_Msk & ((value) << FUSES_BODCORE_ACTION_Pos))
#define FUSES_BODCORE_DIS_ADDR NVMCTRL_USER
#define FUSES_BODCORE_DIS_Pos 23 /**< \brief (NVMCTRL_USER) BODCORE Disable */
#define FUSES_BODCORE_DIS_Msk (_U_(0x1) << FUSES_BODCORE_DIS_Pos)
#define FUSES_BODCORE_HYST_ADDR (NVMCTRL_USER + 4)
#define FUSES_BODCORE_HYST_Pos 10 /**< \brief (NVMCTRL_USER) BODCORE Hysterisis */
#define FUSES_BODCORE_HYST_Msk (_U_(0x1) << FUSES_BODCORE_HYST_Pos)
#define FUSES_BODVDDUSERLEVEL_ADDR NVMCTRL_USER
#define FUSES_BODVDDUSERLEVEL_Pos 8 /**< \brief (NVMCTRL_USER) BODVDD User Level */
#define FUSES_BODVDDUSERLEVEL_Msk (_U_(0x3F) << FUSES_BODVDDUSERLEVEL_Pos)
#define FUSES_BODVDDUSERLEVEL(value) (FUSES_BODVDDUSERLEVEL_Msk & ((value) << FUSES_BODVDDUSERLEVEL_Pos))
#define FUSES_BODVDD_ACTION_ADDR NVMCTRL_USER
#define FUSES_BODVDD_ACTION_Pos 15 /**< \brief (NVMCTRL_USER) BODVDD Action */
#define FUSES_BODVDD_ACTION_Msk (_U_(0x3) << FUSES_BODVDD_ACTION_Pos)
#define FUSES_BODVDD_ACTION(value) (FUSES_BODVDD_ACTION_Msk & ((value) << FUSES_BODVDD_ACTION_Pos))
#define FUSES_BODVDD_DIS_ADDR NVMCTRL_USER
#define FUSES_BODVDD_DIS_Pos 14 /**< \brief (NVMCTRL_USER) BODVDD Disable */
#define FUSES_BODVDD_DIS_Msk (_U_(0x1) << FUSES_BODVDD_DIS_Pos)
#define FUSES_BODVDD_HYST_ADDR (NVMCTRL_USER + 4)
#define FUSES_BODVDD_HYST_Pos 9 /**< \brief (NVMCTRL_USER) BODVDD Hysterisis */
#define FUSES_BODVDD_HYST_Msk (_U_(0x1) << FUSES_BODVDD_HYST_Pos)
#define NVMCTRL_FUSES_BOOTPROT_ADDR NVMCTRL_USER
#define NVMCTRL_FUSES_BOOTPROT_Pos 0 /**< \brief (NVMCTRL_USER) Bootloader Size */
#define NVMCTRL_FUSES_BOOTPROT_Msk (_U_(0x7) << NVMCTRL_FUSES_BOOTPROT_Pos)
#define NVMCTRL_FUSES_BOOTPROT(value) (NVMCTRL_FUSES_BOOTPROT_Msk & ((value) << NVMCTRL_FUSES_BOOTPROT_Pos))
#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR NVMCTRL_USER
#define NVMCTRL_FUSES_EEPROM_SIZE_Pos 4 /**< \brief (NVMCTRL_USER) EEPROM Size */
#define NVMCTRL_FUSES_EEPROM_SIZE_Msk (_U_(0x7) << NVMCTRL_FUSES_EEPROM_SIZE_Pos)
#define NVMCTRL_FUSES_EEPROM_SIZE(value) (NVMCTRL_FUSES_EEPROM_SIZE_Msk & ((value) << NVMCTRL_FUSES_EEPROM_SIZE_Pos))
#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (NVMCTRL_USER + 4)
#define NVMCTRL_FUSES_REGION_LOCKS_Pos 16 /**< \brief (NVMCTRL_USER) NVM Region Locks */
#define NVMCTRL_FUSES_REGION_LOCKS_Msk (_U_(0xFFFF) << NVMCTRL_FUSES_REGION_LOCKS_Pos)
#define NVMCTRL_FUSES_REGION_LOCKS(value) (NVMCTRL_FUSES_REGION_LOCKS_Msk & ((value) << NVMCTRL_FUSES_REGION_LOCKS_Pos))
#define TSENS_FUSES_FCAL_ADDR NVMCTRL_TEMP_LOG
#define TSENS_FUSES_FCAL_Pos 6 /**< \brief (NVMCTRL_TEMP_LOG) Frequency Calibration */
#define TSENS_FUSES_FCAL_Msk (_U_(0x3F) << TSENS_FUSES_FCAL_Pos)
#define TSENS_FUSES_FCAL(value) (TSENS_FUSES_FCAL_Msk & ((value) << TSENS_FUSES_FCAL_Pos))
#define TSENS_FUSES_GAIN_0_ADDR NVMCTRL_TEMP_LOG
#define TSENS_FUSES_GAIN_0_Pos 12 /**< \brief (NVMCTRL_TEMP_LOG) Gain Calibration bits 19:0 */
#define TSENS_FUSES_GAIN_0_Msk (_U_(0xFFFFF) << TSENS_FUSES_GAIN_0_Pos)
#define TSENS_FUSES_GAIN_0(value) (TSENS_FUSES_GAIN_0_Msk & ((value) << TSENS_FUSES_GAIN_0_Pos))
#define TSENS_FUSES_GAIN_1_ADDR (NVMCTRL_TEMP_LOG + 4)
#define TSENS_FUSES_GAIN_1_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Gain Calibration bits 23:20 */
#define TSENS_FUSES_GAIN_1_Msk (_U_(0xF) << TSENS_FUSES_GAIN_1_Pos)
#define TSENS_FUSES_GAIN_1(value) (TSENS_FUSES_GAIN_1_Msk & ((value) << TSENS_FUSES_GAIN_1_Pos))
#define TSENS_FUSES_OFFSET_ADDR (NVMCTRL_TEMP_LOG + 4)
#define TSENS_FUSES_OFFSET_Pos 4 /**< \brief (NVMCTRL_TEMP_LOG) Offse Calibration */
#define TSENS_FUSES_OFFSET_Msk (_U_(0xFFFFFF) << TSENS_FUSES_OFFSET_Pos)
#define TSENS_FUSES_OFFSET(value) (TSENS_FUSES_OFFSET_Msk & ((value) << TSENS_FUSES_OFFSET_Pos))
#define TSENS_FUSES_TCAL_ADDR NVMCTRL_TEMP_LOG
#define TSENS_FUSES_TCAL_Pos 0 /**< \brief (NVMCTRL_TEMP_LOG) Temperature Calibration */
#define TSENS_FUSES_TCAL_Msk (_U_(0x3F) << TSENS_FUSES_TCAL_Pos)
#define TSENS_FUSES_TCAL(value) (TSENS_FUSES_TCAL_Msk & ((value) << TSENS_FUSES_TCAL_Pos))
#define WDT_FUSES_ALWAYSON_ADDR NVMCTRL_USER
#define WDT_FUSES_ALWAYSON_Pos 27 /**< \brief (NVMCTRL_USER) WDT Always On */
#define WDT_FUSES_ALWAYSON_Msk (_U_(0x1) << WDT_FUSES_ALWAYSON_Pos)
#define WDT_FUSES_ENABLE_ADDR NVMCTRL_USER
#define WDT_FUSES_ENABLE_Pos 26 /**< \brief (NVMCTRL_USER) WDT Enable */
#define WDT_FUSES_ENABLE_Msk (_U_(0x1) << WDT_FUSES_ENABLE_Pos)
#define WDT_FUSES_EWOFFSET_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_EWOFFSET_Pos 4 /**< \brief (NVMCTRL_USER) WDT Early Warning Offset */
#define WDT_FUSES_EWOFFSET_Msk (_U_(0xF) << WDT_FUSES_EWOFFSET_Pos)
#define WDT_FUSES_EWOFFSET(value) (WDT_FUSES_EWOFFSET_Msk & ((value) << WDT_FUSES_EWOFFSET_Pos))
#define WDT_FUSES_PER_ADDR NVMCTRL_USER
#define WDT_FUSES_PER_Pos 28 /**< \brief (NVMCTRL_USER) WDT Period */
#define WDT_FUSES_PER_Msk (_U_(0xF) << WDT_FUSES_PER_Pos)
#define WDT_FUSES_PER(value) (WDT_FUSES_PER_Msk & ((value) << WDT_FUSES_PER_Pos))
#define WDT_FUSES_WEN_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_WEN_Pos 8 /**< \brief (NVMCTRL_USER) WDT Window Mode Enable */
#define WDT_FUSES_WEN_Msk (_U_(0x1) << WDT_FUSES_WEN_Pos)
#define WDT_FUSES_WINDOW_ADDR (NVMCTRL_USER + 4)
#define WDT_FUSES_WINDOW_Pos 0 /**< \brief (NVMCTRL_USER) WDT Window */
#define WDT_FUSES_WINDOW_Msk (_U_(0xF) << WDT_FUSES_WINDOW_Pos)
#define WDT_FUSES_WINDOW(value) (WDT_FUSES_WINDOW_Msk & ((value) << WDT_FUSES_WINDOW_Pos))
/*@}*/
#endif /* _SAMC21_NVMCTRL_COMPONENT_ */

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/**
* \file
*
* \brief Component description for OSC32KCTRL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_OSC32KCTRL_COMPONENT_
#define _SAMC21_OSC32KCTRL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR OSC32KCTRL */
/* ========================================================================== */
/** \addtogroup SAMC21_OSC32KCTRL 32k Oscillators Control */
/*@{*/
#define OSC32KCTRL_U2246
#define REV_OSC32KCTRL 0x210
/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */
uint32_t CLKFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */
#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */
#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
#define OSC32KCTRL_INTENCLR_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENCLR) OSC32K Ready Interrupt Enable */
#define OSC32KCTRL_INTENCLR_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_OSC32KRDY_Pos)
#define OSC32KCTRL_INTENCLR_CLKFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */
#define OSC32KCTRL_INTENCLR_CLKFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_CLKFAIL_Pos)
#define OSC32KCTRL_INTENCLR_MASK _U_(0x00000007) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */
/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready Interrupt Enable */
uint32_t CLKFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */
#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */
#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
#define OSC32KCTRL_INTENSET_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTENSET) OSC32K Ready Interrupt Enable */
#define OSC32KCTRL_INTENSET_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_OSC32KRDY_Pos)
#define OSC32KCTRL_INTENSET_CLKFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */
#define OSC32KCTRL_INTENSET_CLKFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_CLKFAIL_Pos)
#define OSC32KCTRL_INTENSET_MASK _U_(0x00000007) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */
/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
__I uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */
__I uint32_t CLKFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
__I uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */
#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
#define OSC32KCTRL_INTFLAG_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_INTFLAG) OSC32K Ready */
#define OSC32KCTRL_INTFLAG_OSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_OSC32KRDY_Pos)
#define OSC32KCTRL_INTFLAG_CLKFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */
#define OSC32KCTRL_INTFLAG_CLKFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_CLKFAIL_Pos)
#define OSC32KCTRL_INTFLAG_MASK _U_(0x00000007) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */
/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 1 OSC32K Ready */
uint32_t CLKFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
uint32_t CLKSW:1; /*!< bit: 3 XOSC32K Clock switch */
uint32_t :28; /*!< bit: 4..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */
#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */
#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */
#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
#define OSC32KCTRL_STATUS_OSC32KRDY_Pos 1 /**< \brief (OSC32KCTRL_STATUS) OSC32K Ready */
#define OSC32KCTRL_STATUS_OSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_OSC32KRDY_Pos)
#define OSC32KCTRL_STATUS_CLKFAIL_Pos 2 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */
#define OSC32KCTRL_STATUS_CLKFAIL (_U_(0x1) << OSC32KCTRL_STATUS_CLKFAIL_Pos)
#define OSC32KCTRL_STATUS_CLKSW_Pos 3 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */
#define OSC32KCTRL_STATUS_CLKSW (_U_(0x1) << OSC32KCTRL_STATUS_CLKSW_Pos)
#define OSC32KCTRL_STATUS_MASK _U_(0x0000000F) /**< \brief (OSC32KCTRL_STATUS) MASK Register */
/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 32) Clock selection -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_RTCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) Clock selection */
#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) Clock selection */
#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */
#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val _U_(0x2) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val _U_(0x3) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz internal oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_OSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
#define OSC32KCTRL_RTCCTRL_MASK _U_(0x00000007) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */
/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
uint16_t :1; /*!< bit: 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint16_t :1; /*!< bit: 11 Reserved */
uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} OSC32KCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x0080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */
#define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */
#define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
#define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */
#define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
#define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */
#define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */
#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */
#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */
#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */
#define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
#define OSC32KCTRL_XOSC32K_MASK _U_(0x17DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */
/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CFDEN:1; /*!< bit: 0 Clock Failure Detector Enable */
uint8_t SWBACK:1; /*!< bit: 1 Clock Switch Back */
uint8_t CFDPRESC:1; /*!< bit: 2 Clock Failure Detector Prescaler */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSC32KCTRL_CFDCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_CFDCTRL_OFFSET 0x16 /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */
#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */
#define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */
#define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
#define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */
#define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */
#define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
#define OSC32KCTRL_CFDCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */
/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSC32KCTRL_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_EVCTRL_OFFSET 0x17 /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */
#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */
#define OSC32KCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */
#define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
#define OSC32KCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */
/* -------- OSC32KCTRL_OSC32K : (OSC32KCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_OSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_OSC32K_OFFSET 0x18 /**< \brief (OSC32KCTRL_OSC32K offset) 32kHz Internal Oscillator (OSC32K) Control */
#define OSC32KCTRL_OSC32K_RESETVALUE _U_(0x003F0080) /**< \brief (OSC32KCTRL_OSC32K reset_value) 32kHz Internal Oscillator (OSC32K) Control */
#define OSC32KCTRL_OSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Enable */
#define OSC32KCTRL_OSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_OSC32K_ENABLE_Pos)
#define OSC32KCTRL_OSC32K_EN32K_Pos 2 /**< \brief (OSC32KCTRL_OSC32K) 32kHz Output Enable */
#define OSC32KCTRL_OSC32K_EN32K (_U_(0x1) << OSC32KCTRL_OSC32K_EN32K_Pos)
#define OSC32KCTRL_OSC32K_EN1K_Pos 3 /**< \brief (OSC32KCTRL_OSC32K) 1kHz Output Enable */
#define OSC32KCTRL_OSC32K_EN1K (_U_(0x1) << OSC32KCTRL_OSC32K_EN1K_Pos)
#define OSC32KCTRL_OSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_OSC32K) Run in Standby */
#define OSC32KCTRL_OSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_OSC32K_RUNSTDBY_Pos)
#define OSC32KCTRL_OSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_OSC32K) On Demand Control */
#define OSC32KCTRL_OSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_OSC32K_ONDEMAND_Pos)
#define OSC32KCTRL_OSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Start-Up Time */
#define OSC32KCTRL_OSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_OSC32K_STARTUP_Pos)
#define OSC32KCTRL_OSC32K_STARTUP(value) (OSC32KCTRL_OSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_OSC32K_STARTUP_Pos))
#define OSC32KCTRL_OSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_OSC32K) Write Lock */
#define OSC32KCTRL_OSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSC32K_WRTLOCK_Pos)
#define OSC32KCTRL_OSC32K_CALIB_Pos 16 /**< \brief (OSC32KCTRL_OSC32K) Oscillator Calibration */
#define OSC32KCTRL_OSC32K_CALIB_Msk (_U_(0x7F) << OSC32KCTRL_OSC32K_CALIB_Pos)
#define OSC32KCTRL_OSC32K_CALIB(value) (OSC32KCTRL_OSC32K_CALIB_Msk & ((value) << OSC32KCTRL_OSC32K_CALIB_Pos))
#define OSC32KCTRL_OSC32K_MASK _U_(0x007F17CE) /**< \brief (OSC32KCTRL_OSC32K) MASK Register */
/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :8; /*!< bit: 0.. 7 Reserved */
uint32_t CALIB:5; /*!< bit: 8..12 Oscillator Calibration */
uint32_t :2; /*!< bit: 13..14 Reserved */
uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSC32KCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */
#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x1F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */
#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
#define OSC32KCTRL_OSCULP32K_MASK _U_(0x00009F00) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */
/** \brief OSC32KCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 32) Clock selection */
__IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
__IO OSC32KCTRL_CFDCTRL_Type CFDCTRL; /**< \brief Offset: 0x16 (R/W 8) Clock Failure Detector Control */
__IO OSC32KCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x17 (R/W 8) Event Control */
__IO OSC32KCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
__IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
} Osc32kctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_OSC32KCTRL_COMPONENT_ */

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/**
* \file
*
* \brief Component description for OSCCTRL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_OSCCTRL_COMPONENT_
#define _SAMC21_OSCCTRL_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR OSCCTRL */
/* ========================================================================== */
/** \addtogroup SAMC21_OSCCTRL Oscillators Control */
/*@{*/
#define OSCCTRL_U2119
#define REV_OSCCTRL 0x210
/* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSCFAIL:1; /*!< bit: 1 XOSC Clock Failure Detector Interrupt Enable */
uint32_t :2; /*!< bit: 2.. 3 Reserved */
uint32_t OSC48MRDY:1; /*!< bit: 4 OSC48M Ready Interrupt Enable */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 8 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 9 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 10 DPLL Time Out Interrupt Enable */
uint32_t DPLLLDRTO:1; /*!< bit: 11 DPLL Ratio Ready Interrupt Enable */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */
#define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */
#define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC Ready Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCRDY (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY_Pos)
#define OSCCTRL_INTENCLR_XOSCFAIL_Pos 1 /**< \brief (OSCCTRL_INTENCLR) XOSC Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENCLR_XOSCFAIL (_U_(0x1) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)
#define OSCCTRL_INTENCLR_OSC48MRDY_Pos 4 /**< \brief (OSCCTRL_INTENCLR) OSC48M Ready Interrupt Enable */
#define OSCCTRL_INTENCLR_OSC48MRDY (_U_(0x1) << OSCCTRL_INTENCLR_OSC48MRDY_Pos)
#define OSCCTRL_INTENCLR_DPLLLCKR_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLLLCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLCKR_Pos)
#define OSCCTRL_INTENCLR_DPLLLCKF_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLCKF_Pos)
#define OSCCTRL_INTENCLR_DPLLLTO_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DPLL Time Out Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLLLTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLTO_Pos)
#define OSCCTRL_INTENCLR_DPLLLDRTO_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DPLL Ratio Ready Interrupt Enable */
#define OSCCTRL_INTENCLR_DPLLLDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLDRTO_Pos)
#define OSCCTRL_INTENCLR_MASK _U_(0x00000F13) /**< \brief (OSCCTRL_INTENCLR) MASK Register */
/* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSCFAIL:1; /*!< bit: 1 XOSC Clock Failure Detector Interrupt Enable */
uint32_t :2; /*!< bit: 2.. 3 Reserved */
uint32_t OSC48MRDY:1; /*!< bit: 4 OSC48M Ready Interrupt Enable */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 8 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 9 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 10 DPLL Time Out Interrupt Enable */
uint32_t DPLLLDRTO:1; /*!< bit: 11 DPLL Ratio Ready Interrupt Enable */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */
#define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */
#define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC Ready Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCRDY (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY_Pos)
#define OSCCTRL_INTENSET_XOSCFAIL_Pos 1 /**< \brief (OSCCTRL_INTENSET) XOSC Clock Failure Detector Interrupt Enable */
#define OSCCTRL_INTENSET_XOSCFAIL (_U_(0x1) << OSCCTRL_INTENSET_XOSCFAIL_Pos)
#define OSCCTRL_INTENSET_OSC48MRDY_Pos 4 /**< \brief (OSCCTRL_INTENSET) OSC48M Ready Interrupt Enable */
#define OSCCTRL_INTENSET_OSC48MRDY (_U_(0x1) << OSCCTRL_INTENSET_OSC48MRDY_Pos)
#define OSCCTRL_INTENSET_DPLLLCKR_Pos 8 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */
#define OSCCTRL_INTENSET_DPLLLCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLLLCKR_Pos)
#define OSCCTRL_INTENSET_DPLLLCKF_Pos 9 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */
#define OSCCTRL_INTENSET_DPLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLLLCKF_Pos)
#define OSCCTRL_INTENSET_DPLLLTO_Pos 10 /**< \brief (OSCCTRL_INTENSET) DPLL Time Out Interrupt Enable */
#define OSCCTRL_INTENSET_DPLLLTO (_U_(0x1) << OSCCTRL_INTENSET_DPLLLTO_Pos)
#define OSCCTRL_INTENSET_DPLLLDRTO_Pos 11 /**< \brief (OSCCTRL_INTENSET) DPLL Ratio Ready Interrupt Enable */
#define OSCCTRL_INTENSET_DPLLLDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLLLDRTO_Pos)
#define OSCCTRL_INTENSET_MASK _U_(0x00000F13) /**< \brief (OSCCTRL_INTENSET) MASK Register */
/* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
__I uint32_t XOSCFAIL:1; /*!< bit: 1 XOSC Clock Failure Detector */
__I uint32_t :2; /*!< bit: 2.. 3 Reserved */
__I uint32_t OSC48MRDY:1; /*!< bit: 4 OSC48M Ready */
__I uint32_t :3; /*!< bit: 5.. 7 Reserved */
__I uint32_t DPLLLCKR:1; /*!< bit: 8 DPLL Lock Rise */
__I uint32_t DPLLLCKF:1; /*!< bit: 9 DPLL Lock Fall */
__I uint32_t DPLLLTO:1; /*!< bit: 10 DPLL Timeout */
__I uint32_t DPLLLDRTO:1; /*!< bit: 11 DPLL Ratio Ready */
__I uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
#define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC Ready */
#define OSCCTRL_INTFLAG_XOSCRDY (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY_Pos)
#define OSCCTRL_INTFLAG_XOSCFAIL_Pos 1 /**< \brief (OSCCTRL_INTFLAG) XOSC Clock Failure Detector */
#define OSCCTRL_INTFLAG_XOSCFAIL (_U_(0x1) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)
#define OSCCTRL_INTFLAG_OSC48MRDY_Pos 4 /**< \brief (OSCCTRL_INTFLAG) OSC48M Ready */
#define OSCCTRL_INTFLAG_OSC48MRDY (_U_(0x1) << OSCCTRL_INTFLAG_OSC48MRDY_Pos)
#define OSCCTRL_INTFLAG_DPLLLCKR_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Rise */
#define OSCCTRL_INTFLAG_DPLLLCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLCKR_Pos)
#define OSCCTRL_INTFLAG_DPLLLCKF_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Fall */
#define OSCCTRL_INTFLAG_DPLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLCKF_Pos)
#define OSCCTRL_INTFLAG_DPLLLTO_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DPLL Timeout */
#define OSCCTRL_INTFLAG_DPLLLTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLTO_Pos)
#define OSCCTRL_INTFLAG_DPLLLDRTO_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DPLL Ratio Ready */
#define OSCCTRL_INTFLAG_DPLLLDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLDRTO_Pos)
#define OSCCTRL_INTFLAG_MASK _U_(0x00000F13) /**< \brief (OSCCTRL_INTFLAG) MASK Register */
/* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSCFAIL:1; /*!< bit: 1 XOSC Clock Failure Detector */
uint32_t XOSCCKSW:1; /*!< bit: 2 XOSC Clock Switch */
uint32_t :1; /*!< bit: 3 Reserved */
uint32_t OSC48MRDY:1; /*!< bit: 4 OSC48M Ready */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 8 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 9 DPLL Lock Fall */
uint32_t DPLLTO:1; /*!< bit: 10 DPLL Timeout */
uint32_t DPLLLDRTO:1; /*!< bit: 11 DPLL Ratio Ready */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_STATUS_OFFSET 0x0C /**< \brief (OSCCTRL_STATUS offset) Power and Clocks Status */
#define OSCCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Power and Clocks Status */
#define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC Ready */
#define OSCCTRL_STATUS_XOSCRDY (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY_Pos)
#define OSCCTRL_STATUS_XOSCFAIL_Pos 1 /**< \brief (OSCCTRL_STATUS) XOSC Clock Failure Detector */
#define OSCCTRL_STATUS_XOSCFAIL (_U_(0x1) << OSCCTRL_STATUS_XOSCFAIL_Pos)
#define OSCCTRL_STATUS_XOSCCKSW_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC Clock Switch */
#define OSCCTRL_STATUS_XOSCCKSW (_U_(0x1) << OSCCTRL_STATUS_XOSCCKSW_Pos)
#define OSCCTRL_STATUS_OSC48MRDY_Pos 4 /**< \brief (OSCCTRL_STATUS) OSC48M Ready */
#define OSCCTRL_STATUS_OSC48MRDY (_U_(0x1) << OSCCTRL_STATUS_OSC48MRDY_Pos)
#define OSCCTRL_STATUS_DPLLLCKR_Pos 8 /**< \brief (OSCCTRL_STATUS) DPLL Lock Rise */
#define OSCCTRL_STATUS_DPLLLCKR (_U_(0x1) << OSCCTRL_STATUS_DPLLLCKR_Pos)
#define OSCCTRL_STATUS_DPLLLCKF_Pos 9 /**< \brief (OSCCTRL_STATUS) DPLL Lock Fall */
#define OSCCTRL_STATUS_DPLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DPLLLCKF_Pos)
#define OSCCTRL_STATUS_DPLLTO_Pos 10 /**< \brief (OSCCTRL_STATUS) DPLL Timeout */
#define OSCCTRL_STATUS_DPLLTO (_U_(0x1) << OSCCTRL_STATUS_DPLLTO_Pos)
#define OSCCTRL_STATUS_DPLLLDRTO_Pos 11 /**< \brief (OSCCTRL_STATUS) DPLL Ratio Ready */
#define OSCCTRL_STATUS_DPLLLDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLLLDRTO_Pos)
#define OSCCTRL_STATUS_MASK _U_(0x00000F17) /**< \brief (OSCCTRL_STATUS) MASK Register */
/* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t CFDEN:1; /*!< bit: 3 Xosc Clock Failure Detecteor Enable */
uint16_t SWBEN:1; /*!< bit: 4 Xosc Clock Switch Enable */
uint16_t :1; /*!< bit: 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} OSCCTRL_XOSCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_XOSCCTRL_OFFSET 0x10 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator (XOSC) Control */
#define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x0080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */
#define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */
#define OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos)
#define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */
#define OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos)
#define OSCCTRL_XOSCCTRL_CFDEN_Pos 3 /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Failure Detecteor Enable */
#define OSCCTRL_XOSCCTRL_CFDEN (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos)
#define OSCCTRL_XOSCCTRL_SWBEN_Pos 4 /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable */
#define OSCCTRL_XOSCCTRL_SWBEN (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos)
#define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */
#define OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos)
#define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */
#define OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos)
#define OSCCTRL_XOSCCTRL_GAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Gain */
#define OSCCTRL_XOSCCTRL_GAIN_Msk (_U_(0x7) << OSCCTRL_XOSCCTRL_GAIN_Pos)
#define OSCCTRL_XOSCCTRL_GAIN(value) (OSCCTRL_XOSCCTRL_GAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_GAIN_Pos))
#define OSCCTRL_XOSCCTRL_AMPGC_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Amplitude Gain Control */
#define OSCCTRL_XOSCCTRL_AMPGC (_U_(0x1) << OSCCTRL_XOSCCTRL_AMPGC_Pos)
#define OSCCTRL_XOSCCTRL_STARTUP_Pos 12 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */
#define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos)
#define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos))
#define OSCCTRL_XOSCCTRL_MASK _U_(0xFFDE) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */
/* -------- OSCCTRL_CFDPRESC : (OSCCTRL Offset: 0x12) (R/W 8) Clock Failure Detector Prescaler -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CFDPRESC:3; /*!< bit: 0.. 2 Clock Failure Detector Prescaler */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_CFDPRESC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_CFDPRESC_OFFSET 0x12 /**< \brief (OSCCTRL_CFDPRESC offset) Clock Failure Detector Prescaler */
#define OSCCTRL_CFDPRESC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_CFDPRESC reset_value) Clock Failure Detector Prescaler */
#define OSCCTRL_CFDPRESC_CFDPRESC_Pos 0 /**< \brief (OSCCTRL_CFDPRESC) Clock Failure Detector Prescaler */
#define OSCCTRL_CFDPRESC_CFDPRESC_Msk (_U_(0x7) << OSCCTRL_CFDPRESC_CFDPRESC_Pos)
#define OSCCTRL_CFDPRESC_CFDPRESC(value) (OSCCTRL_CFDPRESC_CFDPRESC_Msk & ((value) << OSCCTRL_CFDPRESC_CFDPRESC_Pos))
#define OSCCTRL_CFDPRESC_MASK _U_(0x07) /**< \brief (OSCCTRL_CFDPRESC) MASK Register */
/* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x13) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_EVCTRL_OFFSET 0x13 /**< \brief (OSCCTRL_EVCTRL offset) Event Control */
#define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_EVCTRL reset_value) Event Control */
#define OSCCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock Failure Detector Event Output Enable */
#define OSCCTRL_EVCTRL_CFDEO (_U_(0x1) << OSCCTRL_EVCTRL_CFDEO_Pos)
#define OSCCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSCCTRL_EVCTRL) MASK Register */
/* -------- OSCCTRL_OSC48MCTRL : (OSCCTRL Offset: 0x14) (R/W 8) 48MHz Internal Oscillator (OSC48M) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_OSC48MCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_OSC48MCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_OSC48MCTRL offset) 48MHz Internal Oscillator (OSC48M) Control */
#define OSCCTRL_OSC48MCTRL_RESETVALUE _U_(0x82) /**< \brief (OSCCTRL_OSC48MCTRL reset_value) 48MHz Internal Oscillator (OSC48M) Control */
#define OSCCTRL_OSC48MCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_OSC48MCTRL) Oscillator Enable */
#define OSCCTRL_OSC48MCTRL_ENABLE (_U_(0x1) << OSCCTRL_OSC48MCTRL_ENABLE_Pos)
#define OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_OSC48MCTRL) Run in Standby */
#define OSCCTRL_OSC48MCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_OSC48MCTRL_RUNSTDBY_Pos)
#define OSCCTRL_OSC48MCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_OSC48MCTRL) On Demand Control */
#define OSCCTRL_OSC48MCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_OSC48MCTRL_ONDEMAND_Pos)
#define OSCCTRL_OSC48MCTRL_MASK _U_(0xC2) /**< \brief (OSCCTRL_OSC48MCTRL) MASK Register */
/* -------- OSCCTRL_OSC48MDIV : (OSCCTRL Offset: 0x15) (R/W 8) OSC48M Divider -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIV:4; /*!< bit: 0.. 3 OSC48M Division Factor */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_OSC48MDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_OSC48MDIV_OFFSET 0x15 /**< \brief (OSCCTRL_OSC48MDIV offset) OSC48M Divider */
#define OSCCTRL_OSC48MDIV_RESETVALUE _U_(0x0B) /**< \brief (OSCCTRL_OSC48MDIV reset_value) OSC48M Divider */
#define OSCCTRL_OSC48MDIV_DIV_Pos 0 /**< \brief (OSCCTRL_OSC48MDIV) OSC48M Division Factor */
#define OSCCTRL_OSC48MDIV_DIV_Msk (_U_(0xF) << OSCCTRL_OSC48MDIV_DIV_Pos)
#define OSCCTRL_OSC48MDIV_DIV(value) (OSCCTRL_OSC48MDIV_DIV_Msk & ((value) << OSCCTRL_OSC48MDIV_DIV_Pos))
#define OSCCTRL_OSC48MDIV_MASK _U_(0x0F) /**< \brief (OSCCTRL_OSC48MDIV) MASK Register */
/* -------- OSCCTRL_OSC48MSTUP : (OSCCTRL Offset: 0x16) (R/W 8) OSC48M Startup Time -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTUP:3; /*!< bit: 0.. 2 Startup Time */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_OSC48MSTUP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_OSC48MSTUP_OFFSET 0x16 /**< \brief (OSCCTRL_OSC48MSTUP offset) OSC48M Startup Time */
#define OSCCTRL_OSC48MSTUP_RESETVALUE _U_(0x07) /**< \brief (OSCCTRL_OSC48MSTUP reset_value) OSC48M Startup Time */
#define OSCCTRL_OSC48MSTUP_STARTUP_Pos 0 /**< \brief (OSCCTRL_OSC48MSTUP) Startup Time */
#define OSCCTRL_OSC48MSTUP_STARTUP_Msk (_U_(0x7) << OSCCTRL_OSC48MSTUP_STARTUP_Pos)
#define OSCCTRL_OSC48MSTUP_STARTUP(value) (OSCCTRL_OSC48MSTUP_STARTUP_Msk & ((value) << OSCCTRL_OSC48MSTUP_STARTUP_Pos))
#define OSCCTRL_OSC48MSTUP_MASK _U_(0x07) /**< \brief (OSCCTRL_OSC48MSTUP) MASK Register */
/* -------- OSCCTRL_OSC48MSYNCBUSY : (OSCCTRL Offset: 0x18) (R/ 32) OSC48M Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t OSC48MDIV:1; /*!< bit: 2 OSC48MDIV Synchronization Status */
uint32_t :29; /*!< bit: 3..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_OSC48MSYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_OSC48MSYNCBUSY_OFFSET 0x18 /**< \brief (OSCCTRL_OSC48MSYNCBUSY offset) OSC48M Synchronization Busy */
#define OSCCTRL_OSC48MSYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_OSC48MSYNCBUSY reset_value) OSC48M Synchronization Busy */
#define OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Pos 2 /**< \brief (OSCCTRL_OSC48MSYNCBUSY) OSC48MDIV Synchronization Status */
#define OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV (_U_(0x1) << OSCCTRL_OSC48MSYNCBUSY_OSC48MDIV_Pos)
#define OSCCTRL_OSC48MSYNCBUSY_MASK _U_(0x00000004) /**< \brief (OSCCTRL_OSC48MSYNCBUSY) MASK Register */
/* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DPLL Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLCTRLA_OFFSET 0x1C /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control */
#define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control */
#define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) Enable */
#define OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos)
#define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */
#define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos)
#define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand */
#define OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos)
#define OSCCTRL_DPLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */
/* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x20) (R/W 32) DPLL Ratio Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLRATIO_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLRATIO_OFFSET 0x20 /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */
#define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */
#define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */
#define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0xFFF) << OSCCTRL_DPLLRATIO_LDR_Pos)
#define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos))
#define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */
#define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0xF) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)
#define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos))
#define OSCCTRL_DPLLRATIO_MASK _U_(0x000F0FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */
/* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x24) (R/W 32) Digital Core Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLCTRLB_OFFSET 0x24 /**< \brief (OSCCTRL_DPLLCTRLB offset) Digital Core Configuration */
#define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) Digital Core Configuration */
#define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */
#define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0x3) << OSCCTRL_DPLLCTRLB_FILTER_Pos)
#define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos))
#define OSCCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (OSCCTRL_DPLLCTRLB) Low-Power Enable */
#define OSCCTRL_DPLLCTRLB_LPEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_LPEN_Pos)
#define OSCCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */
#define OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos)
#define OSCCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */
#define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x3) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)
#define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos))
#define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */
#define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos)
#define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos))
#define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */
#define OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos)
#define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */
#define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos)
#define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos))
#define OSCCTRL_DPLLCTRLB_MASK _U_(0x07FF173F) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */
/* -------- OSCCTRL_DPLLPRESC : (OSCCTRL Offset: 0x28) (R/W 8) DPLL Prescaler -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PRESC:2; /*!< bit: 0.. 1 Output Clock Prescaler */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLPRESC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLPRESC_OFFSET 0x28 /**< \brief (OSCCTRL_DPLLPRESC offset) DPLL Prescaler */
#define OSCCTRL_DPLLPRESC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DPLLPRESC reset_value) DPLL Prescaler */
#define OSCCTRL_DPLLPRESC_PRESC_Pos 0 /**< \brief (OSCCTRL_DPLLPRESC) Output Clock Prescaler */
#define OSCCTRL_DPLLPRESC_PRESC_Msk (_U_(0x3) << OSCCTRL_DPLLPRESC_PRESC_Pos)
#define OSCCTRL_DPLLPRESC_PRESC(value) (OSCCTRL_DPLLPRESC_PRESC_Msk & ((value) << OSCCTRL_DPLLPRESC_PRESC_Pos))
#define OSCCTRL_DPLLPRESC_PRESC_DIV1_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 1 */
#define OSCCTRL_DPLLPRESC_PRESC_DIV2_Val _U_(0x1) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 2 */
#define OSCCTRL_DPLLPRESC_PRESC_DIV4_Val _U_(0x2) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 4 */
#define OSCCTRL_DPLLPRESC_PRESC_DIV1 (OSCCTRL_DPLLPRESC_PRESC_DIV1_Val << OSCCTRL_DPLLPRESC_PRESC_Pos)
#define OSCCTRL_DPLLPRESC_PRESC_DIV2 (OSCCTRL_DPLLPRESC_PRESC_DIV2_Val << OSCCTRL_DPLLPRESC_PRESC_Pos)
#define OSCCTRL_DPLLPRESC_PRESC_DIV4 (OSCCTRL_DPLLPRESC_PRESC_DIV4_Val << OSCCTRL_DPLLPRESC_PRESC_Pos)
#define OSCCTRL_DPLLPRESC_MASK _U_(0x03) /**< \brief (OSCCTRL_DPLLPRESC) MASK Register */
/* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x2C) (R/ 8) DPLL Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */
uint8_t DPLLRATIO:1; /*!< bit: 2 DPLL Ratio Synchronization Status */
uint8_t DPLLPRESC:1; /*!< bit: 3 DPLL Prescaler Synchronization Status */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLSYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x2C /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */
#define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */
#define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */
#define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos)
#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Ratio Synchronization Status */
#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos)
#define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos 3 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Prescaler Synchronization Status */
#define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos)
#define OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x0E) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */
/* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x30) (R/ 8) DPLL Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
uint8_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} OSCCTRL_DPLLSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_DPLLSTATUS_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */
#define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */
#define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */
#define OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos)
#define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */
#define OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos)
#define OSCCTRL_DPLLSTATUS_MASK _U_(0x03) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */
/* -------- OSCCTRL_CAL48M : (OSCCTRL Offset: 0x38) (R/W 32) 48MHz Oscillator Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FCAL:6; /*!< bit: 0.. 5 Frequency Calibration (48MHz) */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t FRANGE:2; /*!< bit: 8.. 9 Frequency Range (48MHz) */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t TCAL:6; /*!< bit: 16..21 Temperature Calibration (48MHz) */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} OSCCTRL_CAL48M_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define OSCCTRL_CAL48M_OFFSET 0x38 /**< \brief (OSCCTRL_CAL48M offset) 48MHz Oscillator Calibration */
#define OSCCTRL_CAL48M_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_CAL48M reset_value) 48MHz Oscillator Calibration */
#define OSCCTRL_CAL48M_FCAL_Pos 0 /**< \brief (OSCCTRL_CAL48M) Frequency Calibration (48MHz) */
#define OSCCTRL_CAL48M_FCAL_Msk (_U_(0x3F) << OSCCTRL_CAL48M_FCAL_Pos)
#define OSCCTRL_CAL48M_FCAL(value) (OSCCTRL_CAL48M_FCAL_Msk & ((value) << OSCCTRL_CAL48M_FCAL_Pos))
#define OSCCTRL_CAL48M_FRANGE_Pos 8 /**< \brief (OSCCTRL_CAL48M) Frequency Range (48MHz) */
#define OSCCTRL_CAL48M_FRANGE_Msk (_U_(0x3) << OSCCTRL_CAL48M_FRANGE_Pos)
#define OSCCTRL_CAL48M_FRANGE(value) (OSCCTRL_CAL48M_FRANGE_Msk & ((value) << OSCCTRL_CAL48M_FRANGE_Pos))
#define OSCCTRL_CAL48M_TCAL_Pos 16 /**< \brief (OSCCTRL_CAL48M) Temperature Calibration (48MHz) */
#define OSCCTRL_CAL48M_TCAL_Msk (_U_(0x3F) << OSCCTRL_CAL48M_TCAL_Pos)
#define OSCCTRL_CAL48M_TCAL(value) (OSCCTRL_CAL48M_TCAL_Msk & ((value) << OSCCTRL_CAL48M_TCAL_Pos))
#define OSCCTRL_CAL48M_MASK _U_(0x003F033F) /**< \brief (OSCCTRL_CAL48M) MASK Register */
/** \brief OSCCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO OSCCTRL_XOSCCTRL_Type XOSCCTRL; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
__IO OSCCTRL_CFDPRESC_Type CFDPRESC; /**< \brief Offset: 0x12 (R/W 8) Clock Failure Detector Prescaler */
__IO OSCCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x13 (R/W 8) Event Control */
__IO OSCCTRL_OSC48MCTRL_Type OSC48MCTRL; /**< \brief Offset: 0x14 (R/W 8) 48MHz Internal Oscillator (OSC48M) Control */
__IO OSCCTRL_OSC48MDIV_Type OSC48MDIV; /**< \brief Offset: 0x15 (R/W 8) OSC48M Divider */
__IO OSCCTRL_OSC48MSTUP_Type OSC48MSTUP; /**< \brief Offset: 0x16 (R/W 8) OSC48M Startup Time */
RoReg8 Reserved1[0x1];
__I OSCCTRL_OSC48MSYNCBUSY_Type OSC48MSYNCBUSY; /**< \brief Offset: 0x18 (R/ 32) OSC48M Synchronization Busy */
__IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x1C (R/W 8) DPLL Control */
RoReg8 Reserved2[0x3];
__IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x20 (R/W 32) DPLL Ratio Control */
__IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x24 (R/W 32) Digital Core Configuration */
__IO OSCCTRL_DPLLPRESC_Type DPLLPRESC; /**< \brief Offset: 0x28 (R/W 8) DPLL Prescaler */
RoReg8 Reserved3[0x3];
__I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x2C (R/ 8) DPLL Synchronization Busy */
RoReg8 Reserved4[0x3];
__I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x30 (R/ 8) DPLL Status */
RoReg8 Reserved5[0x7];
__IO OSCCTRL_CAL48M_Type CAL48M; /**< \brief Offset: 0x38 (R/W 32) 48MHz Oscillator Calibration */
} Oscctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_OSCCTRL_COMPONENT_ */

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/**
* \file
*
* \brief Component description for PAC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PAC_COMPONENT_
#define _SAMC21_PAC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PAC */
/* ========================================================================== */
/** \addtogroup SAMC21_PAC Peripheral Access Controller */
/*@{*/
#define PAC_U2120
#define REV_PAC 0x110
/* -------- PAC_WRCTRL : (PAC Offset: 0x00) (R/W 32) Write control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PERID:16; /*!< bit: 0..15 Peripheral identifier */
uint32_t KEY:8; /*!< bit: 16..23 Peripheral access control key */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WRCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_WRCTRL_OFFSET 0x00 /**< \brief (PAC_WRCTRL offset) Write control */
#define PAC_WRCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WRCTRL reset_value) Write control */
#define PAC_WRCTRL_PERID_Pos 0 /**< \brief (PAC_WRCTRL) Peripheral identifier */
#define PAC_WRCTRL_PERID_Msk (_U_(0xFFFF) << PAC_WRCTRL_PERID_Pos)
#define PAC_WRCTRL_PERID(value) (PAC_WRCTRL_PERID_Msk & ((value) << PAC_WRCTRL_PERID_Pos))
#define PAC_WRCTRL_KEY_Pos 16 /**< \brief (PAC_WRCTRL) Peripheral access control key */
#define PAC_WRCTRL_KEY_Msk (_U_(0xFF) << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY(value) (PAC_WRCTRL_KEY_Msk & ((value) << PAC_WRCTRL_KEY_Pos))
#define PAC_WRCTRL_KEY_OFF_Val _U_(0x0) /**< \brief (PAC_WRCTRL) No action */
#define PAC_WRCTRL_KEY_CLR_Val _U_(0x1) /**< \brief (PAC_WRCTRL) Clear protection */
#define PAC_WRCTRL_KEY_SET_Val _U_(0x2) /**< \brief (PAC_WRCTRL) Set protection */
#define PAC_WRCTRL_KEY_SETLCK_Val _U_(0x3) /**< \brief (PAC_WRCTRL) Set and lock protection */
#define PAC_WRCTRL_KEY_OFF (PAC_WRCTRL_KEY_OFF_Val << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY_CLR (PAC_WRCTRL_KEY_CLR_Val << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY_SET (PAC_WRCTRL_KEY_SET_Val << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_KEY_SETLCK (PAC_WRCTRL_KEY_SETLCK_Val << PAC_WRCTRL_KEY_Pos)
#define PAC_WRCTRL_MASK _U_(0x00FFFFFF) /**< \brief (PAC_WRCTRL) MASK Register */
/* -------- PAC_EVCTRL : (PAC Offset: 0x04) (R/W 8) Event control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ERREO:1; /*!< bit: 0 Peripheral acess error event output */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_EVCTRL_OFFSET 0x04 /**< \brief (PAC_EVCTRL offset) Event control */
#define PAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (PAC_EVCTRL reset_value) Event control */
#define PAC_EVCTRL_ERREO_Pos 0 /**< \brief (PAC_EVCTRL) Peripheral acess error event output */
#define PAC_EVCTRL_ERREO (_U_(0x1) << PAC_EVCTRL_ERREO_Pos)
#define PAC_EVCTRL_MASK _U_(0x01) /**< \brief (PAC_EVCTRL) MASK Register */
/* -------- PAC_INTENCLR : (PAC Offset: 0x08) (R/W 8) Interrupt enable clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt disable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTENCLR_OFFSET 0x08 /**< \brief (PAC_INTENCLR offset) Interrupt enable clear */
#define PAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENCLR reset_value) Interrupt enable clear */
#define PAC_INTENCLR_ERR_Pos 0 /**< \brief (PAC_INTENCLR) Peripheral access error interrupt disable */
#define PAC_INTENCLR_ERR (_U_(0x1) << PAC_INTENCLR_ERR_Pos)
#define PAC_INTENCLR_MASK _U_(0x01) /**< \brief (PAC_INTENCLR) MASK Register */
/* -------- PAC_INTENSET : (PAC Offset: 0x09) (R/W 8) Interrupt enable set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ERR:1; /*!< bit: 0 Peripheral access error interrupt enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTENSET_OFFSET 0x09 /**< \brief (PAC_INTENSET offset) Interrupt enable set */
#define PAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (PAC_INTENSET reset_value) Interrupt enable set */
#define PAC_INTENSET_ERR_Pos 0 /**< \brief (PAC_INTENSET) Peripheral access error interrupt enable */
#define PAC_INTENSET_ERR (_U_(0x1) << PAC_INTENSET_ERR_Pos)
#define PAC_INTENSET_MASK _U_(0x01) /**< \brief (PAC_INTENSET) MASK Register */
/* -------- PAC_INTFLAGAHB : (PAC Offset: 0x10) (R/W 32) Bridge interrupt flag status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t FLASH_:1; /*!< bit: 0 FLASH */
__I uint32_t HSRAMCM0P_:1; /*!< bit: 1 HSRAMCM0P */
__I uint32_t HSRAMDSU_:1; /*!< bit: 2 HSRAMDSU */
__I uint32_t HPB1_:1; /*!< bit: 3 HPB1 */
__I uint32_t HPB0_:1; /*!< bit: 4 HPB0 */
__I uint32_t HPB2_:1; /*!< bit: 5 HPB2 */
__I uint32_t LPRAMDMAC_:1; /*!< bit: 6 LPRAMDMAC */
__I uint32_t DIVAS_:1; /*!< bit: 7 DIVAS */
__I uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_INTFLAGAHB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTFLAGAHB_OFFSET 0x10 /**< \brief (PAC_INTFLAGAHB offset) Bridge interrupt flag status */
#define PAC_INTFLAGAHB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGAHB reset_value) Bridge interrupt flag status */
#define PAC_INTFLAGAHB_FLASH_Pos 0 /**< \brief (PAC_INTFLAGAHB) FLASH */
#define PAC_INTFLAGAHB_FLASH (_U_(0x1) << PAC_INTFLAGAHB_FLASH_Pos)
#define PAC_INTFLAGAHB_HSRAMCM0P_Pos 1 /**< \brief (PAC_INTFLAGAHB) HSRAMCM0P */
#define PAC_INTFLAGAHB_HSRAMCM0P (_U_(0x1) << PAC_INTFLAGAHB_HSRAMCM0P_Pos)
#define PAC_INTFLAGAHB_HSRAMDSU_Pos 2 /**< \brief (PAC_INTFLAGAHB) HSRAMDSU */
#define PAC_INTFLAGAHB_HSRAMDSU (_U_(0x1) << PAC_INTFLAGAHB_HSRAMDSU_Pos)
#define PAC_INTFLAGAHB_HPB1_Pos 3 /**< \brief (PAC_INTFLAGAHB) HPB1 */
#define PAC_INTFLAGAHB_HPB1 (_U_(0x1) << PAC_INTFLAGAHB_HPB1_Pos)
#define PAC_INTFLAGAHB_HPB0_Pos 4 /**< \brief (PAC_INTFLAGAHB) HPB0 */
#define PAC_INTFLAGAHB_HPB0 (_U_(0x1) << PAC_INTFLAGAHB_HPB0_Pos)
#define PAC_INTFLAGAHB_HPB2_Pos 5 /**< \brief (PAC_INTFLAGAHB) HPB2 */
#define PAC_INTFLAGAHB_HPB2 (_U_(0x1) << PAC_INTFLAGAHB_HPB2_Pos)
#define PAC_INTFLAGAHB_LPRAMDMAC_Pos 6 /**< \brief (PAC_INTFLAGAHB) LPRAMDMAC */
#define PAC_INTFLAGAHB_LPRAMDMAC (_U_(0x1) << PAC_INTFLAGAHB_LPRAMDMAC_Pos)
#define PAC_INTFLAGAHB_DIVAS_Pos 7 /**< \brief (PAC_INTFLAGAHB) DIVAS */
#define PAC_INTFLAGAHB_DIVAS (_U_(0x1) << PAC_INTFLAGAHB_DIVAS_Pos)
#define PAC_INTFLAGAHB_MASK _U_(0x000000FF) /**< \brief (PAC_INTFLAGAHB) MASK Register */
/* -------- PAC_INTFLAGA : (PAC Offset: 0x14) (R/W 32) Peripheral interrupt flag status - Bridge A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t PAC_:1; /*!< bit: 0 PAC */
__I uint32_t PM_:1; /*!< bit: 1 PM */
__I uint32_t MCLK_:1; /*!< bit: 2 MCLK */
__I uint32_t RSTC_:1; /*!< bit: 3 RSTC */
__I uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL */
__I uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL */
__I uint32_t SUPC_:1; /*!< bit: 6 SUPC */
__I uint32_t GCLK_:1; /*!< bit: 7 GCLK */
__I uint32_t WDT_:1; /*!< bit: 8 WDT */
__I uint32_t RTC_:1; /*!< bit: 9 RTC */
__I uint32_t EIC_:1; /*!< bit: 10 EIC */
__I uint32_t FREQM_:1; /*!< bit: 11 FREQM */
__I uint32_t TSENS_:1; /*!< bit: 12 TSENS */
__I uint32_t :19; /*!< bit: 13..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_INTFLAGA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTFLAGA_OFFSET 0x14 /**< \brief (PAC_INTFLAGA offset) Peripheral interrupt flag status - Bridge A */
#define PAC_INTFLAGA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGA reset_value) Peripheral interrupt flag status - Bridge A */
#define PAC_INTFLAGA_PAC_Pos 0 /**< \brief (PAC_INTFLAGA) PAC */
#define PAC_INTFLAGA_PAC (_U_(0x1) << PAC_INTFLAGA_PAC_Pos)
#define PAC_INTFLAGA_PM_Pos 1 /**< \brief (PAC_INTFLAGA) PM */
#define PAC_INTFLAGA_PM (_U_(0x1) << PAC_INTFLAGA_PM_Pos)
#define PAC_INTFLAGA_MCLK_Pos 2 /**< \brief (PAC_INTFLAGA) MCLK */
#define PAC_INTFLAGA_MCLK (_U_(0x1) << PAC_INTFLAGA_MCLK_Pos)
#define PAC_INTFLAGA_RSTC_Pos 3 /**< \brief (PAC_INTFLAGA) RSTC */
#define PAC_INTFLAGA_RSTC (_U_(0x1) << PAC_INTFLAGA_RSTC_Pos)
#define PAC_INTFLAGA_OSCCTRL_Pos 4 /**< \brief (PAC_INTFLAGA) OSCCTRL */
#define PAC_INTFLAGA_OSCCTRL (_U_(0x1) << PAC_INTFLAGA_OSCCTRL_Pos)
#define PAC_INTFLAGA_OSC32KCTRL_Pos 5 /**< \brief (PAC_INTFLAGA) OSC32KCTRL */
#define PAC_INTFLAGA_OSC32KCTRL (_U_(0x1) << PAC_INTFLAGA_OSC32KCTRL_Pos)
#define PAC_INTFLAGA_SUPC_Pos 6 /**< \brief (PAC_INTFLAGA) SUPC */
#define PAC_INTFLAGA_SUPC (_U_(0x1) << PAC_INTFLAGA_SUPC_Pos)
#define PAC_INTFLAGA_GCLK_Pos 7 /**< \brief (PAC_INTFLAGA) GCLK */
#define PAC_INTFLAGA_GCLK (_U_(0x1) << PAC_INTFLAGA_GCLK_Pos)
#define PAC_INTFLAGA_WDT_Pos 8 /**< \brief (PAC_INTFLAGA) WDT */
#define PAC_INTFLAGA_WDT (_U_(0x1) << PAC_INTFLAGA_WDT_Pos)
#define PAC_INTFLAGA_RTC_Pos 9 /**< \brief (PAC_INTFLAGA) RTC */
#define PAC_INTFLAGA_RTC (_U_(0x1) << PAC_INTFLAGA_RTC_Pos)
#define PAC_INTFLAGA_EIC_Pos 10 /**< \brief (PAC_INTFLAGA) EIC */
#define PAC_INTFLAGA_EIC (_U_(0x1) << PAC_INTFLAGA_EIC_Pos)
#define PAC_INTFLAGA_FREQM_Pos 11 /**< \brief (PAC_INTFLAGA) FREQM */
#define PAC_INTFLAGA_FREQM (_U_(0x1) << PAC_INTFLAGA_FREQM_Pos)
#define PAC_INTFLAGA_TSENS_Pos 12 /**< \brief (PAC_INTFLAGA) TSENS */
#define PAC_INTFLAGA_TSENS (_U_(0x1) << PAC_INTFLAGA_TSENS_Pos)
#define PAC_INTFLAGA_MASK _U_(0x00001FFF) /**< \brief (PAC_INTFLAGA) MASK Register */
/* -------- PAC_INTFLAGB : (PAC Offset: 0x18) (R/W 32) Peripheral interrupt flag status - Bridge B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t PORT_:1; /*!< bit: 0 PORT */
__I uint32_t DSU_:1; /*!< bit: 1 DSU */
__I uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL */
__I uint32_t DMAC_:1; /*!< bit: 3 DMAC */
__I uint32_t MTB_:1; /*!< bit: 4 MTB */
__I uint32_t HMATRIXHS_:1; /*!< bit: 5 HMATRIXHS */
__I uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_INTFLAGB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTFLAGB_OFFSET 0x18 /**< \brief (PAC_INTFLAGB offset) Peripheral interrupt flag status - Bridge B */
#define PAC_INTFLAGB_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGB reset_value) Peripheral interrupt flag status - Bridge B */
#define PAC_INTFLAGB_PORT_Pos 0 /**< \brief (PAC_INTFLAGB) PORT */
#define PAC_INTFLAGB_PORT (_U_(0x1) << PAC_INTFLAGB_PORT_Pos)
#define PAC_INTFLAGB_DSU_Pos 1 /**< \brief (PAC_INTFLAGB) DSU */
#define PAC_INTFLAGB_DSU (_U_(0x1) << PAC_INTFLAGB_DSU_Pos)
#define PAC_INTFLAGB_NVMCTRL_Pos 2 /**< \brief (PAC_INTFLAGB) NVMCTRL */
#define PAC_INTFLAGB_NVMCTRL (_U_(0x1) << PAC_INTFLAGB_NVMCTRL_Pos)
#define PAC_INTFLAGB_DMAC_Pos 3 /**< \brief (PAC_INTFLAGB) DMAC */
#define PAC_INTFLAGB_DMAC (_U_(0x1) << PAC_INTFLAGB_DMAC_Pos)
#define PAC_INTFLAGB_MTB_Pos 4 /**< \brief (PAC_INTFLAGB) MTB */
#define PAC_INTFLAGB_MTB (_U_(0x1) << PAC_INTFLAGB_MTB_Pos)
#define PAC_INTFLAGB_HMATRIXHS_Pos 5 /**< \brief (PAC_INTFLAGB) HMATRIXHS */
#define PAC_INTFLAGB_HMATRIXHS (_U_(0x1) << PAC_INTFLAGB_HMATRIXHS_Pos)
#define PAC_INTFLAGB_MASK _U_(0x0000003F) /**< \brief (PAC_INTFLAGB) MASK Register */
/* -------- PAC_INTFLAGC : (PAC Offset: 0x1C) (R/W 32) Peripheral interrupt flag status - Bridge C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t EVSYS_:1; /*!< bit: 0 EVSYS */
__I uint32_t SERCOM0_:1; /*!< bit: 1 SERCOM0 */
__I uint32_t SERCOM1_:1; /*!< bit: 2 SERCOM1 */
__I uint32_t SERCOM2_:1; /*!< bit: 3 SERCOM2 */
__I uint32_t SERCOM3_:1; /*!< bit: 4 SERCOM3 */
__I uint32_t SERCOM4_:1; /*!< bit: 5 SERCOM4 */
__I uint32_t SERCOM5_:1; /*!< bit: 6 SERCOM5 */
__I uint32_t CAN0_:1; /*!< bit: 7 CAN0 */
__I uint32_t CAN1_:1; /*!< bit: 8 CAN1 */
__I uint32_t TCC0_:1; /*!< bit: 9 TCC0 */
__I uint32_t TCC1_:1; /*!< bit: 10 TCC1 */
__I uint32_t TCC2_:1; /*!< bit: 11 TCC2 */
__I uint32_t TC0_:1; /*!< bit: 12 TC0 */
__I uint32_t TC1_:1; /*!< bit: 13 TC1 */
__I uint32_t TC2_:1; /*!< bit: 14 TC2 */
__I uint32_t TC3_:1; /*!< bit: 15 TC3 */
__I uint32_t TC4_:1; /*!< bit: 16 TC4 */
__I uint32_t ADC0_:1; /*!< bit: 17 ADC0 */
__I uint32_t ADC1_:1; /*!< bit: 18 ADC1 */
__I uint32_t SDADC_:1; /*!< bit: 19 SDADC */
__I uint32_t AC_:1; /*!< bit: 20 AC */
__I uint32_t DAC_:1; /*!< bit: 21 DAC */
__I uint32_t PTC_:1; /*!< bit: 22 PTC */
__I uint32_t CCL_:1; /*!< bit: 23 CCL */
__I uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_INTFLAGC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_INTFLAGC_OFFSET 0x1C /**< \brief (PAC_INTFLAGC offset) Peripheral interrupt flag status - Bridge C */
#define PAC_INTFLAGC_RESETVALUE _U_(0x00000000) /**< \brief (PAC_INTFLAGC reset_value) Peripheral interrupt flag status - Bridge C */
#define PAC_INTFLAGC_EVSYS_Pos 0 /**< \brief (PAC_INTFLAGC) EVSYS */
#define PAC_INTFLAGC_EVSYS (_U_(0x1) << PAC_INTFLAGC_EVSYS_Pos)
#define PAC_INTFLAGC_SERCOM0_Pos 1 /**< \brief (PAC_INTFLAGC) SERCOM0 */
#define PAC_INTFLAGC_SERCOM0 (_U_(0x1) << PAC_INTFLAGC_SERCOM0_Pos)
#define PAC_INTFLAGC_SERCOM1_Pos 2 /**< \brief (PAC_INTFLAGC) SERCOM1 */
#define PAC_INTFLAGC_SERCOM1 (_U_(0x1) << PAC_INTFLAGC_SERCOM1_Pos)
#define PAC_INTFLAGC_SERCOM2_Pos 3 /**< \brief (PAC_INTFLAGC) SERCOM2 */
#define PAC_INTFLAGC_SERCOM2 (_U_(0x1) << PAC_INTFLAGC_SERCOM2_Pos)
#define PAC_INTFLAGC_SERCOM3_Pos 4 /**< \brief (PAC_INTFLAGC) SERCOM3 */
#define PAC_INTFLAGC_SERCOM3 (_U_(0x1) << PAC_INTFLAGC_SERCOM3_Pos)
#define PAC_INTFLAGC_SERCOM4_Pos 5 /**< \brief (PAC_INTFLAGC) SERCOM4 */
#define PAC_INTFLAGC_SERCOM4 (_U_(0x1) << PAC_INTFLAGC_SERCOM4_Pos)
#define PAC_INTFLAGC_SERCOM5_Pos 6 /**< \brief (PAC_INTFLAGC) SERCOM5 */
#define PAC_INTFLAGC_SERCOM5 (_U_(0x1) << PAC_INTFLAGC_SERCOM5_Pos)
#define PAC_INTFLAGC_CAN0_Pos 7 /**< \brief (PAC_INTFLAGC) CAN0 */
#define PAC_INTFLAGC_CAN0 (_U_(0x1) << PAC_INTFLAGC_CAN0_Pos)
#define PAC_INTFLAGC_CAN1_Pos 8 /**< \brief (PAC_INTFLAGC) CAN1 */
#define PAC_INTFLAGC_CAN1 (_U_(0x1) << PAC_INTFLAGC_CAN1_Pos)
#define PAC_INTFLAGC_TCC0_Pos 9 /**< \brief (PAC_INTFLAGC) TCC0 */
#define PAC_INTFLAGC_TCC0 (_U_(0x1) << PAC_INTFLAGC_TCC0_Pos)
#define PAC_INTFLAGC_TCC1_Pos 10 /**< \brief (PAC_INTFLAGC) TCC1 */
#define PAC_INTFLAGC_TCC1 (_U_(0x1) << PAC_INTFLAGC_TCC1_Pos)
#define PAC_INTFLAGC_TCC2_Pos 11 /**< \brief (PAC_INTFLAGC) TCC2 */
#define PAC_INTFLAGC_TCC2 (_U_(0x1) << PAC_INTFLAGC_TCC2_Pos)
#define PAC_INTFLAGC_TC0_Pos 12 /**< \brief (PAC_INTFLAGC) TC0 */
#define PAC_INTFLAGC_TC0 (_U_(0x1) << PAC_INTFLAGC_TC0_Pos)
#define PAC_INTFLAGC_TC1_Pos 13 /**< \brief (PAC_INTFLAGC) TC1 */
#define PAC_INTFLAGC_TC1 (_U_(0x1) << PAC_INTFLAGC_TC1_Pos)
#define PAC_INTFLAGC_TC2_Pos 14 /**< \brief (PAC_INTFLAGC) TC2 */
#define PAC_INTFLAGC_TC2 (_U_(0x1) << PAC_INTFLAGC_TC2_Pos)
#define PAC_INTFLAGC_TC3_Pos 15 /**< \brief (PAC_INTFLAGC) TC3 */
#define PAC_INTFLAGC_TC3 (_U_(0x1) << PAC_INTFLAGC_TC3_Pos)
#define PAC_INTFLAGC_TC4_Pos 16 /**< \brief (PAC_INTFLAGC) TC4 */
#define PAC_INTFLAGC_TC4 (_U_(0x1) << PAC_INTFLAGC_TC4_Pos)
#define PAC_INTFLAGC_ADC0_Pos 17 /**< \brief (PAC_INTFLAGC) ADC0 */
#define PAC_INTFLAGC_ADC0 (_U_(0x1) << PAC_INTFLAGC_ADC0_Pos)
#define PAC_INTFLAGC_ADC1_Pos 18 /**< \brief (PAC_INTFLAGC) ADC1 */
#define PAC_INTFLAGC_ADC1 (_U_(0x1) << PAC_INTFLAGC_ADC1_Pos)
#define PAC_INTFLAGC_SDADC_Pos 19 /**< \brief (PAC_INTFLAGC) SDADC */
#define PAC_INTFLAGC_SDADC (_U_(0x1) << PAC_INTFLAGC_SDADC_Pos)
#define PAC_INTFLAGC_AC_Pos 20 /**< \brief (PAC_INTFLAGC) AC */
#define PAC_INTFLAGC_AC (_U_(0x1) << PAC_INTFLAGC_AC_Pos)
#define PAC_INTFLAGC_DAC_Pos 21 /**< \brief (PAC_INTFLAGC) DAC */
#define PAC_INTFLAGC_DAC (_U_(0x1) << PAC_INTFLAGC_DAC_Pos)
#define PAC_INTFLAGC_PTC_Pos 22 /**< \brief (PAC_INTFLAGC) PTC */
#define PAC_INTFLAGC_PTC (_U_(0x1) << PAC_INTFLAGC_PTC_Pos)
#define PAC_INTFLAGC_CCL_Pos 23 /**< \brief (PAC_INTFLAGC) CCL */
#define PAC_INTFLAGC_CCL (_U_(0x1) << PAC_INTFLAGC_CCL_Pos)
#define PAC_INTFLAGC_MASK _U_(0x00FFFFFF) /**< \brief (PAC_INTFLAGC) MASK Register */
/* -------- PAC_STATUSA : (PAC Offset: 0x34) (R/ 32) Peripheral write protection status - Bridge A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC_:1; /*!< bit: 0 PAC APB Protect Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Protect Enable */
uint32_t MCLK_:1; /*!< bit: 2 MCLK APB Protect Enable */
uint32_t RSTC_:1; /*!< bit: 3 RSTC APB Protect Enable */
uint32_t OSCCTRL_:1; /*!< bit: 4 OSCCTRL APB Protect Enable */
uint32_t OSC32KCTRL_:1; /*!< bit: 5 OSC32KCTRL APB Protect Enable */
uint32_t SUPC_:1; /*!< bit: 6 SUPC APB Protect Enable */
uint32_t GCLK_:1; /*!< bit: 7 GCLK APB Protect Enable */
uint32_t WDT_:1; /*!< bit: 8 WDT APB Protect Enable */
uint32_t RTC_:1; /*!< bit: 9 RTC APB Protect Enable */
uint32_t EIC_:1; /*!< bit: 10 EIC APB Protect Enable */
uint32_t FREQM_:1; /*!< bit: 11 FREQM APB Protect Enable */
uint32_t TSENS_:1; /*!< bit: 12 TSENS APB Protect Enable */
uint32_t :19; /*!< bit: 13..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_STATUSA_OFFSET 0x34 /**< \brief (PAC_STATUSA offset) Peripheral write protection status - Bridge A */
#define PAC_STATUSA_RESETVALUE _U_(0x00000000) /**< \brief (PAC_STATUSA reset_value) Peripheral write protection status - Bridge A */
#define PAC_STATUSA_PAC_Pos 0 /**< \brief (PAC_STATUSA) PAC APB Protect Enable */
#define PAC_STATUSA_PAC (_U_(0x1) << PAC_STATUSA_PAC_Pos)
#define PAC_STATUSA_PM_Pos 1 /**< \brief (PAC_STATUSA) PM APB Protect Enable */
#define PAC_STATUSA_PM (_U_(0x1) << PAC_STATUSA_PM_Pos)
#define PAC_STATUSA_MCLK_Pos 2 /**< \brief (PAC_STATUSA) MCLK APB Protect Enable */
#define PAC_STATUSA_MCLK (_U_(0x1) << PAC_STATUSA_MCLK_Pos)
#define PAC_STATUSA_RSTC_Pos 3 /**< \brief (PAC_STATUSA) RSTC APB Protect Enable */
#define PAC_STATUSA_RSTC (_U_(0x1) << PAC_STATUSA_RSTC_Pos)
#define PAC_STATUSA_OSCCTRL_Pos 4 /**< \brief (PAC_STATUSA) OSCCTRL APB Protect Enable */
#define PAC_STATUSA_OSCCTRL (_U_(0x1) << PAC_STATUSA_OSCCTRL_Pos)
#define PAC_STATUSA_OSC32KCTRL_Pos 5 /**< \brief (PAC_STATUSA) OSC32KCTRL APB Protect Enable */
#define PAC_STATUSA_OSC32KCTRL (_U_(0x1) << PAC_STATUSA_OSC32KCTRL_Pos)
#define PAC_STATUSA_SUPC_Pos 6 /**< \brief (PAC_STATUSA) SUPC APB Protect Enable */
#define PAC_STATUSA_SUPC (_U_(0x1) << PAC_STATUSA_SUPC_Pos)
#define PAC_STATUSA_GCLK_Pos 7 /**< \brief (PAC_STATUSA) GCLK APB Protect Enable */
#define PAC_STATUSA_GCLK (_U_(0x1) << PAC_STATUSA_GCLK_Pos)
#define PAC_STATUSA_WDT_Pos 8 /**< \brief (PAC_STATUSA) WDT APB Protect Enable */
#define PAC_STATUSA_WDT (_U_(0x1) << PAC_STATUSA_WDT_Pos)
#define PAC_STATUSA_RTC_Pos 9 /**< \brief (PAC_STATUSA) RTC APB Protect Enable */
#define PAC_STATUSA_RTC (_U_(0x1) << PAC_STATUSA_RTC_Pos)
#define PAC_STATUSA_EIC_Pos 10 /**< \brief (PAC_STATUSA) EIC APB Protect Enable */
#define PAC_STATUSA_EIC (_U_(0x1) << PAC_STATUSA_EIC_Pos)
#define PAC_STATUSA_FREQM_Pos 11 /**< \brief (PAC_STATUSA) FREQM APB Protect Enable */
#define PAC_STATUSA_FREQM (_U_(0x1) << PAC_STATUSA_FREQM_Pos)
#define PAC_STATUSA_TSENS_Pos 12 /**< \brief (PAC_STATUSA) TSENS APB Protect Enable */
#define PAC_STATUSA_TSENS (_U_(0x1) << PAC_STATUSA_TSENS_Pos)
#define PAC_STATUSA_MASK _U_(0x00001FFF) /**< \brief (PAC_STATUSA) MASK Register */
/* -------- PAC_STATUSB : (PAC Offset: 0x38) (R/ 32) Peripheral write protection status - Bridge B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PORT_:1; /*!< bit: 0 PORT APB Protect Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Protect Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Protect Enable */
uint32_t DMAC_:1; /*!< bit: 3 DMAC APB Protect Enable */
uint32_t MTB_:1; /*!< bit: 4 MTB APB Protect Enable */
uint32_t HMATRIXHS_:1; /*!< bit: 5 HMATRIXHS APB Protect Enable */
uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_STATUSB_OFFSET 0x38 /**< \brief (PAC_STATUSB offset) Peripheral write protection status - Bridge B */
#define PAC_STATUSB_RESETVALUE _U_(0x00000002) /**< \brief (PAC_STATUSB reset_value) Peripheral write protection status - Bridge B */
#define PAC_STATUSB_PORT_Pos 0 /**< \brief (PAC_STATUSB) PORT APB Protect Enable */
#define PAC_STATUSB_PORT (_U_(0x1) << PAC_STATUSB_PORT_Pos)
#define PAC_STATUSB_DSU_Pos 1 /**< \brief (PAC_STATUSB) DSU APB Protect Enable */
#define PAC_STATUSB_DSU (_U_(0x1) << PAC_STATUSB_DSU_Pos)
#define PAC_STATUSB_NVMCTRL_Pos 2 /**< \brief (PAC_STATUSB) NVMCTRL APB Protect Enable */
#define PAC_STATUSB_NVMCTRL (_U_(0x1) << PAC_STATUSB_NVMCTRL_Pos)
#define PAC_STATUSB_DMAC_Pos 3 /**< \brief (PAC_STATUSB) DMAC APB Protect Enable */
#define PAC_STATUSB_DMAC (_U_(0x1) << PAC_STATUSB_DMAC_Pos)
#define PAC_STATUSB_MTB_Pos 4 /**< \brief (PAC_STATUSB) MTB APB Protect Enable */
#define PAC_STATUSB_MTB (_U_(0x1) << PAC_STATUSB_MTB_Pos)
#define PAC_STATUSB_HMATRIXHS_Pos 5 /**< \brief (PAC_STATUSB) HMATRIXHS APB Protect Enable */
#define PAC_STATUSB_HMATRIXHS (_U_(0x1) << PAC_STATUSB_HMATRIXHS_Pos)
#define PAC_STATUSB_MASK _U_(0x0000003F) /**< \brief (PAC_STATUSB) MASK Register */
/* -------- PAC_STATUSC : (PAC Offset: 0x3C) (R/ 32) Peripheral write protection status - Bridge C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EVSYS_:1; /*!< bit: 0 EVSYS APB Protect Enable */
uint32_t SERCOM0_:1; /*!< bit: 1 SERCOM0 APB Protect Enable */
uint32_t SERCOM1_:1; /*!< bit: 2 SERCOM1 APB Protect Enable */
uint32_t SERCOM2_:1; /*!< bit: 3 SERCOM2 APB Protect Enable */
uint32_t SERCOM3_:1; /*!< bit: 4 SERCOM3 APB Protect Enable */
uint32_t SERCOM4_:1; /*!< bit: 5 SERCOM4 APB Protect Enable */
uint32_t SERCOM5_:1; /*!< bit: 6 SERCOM5 APB Protect Enable */
uint32_t CAN0_:1; /*!< bit: 7 CAN0 APB Protect Enable */
uint32_t CAN1_:1; /*!< bit: 8 CAN1 APB Protect Enable */
uint32_t TCC0_:1; /*!< bit: 9 TCC0 APB Protect Enable */
uint32_t TCC1_:1; /*!< bit: 10 TCC1 APB Protect Enable */
uint32_t TCC2_:1; /*!< bit: 11 TCC2 APB Protect Enable */
uint32_t TC0_:1; /*!< bit: 12 TC0 APB Protect Enable */
uint32_t TC1_:1; /*!< bit: 13 TC1 APB Protect Enable */
uint32_t TC2_:1; /*!< bit: 14 TC2 APB Protect Enable */
uint32_t TC3_:1; /*!< bit: 15 TC3 APB Protect Enable */
uint32_t TC4_:1; /*!< bit: 16 TC4 APB Protect Enable */
uint32_t ADC0_:1; /*!< bit: 17 ADC0 APB Protect Enable */
uint32_t ADC1_:1; /*!< bit: 18 ADC1 APB Protect Enable */
uint32_t SDADC_:1; /*!< bit: 19 SDADC APB Protect Enable */
uint32_t AC_:1; /*!< bit: 20 AC APB Protect Enable */
uint32_t DAC_:1; /*!< bit: 21 DAC APB Protect Enable */
uint32_t PTC_:1; /*!< bit: 22 PTC APB Protect Enable */
uint32_t CCL_:1; /*!< bit: 23 CCL APB Protect Enable */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PAC_STATUSC_OFFSET 0x3C /**< \brief (PAC_STATUSC offset) Peripheral write protection status - Bridge C */
#define PAC_STATUSC_RESETVALUE _U_(0x02000000) /**< \brief (PAC_STATUSC reset_value) Peripheral write protection status - Bridge C */
#define PAC_STATUSC_EVSYS_Pos 0 /**< \brief (PAC_STATUSC) EVSYS APB Protect Enable */
#define PAC_STATUSC_EVSYS (_U_(0x1) << PAC_STATUSC_EVSYS_Pos)
#define PAC_STATUSC_SERCOM0_Pos 1 /**< \brief (PAC_STATUSC) SERCOM0 APB Protect Enable */
#define PAC_STATUSC_SERCOM0 (_U_(0x1) << PAC_STATUSC_SERCOM0_Pos)
#define PAC_STATUSC_SERCOM1_Pos 2 /**< \brief (PAC_STATUSC) SERCOM1 APB Protect Enable */
#define PAC_STATUSC_SERCOM1 (_U_(0x1) << PAC_STATUSC_SERCOM1_Pos)
#define PAC_STATUSC_SERCOM2_Pos 3 /**< \brief (PAC_STATUSC) SERCOM2 APB Protect Enable */
#define PAC_STATUSC_SERCOM2 (_U_(0x1) << PAC_STATUSC_SERCOM2_Pos)
#define PAC_STATUSC_SERCOM3_Pos 4 /**< \brief (PAC_STATUSC) SERCOM3 APB Protect Enable */
#define PAC_STATUSC_SERCOM3 (_U_(0x1) << PAC_STATUSC_SERCOM3_Pos)
#define PAC_STATUSC_SERCOM4_Pos 5 /**< \brief (PAC_STATUSC) SERCOM4 APB Protect Enable */
#define PAC_STATUSC_SERCOM4 (_U_(0x1) << PAC_STATUSC_SERCOM4_Pos)
#define PAC_STATUSC_SERCOM5_Pos 6 /**< \brief (PAC_STATUSC) SERCOM5 APB Protect Enable */
#define PAC_STATUSC_SERCOM5 (_U_(0x1) << PAC_STATUSC_SERCOM5_Pos)
#define PAC_STATUSC_CAN0_Pos 7 /**< \brief (PAC_STATUSC) CAN0 APB Protect Enable */
#define PAC_STATUSC_CAN0 (_U_(0x1) << PAC_STATUSC_CAN0_Pos)
#define PAC_STATUSC_CAN1_Pos 8 /**< \brief (PAC_STATUSC) CAN1 APB Protect Enable */
#define PAC_STATUSC_CAN1 (_U_(0x1) << PAC_STATUSC_CAN1_Pos)
#define PAC_STATUSC_TCC0_Pos 9 /**< \brief (PAC_STATUSC) TCC0 APB Protect Enable */
#define PAC_STATUSC_TCC0 (_U_(0x1) << PAC_STATUSC_TCC0_Pos)
#define PAC_STATUSC_TCC1_Pos 10 /**< \brief (PAC_STATUSC) TCC1 APB Protect Enable */
#define PAC_STATUSC_TCC1 (_U_(0x1) << PAC_STATUSC_TCC1_Pos)
#define PAC_STATUSC_TCC2_Pos 11 /**< \brief (PAC_STATUSC) TCC2 APB Protect Enable */
#define PAC_STATUSC_TCC2 (_U_(0x1) << PAC_STATUSC_TCC2_Pos)
#define PAC_STATUSC_TC0_Pos 12 /**< \brief (PAC_STATUSC) TC0 APB Protect Enable */
#define PAC_STATUSC_TC0 (_U_(0x1) << PAC_STATUSC_TC0_Pos)
#define PAC_STATUSC_TC1_Pos 13 /**< \brief (PAC_STATUSC) TC1 APB Protect Enable */
#define PAC_STATUSC_TC1 (_U_(0x1) << PAC_STATUSC_TC1_Pos)
#define PAC_STATUSC_TC2_Pos 14 /**< \brief (PAC_STATUSC) TC2 APB Protect Enable */
#define PAC_STATUSC_TC2 (_U_(0x1) << PAC_STATUSC_TC2_Pos)
#define PAC_STATUSC_TC3_Pos 15 /**< \brief (PAC_STATUSC) TC3 APB Protect Enable */
#define PAC_STATUSC_TC3 (_U_(0x1) << PAC_STATUSC_TC3_Pos)
#define PAC_STATUSC_TC4_Pos 16 /**< \brief (PAC_STATUSC) TC4 APB Protect Enable */
#define PAC_STATUSC_TC4 (_U_(0x1) << PAC_STATUSC_TC4_Pos)
#define PAC_STATUSC_ADC0_Pos 17 /**< \brief (PAC_STATUSC) ADC0 APB Protect Enable */
#define PAC_STATUSC_ADC0 (_U_(0x1) << PAC_STATUSC_ADC0_Pos)
#define PAC_STATUSC_ADC1_Pos 18 /**< \brief (PAC_STATUSC) ADC1 APB Protect Enable */
#define PAC_STATUSC_ADC1 (_U_(0x1) << PAC_STATUSC_ADC1_Pos)
#define PAC_STATUSC_SDADC_Pos 19 /**< \brief (PAC_STATUSC) SDADC APB Protect Enable */
#define PAC_STATUSC_SDADC (_U_(0x1) << PAC_STATUSC_SDADC_Pos)
#define PAC_STATUSC_AC_Pos 20 /**< \brief (PAC_STATUSC) AC APB Protect Enable */
#define PAC_STATUSC_AC (_U_(0x1) << PAC_STATUSC_AC_Pos)
#define PAC_STATUSC_DAC_Pos 21 /**< \brief (PAC_STATUSC) DAC APB Protect Enable */
#define PAC_STATUSC_DAC (_U_(0x1) << PAC_STATUSC_DAC_Pos)
#define PAC_STATUSC_PTC_Pos 22 /**< \brief (PAC_STATUSC) PTC APB Protect Enable */
#define PAC_STATUSC_PTC (_U_(0x1) << PAC_STATUSC_PTC_Pos)
#define PAC_STATUSC_CCL_Pos 23 /**< \brief (PAC_STATUSC) CCL APB Protect Enable */
#define PAC_STATUSC_CCL (_U_(0x1) << PAC_STATUSC_CCL_Pos)
#define PAC_STATUSC_MASK _U_(0x00FFFFFF) /**< \brief (PAC_STATUSC) MASK Register */
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PAC_WRCTRL_Type WRCTRL; /**< \brief Offset: 0x00 (R/W 32) Write control */
__IO PAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event control */
RoReg8 Reserved1[0x3];
__IO PAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt enable clear */
__IO PAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt enable set */
RoReg8 Reserved2[0x6];
__IO PAC_INTFLAGAHB_Type INTFLAGAHB; /**< \brief Offset: 0x10 (R/W 32) Bridge interrupt flag status */
__IO PAC_INTFLAGA_Type INTFLAGA; /**< \brief Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A */
__IO PAC_INTFLAGB_Type INTFLAGB; /**< \brief Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B */
__IO PAC_INTFLAGC_Type INTFLAGC; /**< \brief Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C */
RoReg8 Reserved3[0x14];
__I PAC_STATUSA_Type STATUSA; /**< \brief Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A */
__I PAC_STATUSB_Type STATUSB; /**< \brief Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B */
__I PAC_STATUSC_Type STATUSC; /**< \brief Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_PAC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for PM
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PM_COMPONENT_
#define _SAMC21_PM_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PM */
/* ========================================================================== */
/** \addtogroup SAMC21_PM Power Manager */
/*@{*/
#define PM_U2240
#define REV_PM 0x210
/* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_SLEEPCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_SLEEPCFG_OFFSET 0x01 /**< \brief (PM_SLEEPCFG offset) Sleep Configuration */
#define PM_SLEEPCFG_RESETVALUE _U_(0x00) /**< \brief (PM_SLEEPCFG reset_value) Sleep Configuration */
#define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< \brief (PM_SLEEPCFG) Sleep Mode */
#define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos))
#define PM_SLEEPCFG_SLEEPMODE_IDLE0_Val _U_(0x0) /**< \brief (PM_SLEEPCFG) CPU clock is OFF */
#define PM_SLEEPCFG_SLEEPMODE_IDLE1_Val _U_(0x1) /**< \brief (PM_SLEEPCFG) AHB clock is OFF */
#define PM_SLEEPCFG_SLEEPMODE_IDLE2_Val _U_(0x2) /**< \brief (PM_SLEEPCFG) APB clock are OFF */
#define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< \brief (PM_SLEEPCFG) All Clocks are OFF */
#define PM_SLEEPCFG_SLEEPMODE_IDLE0 (PM_SLEEPCFG_SLEEPMODE_IDLE0_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE_IDLE1 (PM_SLEEPCFG_SLEEPMODE_IDLE1_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE_IDLE2 (PM_SLEEPCFG_SLEEPMODE_IDLE2_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos)
#define PM_SLEEPCFG_MASK _U_(0x07) /**< \brief (PM_SLEEPCFG) MASK Register */
/* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 16) Standby Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :6; /*!< bit: 0.. 5 Reserved */
uint16_t VREGSMOD:2; /*!< bit: 6.. 7 Voltage Regulator Standby mode */
uint16_t :2; /*!< bit: 8.. 9 Reserved */
uint16_t BBIASHS:1; /*!< bit: 10 Back Bias for HMCRAMCHS */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} PM_STDBYCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PM_STDBYCFG_OFFSET 0x08 /**< \brief (PM_STDBYCFG offset) Standby Configuration */
#define PM_STDBYCFG_RESETVALUE _U_(0x0400) /**< \brief (PM_STDBYCFG reset_value) Standby Configuration */
#define PM_STDBYCFG_VREGSMOD_Pos 6 /**< \brief (PM_STDBYCFG) Voltage Regulator Standby mode */
#define PM_STDBYCFG_VREGSMOD_Msk (_U_(0x3) << PM_STDBYCFG_VREGSMOD_Pos)
#define PM_STDBYCFG_VREGSMOD(value) (PM_STDBYCFG_VREGSMOD_Msk & ((value) << PM_STDBYCFG_VREGSMOD_Pos))
#define PM_STDBYCFG_VREGSMOD_AUTO_Val _U_(0x0) /**< \brief (PM_STDBYCFG) Automatic mode */
#define PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val _U_(0x1) /**< \brief (PM_STDBYCFG) Performance oriented */
#define PM_STDBYCFG_VREGSMOD_LP_Val _U_(0x2) /**< \brief (PM_STDBYCFG) Low Power oriented */
#define PM_STDBYCFG_VREGSMOD_AUTO (PM_STDBYCFG_VREGSMOD_AUTO_Val << PM_STDBYCFG_VREGSMOD_Pos)
#define PM_STDBYCFG_VREGSMOD_PERFORMANCE (PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val << PM_STDBYCFG_VREGSMOD_Pos)
#define PM_STDBYCFG_VREGSMOD_LP (PM_STDBYCFG_VREGSMOD_LP_Val << PM_STDBYCFG_VREGSMOD_Pos)
#define PM_STDBYCFG_BBIASHS_Pos 10 /**< \brief (PM_STDBYCFG) Back Bias for HMCRAMCHS */
#define PM_STDBYCFG_BBIASHS_Msk (_U_(0x1) << PM_STDBYCFG_BBIASHS_Pos)
#define PM_STDBYCFG_BBIASHS(value) (PM_STDBYCFG_BBIASHS_Msk & ((value) << PM_STDBYCFG_BBIASHS_Pos))
#define PM_STDBYCFG_MASK _U_(0x04C0) /**< \brief (PM_STDBYCFG) MASK Register */
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
RoReg8 Reserved1[0x1];
__IO PM_SLEEPCFG_Type SLEEPCFG; /**< \brief Offset: 0x01 (R/W 8) Sleep Configuration */
RoReg8 Reserved2[0x6];
__IO PM_STDBYCFG_Type STDBYCFG; /**< \brief Offset: 0x08 (R/W 16) Standby Configuration */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_PM_COMPONENT_ */

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/**
* \file
*
* \brief Component description for PORT
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PORT_COMPONENT_
#define _SAMC21_PORT_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR PORT */
/* ========================================================================== */
/** \addtogroup SAMC21_PORT Port Module */
/*@{*/
#define PORT_U2210
#define REV_PORT 0x211
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
#define PORT_DIR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
#define PORT_DIR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
#define PORT_DIRCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
#define PORT_DIRCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
#define PORT_DIRSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
#define PORT_DIRSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
#define PORT_DIRTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
#define PORT_DIRTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
#define PORT_OUT_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
#define PORT_OUT_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
#define PORT_OUTCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
#define PORT_OUTCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
#define PORT_OUTSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
#define PORT_OUTSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
#define PORT_OUTTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
#define PORT_OUTTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
#define PORT_IN_RESETVALUE _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
#define PORT_IN_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
#define PORT_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
#define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
#define PORT_CTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
uint32_t PMUXEN:1; /*!< bit: 16 Select Peripheral Multiplexer */
uint32_t INEN:1; /*!< bit: 17 Input Enable */
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
uint32_t :3; /*!< bit: 19..21 Reserved */
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing Template */
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX Registers */
uint32_t :1; /*!< bit: 29 Reserved */
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG Registers */
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
#define PORT_WRCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
#define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Select Peripheral Multiplexer */
#define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
#define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
#define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
#define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing Template */
#define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX Registers */
#define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG Registers */
#define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
#define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
#define PORT_WRCONFIG_MASK _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
/* -------- PORT_EVCTRL : (PORT Offset: 0x2C) (R/W 32) GROUP Event Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PID0:5; /*!< bit: 0.. 4 Port Event Pin Identifier 0 */
uint32_t EVACT0:2; /*!< bit: 5.. 6 Port Event Action 0 */
uint32_t PORTEI0:1; /*!< bit: 7 Port Event Enable Input 0 */
uint32_t PID1:5; /*!< bit: 8..12 Port Event Pin Identifier 1 */
uint32_t EVACT1:2; /*!< bit: 13..14 Port Event Action 1 */
uint32_t PORTEI1:1; /*!< bit: 15 Port Event Enable Input 1 */
uint32_t PID2:5; /*!< bit: 16..20 Port Event Pin Identifier 2 */
uint32_t EVACT2:2; /*!< bit: 21..22 Port Event Action 2 */
uint32_t PORTEI2:1; /*!< bit: 23 Port Event Enable Input 2 */
uint32_t PID3:5; /*!< bit: 24..28 Port Event Pin Identifier 3 */
uint32_t EVACT3:2; /*!< bit: 29..30 Port Event Action 3 */
uint32_t PORTEI3:1; /*!< bit: 31 Port Event Enable Input 3 */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_EVCTRL_OFFSET 0x2C /**< \brief (PORT_EVCTRL offset) Event Input Control */
#define PORT_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_EVCTRL reset_value) Event Input Control */
#define PORT_EVCTRL_PID0_Pos 0 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 0 */
#define PORT_EVCTRL_PID0_Msk (_U_(0x1F) << PORT_EVCTRL_PID0_Pos)
#define PORT_EVCTRL_PID0(value) (PORT_EVCTRL_PID0_Msk & ((value) << PORT_EVCTRL_PID0_Pos))
#define PORT_EVCTRL_EVACT0_Pos 5 /**< \brief (PORT_EVCTRL) Port Event Action 0 */
#define PORT_EVCTRL_EVACT0_Msk (_U_(0x3) << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_EVACT0(value) (PORT_EVCTRL_EVACT0_Msk & ((value) << PORT_EVCTRL_EVACT0_Pos))
#define PORT_EVCTRL_EVACT0_OUT_Val _U_(0x0) /**< \brief (PORT_EVCTRL) Event output to pin */
#define PORT_EVCTRL_EVACT0_SET_Val _U_(0x1) /**< \brief (PORT_EVCTRL) Set output register of pin on event */
#define PORT_EVCTRL_EVACT0_CLR_Val _U_(0x2) /**< \brief (PORT_EVCTRL) Clear output register of pin on event */
#define PORT_EVCTRL_EVACT0_TGL_Val _U_(0x3) /**< \brief (PORT_EVCTRL) Toggle output register of pin on event */
#define PORT_EVCTRL_EVACT0_OUT (PORT_EVCTRL_EVACT0_OUT_Val << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_EVACT0_SET (PORT_EVCTRL_EVACT0_SET_Val << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_EVACT0_CLR (PORT_EVCTRL_EVACT0_CLR_Val << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_EVACT0_TGL (PORT_EVCTRL_EVACT0_TGL_Val << PORT_EVCTRL_EVACT0_Pos)
#define PORT_EVCTRL_PORTEI0_Pos 7 /**< \brief (PORT_EVCTRL) Port Event Enable Input 0 */
#define PORT_EVCTRL_PORTEI0 (_U_(0x1) << PORT_EVCTRL_PORTEI0_Pos)
#define PORT_EVCTRL_PID1_Pos 8 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 1 */
#define PORT_EVCTRL_PID1_Msk (_U_(0x1F) << PORT_EVCTRL_PID1_Pos)
#define PORT_EVCTRL_PID1(value) (PORT_EVCTRL_PID1_Msk & ((value) << PORT_EVCTRL_PID1_Pos))
#define PORT_EVCTRL_EVACT1_Pos 13 /**< \brief (PORT_EVCTRL) Port Event Action 1 */
#define PORT_EVCTRL_EVACT1_Msk (_U_(0x3) << PORT_EVCTRL_EVACT1_Pos)
#define PORT_EVCTRL_EVACT1(value) (PORT_EVCTRL_EVACT1_Msk & ((value) << PORT_EVCTRL_EVACT1_Pos))
#define PORT_EVCTRL_PORTEI1_Pos 15 /**< \brief (PORT_EVCTRL) Port Event Enable Input 1 */
#define PORT_EVCTRL_PORTEI1 (_U_(0x1) << PORT_EVCTRL_PORTEI1_Pos)
#define PORT_EVCTRL_PID2_Pos 16 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 2 */
#define PORT_EVCTRL_PID2_Msk (_U_(0x1F) << PORT_EVCTRL_PID2_Pos)
#define PORT_EVCTRL_PID2(value) (PORT_EVCTRL_PID2_Msk & ((value) << PORT_EVCTRL_PID2_Pos))
#define PORT_EVCTRL_EVACT2_Pos 21 /**< \brief (PORT_EVCTRL) Port Event Action 2 */
#define PORT_EVCTRL_EVACT2_Msk (_U_(0x3) << PORT_EVCTRL_EVACT2_Pos)
#define PORT_EVCTRL_EVACT2(value) (PORT_EVCTRL_EVACT2_Msk & ((value) << PORT_EVCTRL_EVACT2_Pos))
#define PORT_EVCTRL_PORTEI2_Pos 23 /**< \brief (PORT_EVCTRL) Port Event Enable Input 2 */
#define PORT_EVCTRL_PORTEI2 (_U_(0x1) << PORT_EVCTRL_PORTEI2_Pos)
#define PORT_EVCTRL_PID3_Pos 24 /**< \brief (PORT_EVCTRL) Port Event Pin Identifier 3 */
#define PORT_EVCTRL_PID3_Msk (_U_(0x1F) << PORT_EVCTRL_PID3_Pos)
#define PORT_EVCTRL_PID3(value) (PORT_EVCTRL_PID3_Msk & ((value) << PORT_EVCTRL_PID3_Pos))
#define PORT_EVCTRL_EVACT3_Pos 29 /**< \brief (PORT_EVCTRL) Port Event Action 3 */
#define PORT_EVCTRL_EVACT3_Msk (_U_(0x3) << PORT_EVCTRL_EVACT3_Pos)
#define PORT_EVCTRL_EVACT3(value) (PORT_EVCTRL_EVACT3_Msk & ((value) << PORT_EVCTRL_EVACT3_Pos))
#define PORT_EVCTRL_PORTEI3_Pos 31 /**< \brief (PORT_EVCTRL) Port Event Enable Input 3 */
#define PORT_EVCTRL_PORTEI3 (_U_(0x1) << PORT_EVCTRL_PORTEI3_Pos)
#define PORT_EVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_EVCTRL) MASK Register */
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing for Even-Numbered Pin */
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing for Odd-Numbered Pin */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
#define PORT_PMUX_RESETVALUE _U_(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Even-Numbered Pin */
#define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing for Odd-Numbered Pin */
#define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
#define PORT_PMUX_MASK _U_(0xFF) /**< \brief (PORT_PMUX) MASK Register */
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXEN:1; /*!< bit: 0 Select Peripheral Multiplexer */
uint8_t INEN:1; /*!< bit: 1 Input Enable */
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
#define PORT_PINCFG_RESETVALUE _U_(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Select Peripheral Multiplexer */
#define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
#define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos)
#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
#define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
#define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
#define PORT_PINCFG_MASK _U_(0x47) /**< \brief (PORT_PINCFG) MASK Register */
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
__IO PORT_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2C (R/W 32) Event Input Control */
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
RoReg8 Reserved1[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_PORT_COMPONENT_ */

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/**
* \file
*
* \brief Component description for RSTC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_RSTC_COMPONENT_
#define _SAMC21_RSTC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR RSTC */
/* ========================================================================== */
/** \addtogroup SAMC21_RSTC Reset Controller */
/*@{*/
#define RSTC_U2239
#define REV_RSTC 0x202
/* -------- RSTC_RCAUSE : (RSTC Offset: 0x00) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t POR:1; /*!< bit: 0 Power On Reset */
uint8_t BODCORE:1; /*!< bit: 1 Brown Out CORE Detector Reset */
uint8_t BODVDD:1; /*!< bit: 2 Brown Out VDD Detector Reset */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t EXT:1; /*!< bit: 4 External Reset */
uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
uint8_t SYST:1; /*!< bit: 6 System Reset Request */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RSTC_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define RSTC_RCAUSE_OFFSET 0x00 /**< \brief (RSTC_RCAUSE offset) Reset Cause */
#define RSTC_RCAUSE_POR_Pos 0 /**< \brief (RSTC_RCAUSE) Power On Reset */
#define RSTC_RCAUSE_POR (_U_(0x1) << RSTC_RCAUSE_POR_Pos)
#define RSTC_RCAUSE_BODCORE_Pos 1 /**< \brief (RSTC_RCAUSE) Brown Out CORE Detector Reset */
#define RSTC_RCAUSE_BODCORE (_U_(0x1) << RSTC_RCAUSE_BODCORE_Pos)
#define RSTC_RCAUSE_BODVDD_Pos 2 /**< \brief (RSTC_RCAUSE) Brown Out VDD Detector Reset */
#define RSTC_RCAUSE_BODVDD (_U_(0x1) << RSTC_RCAUSE_BODVDD_Pos)
#define RSTC_RCAUSE_EXT_Pos 4 /**< \brief (RSTC_RCAUSE) External Reset */
#define RSTC_RCAUSE_EXT (_U_(0x1) << RSTC_RCAUSE_EXT_Pos)
#define RSTC_RCAUSE_WDT_Pos 5 /**< \brief (RSTC_RCAUSE) Watchdog Reset */
#define RSTC_RCAUSE_WDT (_U_(0x1) << RSTC_RCAUSE_WDT_Pos)
#define RSTC_RCAUSE_SYST_Pos 6 /**< \brief (RSTC_RCAUSE) System Reset Request */
#define RSTC_RCAUSE_SYST (_U_(0x1) << RSTC_RCAUSE_SYST_Pos)
#define RSTC_RCAUSE_MASK _U_(0x77) /**< \brief (RSTC_RCAUSE) MASK Register */
/** \brief RSTC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__I RSTC_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x00 (R/ 8) Reset Cause */
} Rstc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_RSTC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for SDADC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SDADC_COMPONENT_
#define _SAMC21_SDADC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR SDADC */
/* ========================================================================== */
/** \addtogroup SAMC21_SDADC Sigma-Delta Analog Digital Converter */
/*@{*/
#define SDADC_U2260
#define REV_SDADC 0x101
/* -------- SDADC_CTRLA : (SDADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_CTRLA_OFFSET 0x00 /**< \brief (SDADC_CTRLA offset) Control A */
#define SDADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (SDADC_CTRLA reset_value) Control A */
#define SDADC_CTRLA_SWRST_Pos 0 /**< \brief (SDADC_CTRLA) Software Reset */
#define SDADC_CTRLA_SWRST (_U_(0x1) << SDADC_CTRLA_SWRST_Pos)
#define SDADC_CTRLA_ENABLE_Pos 1 /**< \brief (SDADC_CTRLA) Enable */
#define SDADC_CTRLA_ENABLE (_U_(0x1) << SDADC_CTRLA_ENABLE_Pos)
#define SDADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (SDADC_CTRLA) Run during Standby */
#define SDADC_CTRLA_RUNSTDBY (_U_(0x1) << SDADC_CTRLA_RUNSTDBY_Pos)
#define SDADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (SDADC_CTRLA) On Demand Control */
#define SDADC_CTRLA_ONDEMAND (_U_(0x1) << SDADC_CTRLA_ONDEMAND_Pos)
#define SDADC_CTRLA_MASK _U_(0xC3) /**< \brief (SDADC_CTRLA) MASK Register */
/* -------- SDADC_REFCTRL : (SDADC Offset: 0x01) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t REFSEL:2; /*!< bit: 0.. 1 Reference Selection */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t REFRANGE:2; /*!< bit: 4.. 5 Reference Range */
uint8_t :1; /*!< bit: 6 Reserved */
uint8_t ONREFBUF:1; /*!< bit: 7 Reference Buffer */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_REFCTRL_OFFSET 0x01 /**< \brief (SDADC_REFCTRL offset) Reference Control */
#define SDADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_REFCTRL reset_value) Reference Control */
#define SDADC_REFCTRL_REFSEL_Pos 0 /**< \brief (SDADC_REFCTRL) Reference Selection */
#define SDADC_REFCTRL_REFSEL_Msk (_U_(0x3) << SDADC_REFCTRL_REFSEL_Pos)
#define SDADC_REFCTRL_REFSEL(value) (SDADC_REFCTRL_REFSEL_Msk & ((value) << SDADC_REFCTRL_REFSEL_Pos))
#define SDADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (SDADC_REFCTRL) Internal Bandgap Reference */
#define SDADC_REFCTRL_REFSEL_AREFB_Val _U_(0x1) /**< \brief (SDADC_REFCTRL) External Reference */
#define SDADC_REFCTRL_REFSEL_DAC_Val _U_(0x2) /**< \brief (SDADC_REFCTRL) Internal DAC Output */
#define SDADC_REFCTRL_REFSEL_INTVCC_Val _U_(0x3) /**< \brief (SDADC_REFCTRL) VDDANA */
#define SDADC_REFCTRL_REFSEL_INTREF (SDADC_REFCTRL_REFSEL_INTREF_Val << SDADC_REFCTRL_REFSEL_Pos)
#define SDADC_REFCTRL_REFSEL_AREFB (SDADC_REFCTRL_REFSEL_AREFB_Val << SDADC_REFCTRL_REFSEL_Pos)
#define SDADC_REFCTRL_REFSEL_DAC (SDADC_REFCTRL_REFSEL_DAC_Val << SDADC_REFCTRL_REFSEL_Pos)
#define SDADC_REFCTRL_REFSEL_INTVCC (SDADC_REFCTRL_REFSEL_INTVCC_Val << SDADC_REFCTRL_REFSEL_Pos)
#define SDADC_REFCTRL_REFRANGE_Pos 4 /**< \brief (SDADC_REFCTRL) Reference Range */
#define SDADC_REFCTRL_REFRANGE_Msk (_U_(0x3) << SDADC_REFCTRL_REFRANGE_Pos)
#define SDADC_REFCTRL_REFRANGE(value) (SDADC_REFCTRL_REFRANGE_Msk & ((value) << SDADC_REFCTRL_REFRANGE_Pos))
#define SDADC_REFCTRL_ONREFBUF_Pos 7 /**< \brief (SDADC_REFCTRL) Reference Buffer */
#define SDADC_REFCTRL_ONREFBUF (_U_(0x1) << SDADC_REFCTRL_ONREFBUF_Pos)
#define SDADC_REFCTRL_MASK _U_(0xB3) /**< \brief (SDADC_REFCTRL) MASK Register */
/* -------- SDADC_CTRLB : (SDADC Offset: 0x02) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PRESCALER:8; /*!< bit: 0.. 7 Prescaler Configuration */
uint16_t OSR:3; /*!< bit: 8..10 Over Sampling Ratio */
uint16_t :1; /*!< bit: 11 Reserved */
uint16_t SKPCNT:4; /*!< bit: 12..15 Skip Sample Count */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SDADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_CTRLB_OFFSET 0x02 /**< \brief (SDADC_CTRLB offset) Control B */
#define SDADC_CTRLB_RESETVALUE _U_(0x2000) /**< \brief (SDADC_CTRLB reset_value) Control B */
#define SDADC_CTRLB_PRESCALER_Pos 0 /**< \brief (SDADC_CTRLB) Prescaler Configuration */
#define SDADC_CTRLB_PRESCALER_Msk (_U_(0xFF) << SDADC_CTRLB_PRESCALER_Pos)
#define SDADC_CTRLB_PRESCALER(value) (SDADC_CTRLB_PRESCALER_Msk & ((value) << SDADC_CTRLB_PRESCALER_Pos))
#define SDADC_CTRLB_OSR_Pos 8 /**< \brief (SDADC_CTRLB) Over Sampling Ratio */
#define SDADC_CTRLB_OSR_Msk (_U_(0x7) << SDADC_CTRLB_OSR_Pos)
#define SDADC_CTRLB_OSR(value) (SDADC_CTRLB_OSR_Msk & ((value) << SDADC_CTRLB_OSR_Pos))
#define SDADC_CTRLB_SKPCNT_Pos 12 /**< \brief (SDADC_CTRLB) Skip Sample Count */
#define SDADC_CTRLB_SKPCNT_Msk (_U_(0xF) << SDADC_CTRLB_SKPCNT_Pos)
#define SDADC_CTRLB_SKPCNT(value) (SDADC_CTRLB_SKPCNT_Msk & ((value) << SDADC_CTRLB_SKPCNT_Pos))
#define SDADC_CTRLB_MASK _U_(0xF7FF) /**< \brief (SDADC_CTRLB) MASK Register */
/* -------- SDADC_EVCTRL : (SDADC Offset: 0x04) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */
uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */
uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */
uint8_t STARTINV:1; /*!< bit: 3 Satrt Event Invert Enable */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_EVCTRL_OFFSET 0x04 /**< \brief (SDADC_EVCTRL offset) Event Control */
#define SDADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_EVCTRL reset_value) Event Control */
#define SDADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (SDADC_EVCTRL) Flush Event Input Enable */
#define SDADC_EVCTRL_FLUSHEI (_U_(0x1) << SDADC_EVCTRL_FLUSHEI_Pos)
#define SDADC_EVCTRL_STARTEI_Pos 1 /**< \brief (SDADC_EVCTRL) Start Conversion Event Input Enable */
#define SDADC_EVCTRL_STARTEI (_U_(0x1) << SDADC_EVCTRL_STARTEI_Pos)
#define SDADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (SDADC_EVCTRL) Flush Event Invert Enable */
#define SDADC_EVCTRL_FLUSHINV (_U_(0x1) << SDADC_EVCTRL_FLUSHINV_Pos)
#define SDADC_EVCTRL_STARTINV_Pos 3 /**< \brief (SDADC_EVCTRL) Satrt Event Invert Enable */
#define SDADC_EVCTRL_STARTINV (_U_(0x1) << SDADC_EVCTRL_STARTINV_Pos)
#define SDADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (SDADC_EVCTRL) Result Ready Event Out */
#define SDADC_EVCTRL_RESRDYEO (_U_(0x1) << SDADC_EVCTRL_RESRDYEO_Pos)
#define SDADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (SDADC_EVCTRL) Window Monitor Event Out */
#define SDADC_EVCTRL_WINMONEO (_U_(0x1) << SDADC_EVCTRL_WINMONEO_Pos)
#define SDADC_EVCTRL_MASK _U_(0x3F) /**< \brief (SDADC_EVCTRL) MASK Register */
/* -------- SDADC_INTENCLR : (SDADC Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_INTENCLR_OFFSET 0x05 /**< \brief (SDADC_INTENCLR offset) Interrupt Enable Clear */
#define SDADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SDADC_INTENCLR reset_value) Interrupt Enable Clear */
#define SDADC_INTENCLR_RESRDY_Pos 0 /**< \brief (SDADC_INTENCLR) Result Ready Interrupt Disable */
#define SDADC_INTENCLR_RESRDY (_U_(0x1) << SDADC_INTENCLR_RESRDY_Pos)
#define SDADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (SDADC_INTENCLR) Overrun Interrupt Disable */
#define SDADC_INTENCLR_OVERRUN (_U_(0x1) << SDADC_INTENCLR_OVERRUN_Pos)
#define SDADC_INTENCLR_WINMON_Pos 2 /**< \brief (SDADC_INTENCLR) Window Monitor Interrupt Disable */
#define SDADC_INTENCLR_WINMON (_U_(0x1) << SDADC_INTENCLR_WINMON_Pos)
#define SDADC_INTENCLR_MASK _U_(0x07) /**< \brief (SDADC_INTENCLR) MASK Register */
/* -------- SDADC_INTENSET : (SDADC Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_INTENSET_OFFSET 0x06 /**< \brief (SDADC_INTENSET offset) Interrupt Enable Set */
#define SDADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SDADC_INTENSET reset_value) Interrupt Enable Set */
#define SDADC_INTENSET_RESRDY_Pos 0 /**< \brief (SDADC_INTENSET) Result Ready Interrupt Enable */
#define SDADC_INTENSET_RESRDY (_U_(0x1) << SDADC_INTENSET_RESRDY_Pos)
#define SDADC_INTENSET_OVERRUN_Pos 1 /**< \brief (SDADC_INTENSET) Overrun Interrupt Enable */
#define SDADC_INTENSET_OVERRUN (_U_(0x1) << SDADC_INTENSET_OVERRUN_Pos)
#define SDADC_INTENSET_WINMON_Pos 2 /**< \brief (SDADC_INTENSET) Window Monitor Interrupt Enable */
#define SDADC_INTENSET_WINMON (_U_(0x1) << SDADC_INTENSET_WINMON_Pos)
#define SDADC_INTENSET_MASK _U_(0x07) /**< \brief (SDADC_INTENSET) MASK Register */
/* -------- SDADC_INTFLAG : (SDADC Offset: 0x07) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_INTFLAG_OFFSET 0x07 /**< \brief (SDADC_INTFLAG offset) Interrupt Flag Status and Clear */
#define SDADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SDADC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define SDADC_INTFLAG_RESRDY_Pos 0 /**< \brief (SDADC_INTFLAG) Result Ready Interrupt Flag */
#define SDADC_INTFLAG_RESRDY (_U_(0x1) << SDADC_INTFLAG_RESRDY_Pos)
#define SDADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (SDADC_INTFLAG) Overrun Interrupt Flag */
#define SDADC_INTFLAG_OVERRUN (_U_(0x1) << SDADC_INTFLAG_OVERRUN_Pos)
#define SDADC_INTFLAG_WINMON_Pos 2 /**< \brief (SDADC_INTFLAG) Window Monitor Interrupt Flag */
#define SDADC_INTFLAG_WINMON (_U_(0x1) << SDADC_INTFLAG_WINMON_Pos)
#define SDADC_INTFLAG_MASK _U_(0x07) /**< \brief (SDADC_INTFLAG) MASK Register */
/* -------- SDADC_SEQSTATUS : (SDADC Offset: 0x08) (R/ 8) Sequence Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SEQSTATE:4; /*!< bit: 0.. 3 Sequence State */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t SEQBUSY:1; /*!< bit: 7 Sequence Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_SEQSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_SEQSTATUS_OFFSET 0x08 /**< \brief (SDADC_SEQSTATUS offset) Sequence Status */
#define SDADC_SEQSTATUS_RESETVALUE _U_(0x00) /**< \brief (SDADC_SEQSTATUS reset_value) Sequence Status */
#define SDADC_SEQSTATUS_SEQSTATE_Pos 0 /**< \brief (SDADC_SEQSTATUS) Sequence State */
#define SDADC_SEQSTATUS_SEQSTATE_Msk (_U_(0xF) << SDADC_SEQSTATUS_SEQSTATE_Pos)
#define SDADC_SEQSTATUS_SEQSTATE(value) (SDADC_SEQSTATUS_SEQSTATE_Msk & ((value) << SDADC_SEQSTATUS_SEQSTATE_Pos))
#define SDADC_SEQSTATUS_SEQBUSY_Pos 7 /**< \brief (SDADC_SEQSTATUS) Sequence Busy */
#define SDADC_SEQSTATUS_SEQBUSY (_U_(0x1) << SDADC_SEQSTATUS_SEQBUSY_Pos)
#define SDADC_SEQSTATUS_MASK _U_(0x8F) /**< \brief (SDADC_SEQSTATUS) MASK Register */
/* -------- SDADC_INPUTCTRL : (SDADC Offset: 0x09) (R/W 8) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t MUXSEL:4; /*!< bit: 0.. 3 SDADC Input Selection */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_INPUTCTRL_OFFSET 0x09 /**< \brief (SDADC_INPUTCTRL offset) Input Control */
#define SDADC_INPUTCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_INPUTCTRL reset_value) Input Control */
#define SDADC_INPUTCTRL_MUXSEL_Pos 0 /**< \brief (SDADC_INPUTCTRL) SDADC Input Selection */
#define SDADC_INPUTCTRL_MUXSEL_Msk (_U_(0xF) << SDADC_INPUTCTRL_MUXSEL_Pos)
#define SDADC_INPUTCTRL_MUXSEL(value) (SDADC_INPUTCTRL_MUXSEL_Msk & ((value) << SDADC_INPUTCTRL_MUXSEL_Pos))
#define SDADC_INPUTCTRL_MUXSEL_AIN0_Val _U_(0x0) /**< \brief (SDADC_INPUTCTRL) SDADC AIN0 Pin */
#define SDADC_INPUTCTRL_MUXSEL_AIN1_Val _U_(0x1) /**< \brief (SDADC_INPUTCTRL) SDADC AIN1 Pin */
#define SDADC_INPUTCTRL_MUXSEL_AIN2_Val _U_(0x2) /**< \brief (SDADC_INPUTCTRL) SDADC AIN2 Pin */
#define SDADC_INPUTCTRL_MUXSEL_AIN0 (SDADC_INPUTCTRL_MUXSEL_AIN0_Val << SDADC_INPUTCTRL_MUXSEL_Pos)
#define SDADC_INPUTCTRL_MUXSEL_AIN1 (SDADC_INPUTCTRL_MUXSEL_AIN1_Val << SDADC_INPUTCTRL_MUXSEL_Pos)
#define SDADC_INPUTCTRL_MUXSEL_AIN2 (SDADC_INPUTCTRL_MUXSEL_AIN2_Val << SDADC_INPUTCTRL_MUXSEL_Pos)
#define SDADC_INPUTCTRL_MASK _U_(0x0F) /**< \brief (SDADC_INPUTCTRL) MASK Register */
/* -------- SDADC_CTRLC : (SDADC Offset: 0x0A) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FREERUN:1; /*!< bit: 0 Free Running Mode */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_CTRLC_OFFSET 0x0A /**< \brief (SDADC_CTRLC offset) Control C */
#define SDADC_CTRLC_RESETVALUE _U_(0x00) /**< \brief (SDADC_CTRLC reset_value) Control C */
#define SDADC_CTRLC_FREERUN_Pos 0 /**< \brief (SDADC_CTRLC) Free Running Mode */
#define SDADC_CTRLC_FREERUN (_U_(0x1) << SDADC_CTRLC_FREERUN_Pos)
#define SDADC_CTRLC_MASK _U_(0x01) /**< \brief (SDADC_CTRLC) MASK Register */
/* -------- SDADC_WINCTRL : (SDADC Offset: 0x0B) (R/W 8) Window Monitor Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_WINCTRL_OFFSET 0x0B /**< \brief (SDADC_WINCTRL offset) Window Monitor Control */
#define SDADC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_WINCTRL reset_value) Window Monitor Control */
#define SDADC_WINCTRL_WINMODE_Pos 0 /**< \brief (SDADC_WINCTRL) Window Monitor Mode */
#define SDADC_WINCTRL_WINMODE_Msk (_U_(0x7) << SDADC_WINCTRL_WINMODE_Pos)
#define SDADC_WINCTRL_WINMODE(value) (SDADC_WINCTRL_WINMODE_Msk & ((value) << SDADC_WINCTRL_WINMODE_Pos))
#define SDADC_WINCTRL_MASK _U_(0x07) /**< \brief (SDADC_WINCTRL) MASK Register */
/* -------- SDADC_WINLT : (SDADC Offset: 0x0C) (R/W 32) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WINLT:24; /*!< bit: 0..23 Window Lower Threshold */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SDADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_WINLT_OFFSET 0x0C /**< \brief (SDADC_WINLT offset) Window Monitor Lower Threshold */
#define SDADC_WINLT_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_WINLT reset_value) Window Monitor Lower Threshold */
#define SDADC_WINLT_WINLT_Pos 0 /**< \brief (SDADC_WINLT) Window Lower Threshold */
#define SDADC_WINLT_WINLT_Msk (_U_(0xFFFFFF) << SDADC_WINLT_WINLT_Pos)
#define SDADC_WINLT_WINLT(value) (SDADC_WINLT_WINLT_Msk & ((value) << SDADC_WINLT_WINLT_Pos))
#define SDADC_WINLT_MASK _U_(0x00FFFFFF) /**< \brief (SDADC_WINLT) MASK Register */
/* -------- SDADC_WINUT : (SDADC Offset: 0x10) (R/W 32) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WINUT:24; /*!< bit: 0..23 Window Upper Threshold */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SDADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_WINUT_OFFSET 0x10 /**< \brief (SDADC_WINUT offset) Window Monitor Upper Threshold */
#define SDADC_WINUT_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_WINUT reset_value) Window Monitor Upper Threshold */
#define SDADC_WINUT_WINUT_Pos 0 /**< \brief (SDADC_WINUT) Window Upper Threshold */
#define SDADC_WINUT_WINUT_Msk (_U_(0xFFFFFF) << SDADC_WINUT_WINUT_Pos)
#define SDADC_WINUT_WINUT(value) (SDADC_WINUT_WINUT_Msk & ((value) << SDADC_WINUT_WINUT_Pos))
#define SDADC_WINUT_MASK _U_(0x00FFFFFF) /**< \brief (SDADC_WINUT) MASK Register */
/* -------- SDADC_OFFSETCORR : (SDADC Offset: 0x14) (R/W 32) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OFFSETCORR:24; /*!< bit: 0..23 Offset Correction Value */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SDADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_OFFSETCORR_OFFSET 0x14 /**< \brief (SDADC_OFFSETCORR offset) Offset Correction */
#define SDADC_OFFSETCORR_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_OFFSETCORR reset_value) Offset Correction */
#define SDADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (SDADC_OFFSETCORR) Offset Correction Value */
#define SDADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFFFFF) << SDADC_OFFSETCORR_OFFSETCORR_Pos)
#define SDADC_OFFSETCORR_OFFSETCORR(value) (SDADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << SDADC_OFFSETCORR_OFFSETCORR_Pos))
#define SDADC_OFFSETCORR_MASK _U_(0x00FFFFFF) /**< \brief (SDADC_OFFSETCORR) MASK Register */
/* -------- SDADC_GAINCORR : (SDADC Offset: 0x18) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t GAINCORR:14; /*!< bit: 0..13 Gain Correction Value */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SDADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_GAINCORR_OFFSET 0x18 /**< \brief (SDADC_GAINCORR offset) Gain Correction */
#define SDADC_GAINCORR_RESETVALUE _U_(0x0001) /**< \brief (SDADC_GAINCORR reset_value) Gain Correction */
#define SDADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (SDADC_GAINCORR) Gain Correction Value */
#define SDADC_GAINCORR_GAINCORR_Msk (_U_(0x3FFF) << SDADC_GAINCORR_GAINCORR_Pos)
#define SDADC_GAINCORR_GAINCORR(value) (SDADC_GAINCORR_GAINCORR_Msk & ((value) << SDADC_GAINCORR_GAINCORR_Pos))
#define SDADC_GAINCORR_MASK _U_(0x3FFF) /**< \brief (SDADC_GAINCORR) MASK Register */
/* -------- SDADC_SHIFTCORR : (SDADC Offset: 0x1A) (R/W 8) Shift Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SHIFTCORR:4; /*!< bit: 0.. 3 Shift Correction Value */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_SHIFTCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_SHIFTCORR_OFFSET 0x1A /**< \brief (SDADC_SHIFTCORR offset) Shift Correction */
#define SDADC_SHIFTCORR_RESETVALUE _U_(0x00) /**< \brief (SDADC_SHIFTCORR reset_value) Shift Correction */
#define SDADC_SHIFTCORR_SHIFTCORR_Pos 0 /**< \brief (SDADC_SHIFTCORR) Shift Correction Value */
#define SDADC_SHIFTCORR_SHIFTCORR_Msk (_U_(0xF) << SDADC_SHIFTCORR_SHIFTCORR_Pos)
#define SDADC_SHIFTCORR_SHIFTCORR(value) (SDADC_SHIFTCORR_SHIFTCORR_Msk & ((value) << SDADC_SHIFTCORR_SHIFTCORR_Pos))
#define SDADC_SHIFTCORR_MASK _U_(0x0F) /**< \brief (SDADC_SHIFTCORR) MASK Register */
/* -------- SDADC_SWTRIG : (SDADC Offset: 0x1C) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSH:1; /*!< bit: 0 SDADC Flush */
uint8_t START:1; /*!< bit: 1 Start SDADC Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_SWTRIG_OFFSET 0x1C /**< \brief (SDADC_SWTRIG offset) Software Trigger */
#define SDADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (SDADC_SWTRIG reset_value) Software Trigger */
#define SDADC_SWTRIG_FLUSH_Pos 0 /**< \brief (SDADC_SWTRIG) SDADC Flush */
#define SDADC_SWTRIG_FLUSH (_U_(0x1) << SDADC_SWTRIG_FLUSH_Pos)
#define SDADC_SWTRIG_START_Pos 1 /**< \brief (SDADC_SWTRIG) Start SDADC Conversion */
#define SDADC_SWTRIG_START (_U_(0x1) << SDADC_SWTRIG_START_Pos)
#define SDADC_SWTRIG_MASK _U_(0x03) /**< \brief (SDADC_SWTRIG) MASK Register */
/* -------- SDADC_SYNCBUSY : (SDADC Offset: 0x20) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */
uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */
uint32_t CTRLC:1; /*!< bit: 2 CTRLC Synchronization Busy */
uint32_t INPUTCTRL:1; /*!< bit: 3 INPUTCTRL Synchronization Busy */
uint32_t WINCTRL:1; /*!< bit: 4 WINCTRL Synchronization Busy */
uint32_t WINLT:1; /*!< bit: 5 WINLT Synchronization Busy */
uint32_t WINUT:1; /*!< bit: 6 WINUT Synchronization Busy */
uint32_t OFFSETCORR:1; /*!< bit: 7 OFFSETCTRL Synchronization Busy */
uint32_t GAINCORR:1; /*!< bit: 8 GAINCORR Synchronization Busy */
uint32_t SHIFTCORR:1; /*!< bit: 9 SHIFTCORR Synchronization Busy */
uint32_t SWTRIG:1; /*!< bit: 10 SWTRG Synchronization Busy */
uint32_t ANACTRL:1; /*!< bit: 11 ANACTRL Synchronization Busy */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SDADC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_SYNCBUSY_OFFSET 0x20 /**< \brief (SDADC_SYNCBUSY offset) Synchronization Busy */
#define SDADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_SYNCBUSY reset_value) Synchronization Busy */
#define SDADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (SDADC_SYNCBUSY) SWRST Synchronization Busy */
#define SDADC_SYNCBUSY_SWRST (_U_(0x1) << SDADC_SYNCBUSY_SWRST_Pos)
#define SDADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SDADC_SYNCBUSY) ENABLE Synchronization Busy */
#define SDADC_SYNCBUSY_ENABLE (_U_(0x1) << SDADC_SYNCBUSY_ENABLE_Pos)
#define SDADC_SYNCBUSY_CTRLC_Pos 2 /**< \brief (SDADC_SYNCBUSY) CTRLC Synchronization Busy */
#define SDADC_SYNCBUSY_CTRLC (_U_(0x1) << SDADC_SYNCBUSY_CTRLC_Pos)
#define SDADC_SYNCBUSY_INPUTCTRL_Pos 3 /**< \brief (SDADC_SYNCBUSY) INPUTCTRL Synchronization Busy */
#define SDADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << SDADC_SYNCBUSY_INPUTCTRL_Pos)
#define SDADC_SYNCBUSY_WINCTRL_Pos 4 /**< \brief (SDADC_SYNCBUSY) WINCTRL Synchronization Busy */
#define SDADC_SYNCBUSY_WINCTRL (_U_(0x1) << SDADC_SYNCBUSY_WINCTRL_Pos)
#define SDADC_SYNCBUSY_WINLT_Pos 5 /**< \brief (SDADC_SYNCBUSY) WINLT Synchronization Busy */
#define SDADC_SYNCBUSY_WINLT (_U_(0x1) << SDADC_SYNCBUSY_WINLT_Pos)
#define SDADC_SYNCBUSY_WINUT_Pos 6 /**< \brief (SDADC_SYNCBUSY) WINUT Synchronization Busy */
#define SDADC_SYNCBUSY_WINUT (_U_(0x1) << SDADC_SYNCBUSY_WINUT_Pos)
#define SDADC_SYNCBUSY_OFFSETCORR_Pos 7 /**< \brief (SDADC_SYNCBUSY) OFFSETCTRL Synchronization Busy */
#define SDADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << SDADC_SYNCBUSY_OFFSETCORR_Pos)
#define SDADC_SYNCBUSY_GAINCORR_Pos 8 /**< \brief (SDADC_SYNCBUSY) GAINCORR Synchronization Busy */
#define SDADC_SYNCBUSY_GAINCORR (_U_(0x1) << SDADC_SYNCBUSY_GAINCORR_Pos)
#define SDADC_SYNCBUSY_SHIFTCORR_Pos 9 /**< \brief (SDADC_SYNCBUSY) SHIFTCORR Synchronization Busy */
#define SDADC_SYNCBUSY_SHIFTCORR (_U_(0x1) << SDADC_SYNCBUSY_SHIFTCORR_Pos)
#define SDADC_SYNCBUSY_SWTRIG_Pos 10 /**< \brief (SDADC_SYNCBUSY) SWTRG Synchronization Busy */
#define SDADC_SYNCBUSY_SWTRIG (_U_(0x1) << SDADC_SYNCBUSY_SWTRIG_Pos)
#define SDADC_SYNCBUSY_ANACTRL_Pos 11 /**< \brief (SDADC_SYNCBUSY) ANACTRL Synchronization Busy */
#define SDADC_SYNCBUSY_ANACTRL (_U_(0x1) << SDADC_SYNCBUSY_ANACTRL_Pos)
#define SDADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (SDADC_SYNCBUSY) MASK Register */
/* -------- SDADC_RESULT : (SDADC Offset: 0x24) (R/ 32) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RESULT:24; /*!< bit: 0..23 Result Value */
uint32_t RESERVED:8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SDADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_RESULT_OFFSET 0x24 /**< \brief (SDADC_RESULT offset) Result */
#define SDADC_RESULT_RESETVALUE _U_(0x00000000) /**< \brief (SDADC_RESULT reset_value) Result */
#define SDADC_RESULT_RESULT_Pos 0 /**< \brief (SDADC_RESULT) Result Value */
#define SDADC_RESULT_RESULT_Msk (_U_(0xFFFFFF) << SDADC_RESULT_RESULT_Pos)
#define SDADC_RESULT_RESULT(value) (SDADC_RESULT_RESULT_Msk & ((value) << SDADC_RESULT_RESULT_Pos))
#define SDADC_RESULT_RESERVED_Pos 24 /**< \brief (SDADC_RESULT) Reserved */
#define SDADC_RESULT_RESERVED_Msk (_U_(0xFF) << SDADC_RESULT_RESERVED_Pos)
#define SDADC_RESULT_RESERVED(value) (SDADC_RESULT_RESERVED_Msk & ((value) << SDADC_RESULT_RESERVED_Pos))
#define SDADC_RESULT_MASK _U_(0xFFFFFFFF) /**< \brief (SDADC_RESULT) MASK Register */
/* -------- SDADC_SEQCTRL : (SDADC Offset: 0x28) (R/W 8) Sequence Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SEQEN:3; /*!< bit: 0.. 2 Enable Positive Input in the Sequence */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_SEQCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_SEQCTRL_OFFSET 0x28 /**< \brief (SDADC_SEQCTRL offset) Sequence Control */
#define SDADC_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_SEQCTRL reset_value) Sequence Control */
#define SDADC_SEQCTRL_SEQEN_Pos 0 /**< \brief (SDADC_SEQCTRL) Enable Positive Input in the Sequence */
#define SDADC_SEQCTRL_SEQEN_Msk (_U_(0x7) << SDADC_SEQCTRL_SEQEN_Pos)
#define SDADC_SEQCTRL_SEQEN(value) (SDADC_SEQCTRL_SEQEN_Msk & ((value) << SDADC_SEQCTRL_SEQEN_Pos))
#define SDADC_SEQCTRL_MASK _U_(0x07) /**< \brief (SDADC_SEQCTRL) MASK Register */
/* -------- SDADC_ANACTRL : (SDADC Offset: 0x2C) (R/W 8) Analog Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CTRSDADC:6; /*!< bit: 0.. 5 SDADC Control */
uint8_t ONCHOP:1; /*!< bit: 6 Chopper */
uint8_t BUFTEST:1; /*!< bit: 7 BUFTEST */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_ANACTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_ANACTRL_OFFSET 0x2C /**< \brief (SDADC_ANACTRL offset) Analog Control */
#define SDADC_ANACTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_ANACTRL reset_value) Analog Control */
#define SDADC_ANACTRL_CTRSDADC_Pos 0 /**< \brief (SDADC_ANACTRL) SDADC Control */
#define SDADC_ANACTRL_CTRSDADC_Msk (_U_(0x3F) << SDADC_ANACTRL_CTRSDADC_Pos)
#define SDADC_ANACTRL_CTRSDADC(value) (SDADC_ANACTRL_CTRSDADC_Msk & ((value) << SDADC_ANACTRL_CTRSDADC_Pos))
#define SDADC_ANACTRL_ONCHOP_Pos 6 /**< \brief (SDADC_ANACTRL) Chopper */
#define SDADC_ANACTRL_ONCHOP (_U_(0x1) << SDADC_ANACTRL_ONCHOP_Pos)
#define SDADC_ANACTRL_BUFTEST_Pos 7 /**< \brief (SDADC_ANACTRL) BUFTEST */
#define SDADC_ANACTRL_BUFTEST (_U_(0x1) << SDADC_ANACTRL_BUFTEST_Pos)
#define SDADC_ANACTRL_MASK _U_(0xFF) /**< \brief (SDADC_ANACTRL) MASK Register */
/* -------- SDADC_DBGCTRL : (SDADC Offset: 0x2E) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SDADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SDADC_DBGCTRL_OFFSET 0x2E /**< \brief (SDADC_DBGCTRL offset) Debug Control */
#define SDADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SDADC_DBGCTRL reset_value) Debug Control */
#define SDADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (SDADC_DBGCTRL) Debug Run */
#define SDADC_DBGCTRL_DBGRUN (_U_(0x1) << SDADC_DBGCTRL_DBGRUN_Pos)
#define SDADC_DBGCTRL_MASK _U_(0x01) /**< \brief (SDADC_DBGCTRL) MASK Register */
/** \brief SDADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO SDADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO SDADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
__IO SDADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x02 (R/W 16) Control B */
__IO SDADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */
__IO SDADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
__IO SDADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
__IO SDADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status and Clear */
__I SDADC_SEQSTATUS_Type SEQSTATUS; /**< \brief Offset: 0x08 (R/ 8) Sequence Status */
__IO SDADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x09 (R/W 8) Input Control */
__IO SDADC_CTRLC_Type CTRLC; /**< \brief Offset: 0x0A (R/W 8) Control C */
__IO SDADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0B (R/W 8) Window Monitor Control */
__IO SDADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 32) Window Monitor Lower Threshold */
__IO SDADC_WINUT_Type WINUT; /**< \brief Offset: 0x10 (R/W 32) Window Monitor Upper Threshold */
__IO SDADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x14 (R/W 32) Offset Correction */
__IO SDADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x18 (R/W 16) Gain Correction */
__IO SDADC_SHIFTCORR_Type SHIFTCORR; /**< \brief Offset: 0x1A (R/W 8) Shift Correction */
RoReg8 Reserved1[0x1];
__IO SDADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x1C (R/W 8) Software Trigger */
RoReg8 Reserved2[0x3];
__I SDADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */
__I SDADC_RESULT_Type RESULT; /**< \brief Offset: 0x24 (R/ 32) Result */
__IO SDADC_SEQCTRL_Type SEQCTRL; /**< \brief Offset: 0x28 (R/W 8) Sequence Control */
RoReg8 Reserved3[0x3];
__IO SDADC_ANACTRL_Type ANACTRL; /**< \brief Offset: 0x2C (R/W 8) Analog Control */
RoReg8 Reserved4[0x1];
__IO SDADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2E (R/W 8) Debug Control */
} Sdadc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_SDADC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for SUPC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SUPC_COMPONENT_
#define _SAMC21_SUPC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR SUPC */
/* ========================================================================== */
/** \addtogroup SAMC21_SUPC Supply Controller */
/*@{*/
#define SUPC_U2117
#define REV_SUPC 0x211
/* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */
uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */
uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */
uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */
uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */
uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */
uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */
#define SUPC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */
#define SUPC_INTENCLR_BODVDDRDY_Pos 0 /**< \brief (SUPC_INTENCLR) BODVDD Ready */
#define SUPC_INTENCLR_BODVDDRDY (_U_(0x1) << SUPC_INTENCLR_BODVDDRDY_Pos)
#define SUPC_INTENCLR_BODVDDDET_Pos 1 /**< \brief (SUPC_INTENCLR) BODVDD Detection */
#define SUPC_INTENCLR_BODVDDDET (_U_(0x1) << SUPC_INTENCLR_BODVDDDET_Pos)
#define SUPC_INTENCLR_BVDDSRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BODVDD Synchronization Ready */
#define SUPC_INTENCLR_BVDDSRDY (_U_(0x1) << SUPC_INTENCLR_BVDDSRDY_Pos)
#define SUPC_INTENCLR_BODCORERDY_Pos 3 /**< \brief (SUPC_INTENCLR) BODCORE Ready */
#define SUPC_INTENCLR_BODCORERDY (_U_(0x1) << SUPC_INTENCLR_BODCORERDY_Pos)
#define SUPC_INTENCLR_BODCOREDET_Pos 4 /**< \brief (SUPC_INTENCLR) BODCORE Detection */
#define SUPC_INTENCLR_BODCOREDET (_U_(0x1) << SUPC_INTENCLR_BODCOREDET_Pos)
#define SUPC_INTENCLR_BCORESRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BODCORE Synchronization Ready */
#define SUPC_INTENCLR_BCORESRDY (_U_(0x1) << SUPC_INTENCLR_BCORESRDY_Pos)
#define SUPC_INTENCLR_MASK _U_(0x0000003F) /**< \brief (SUPC_INTENCLR) MASK Register */
/* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */
uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */
uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */
uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */
uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */
uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */
uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */
#define SUPC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */
#define SUPC_INTENSET_BODVDDRDY_Pos 0 /**< \brief (SUPC_INTENSET) BODVDD Ready */
#define SUPC_INTENSET_BODVDDRDY (_U_(0x1) << SUPC_INTENSET_BODVDDRDY_Pos)
#define SUPC_INTENSET_BODVDDDET_Pos 1 /**< \brief (SUPC_INTENSET) BODVDD Detection */
#define SUPC_INTENSET_BODVDDDET (_U_(0x1) << SUPC_INTENSET_BODVDDDET_Pos)
#define SUPC_INTENSET_BVDDSRDY_Pos 2 /**< \brief (SUPC_INTENSET) BODVDD Synchronization Ready */
#define SUPC_INTENSET_BVDDSRDY (_U_(0x1) << SUPC_INTENSET_BVDDSRDY_Pos)
#define SUPC_INTENSET_BODCORERDY_Pos 3 /**< \brief (SUPC_INTENSET) BODCORE Ready */
#define SUPC_INTENSET_BODCORERDY (_U_(0x1) << SUPC_INTENSET_BODCORERDY_Pos)
#define SUPC_INTENSET_BODCOREDET_Pos 4 /**< \brief (SUPC_INTENSET) BODCORE Detection */
#define SUPC_INTENSET_BODCOREDET (_U_(0x1) << SUPC_INTENSET_BODCOREDET_Pos)
#define SUPC_INTENSET_BCORESRDY_Pos 5 /**< \brief (SUPC_INTENSET) BODCORE Synchronization Ready */
#define SUPC_INTENSET_BCORESRDY (_U_(0x1) << SUPC_INTENSET_BCORESRDY_Pos)
#define SUPC_INTENSET_MASK _U_(0x0000003F) /**< \brief (SUPC_INTENSET) MASK Register */
/* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */
__I uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */
__I uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */
__I uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */
__I uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */
__I uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */
__I uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */
#define SUPC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define SUPC_INTFLAG_BODVDDRDY_Pos 0 /**< \brief (SUPC_INTFLAG) BODVDD Ready */
#define SUPC_INTFLAG_BODVDDRDY (_U_(0x1) << SUPC_INTFLAG_BODVDDRDY_Pos)
#define SUPC_INTFLAG_BODVDDDET_Pos 1 /**< \brief (SUPC_INTFLAG) BODVDD Detection */
#define SUPC_INTFLAG_BODVDDDET (_U_(0x1) << SUPC_INTFLAG_BODVDDDET_Pos)
#define SUPC_INTFLAG_BVDDSRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BODVDD Synchronization Ready */
#define SUPC_INTFLAG_BVDDSRDY (_U_(0x1) << SUPC_INTFLAG_BVDDSRDY_Pos)
#define SUPC_INTFLAG_BODCORERDY_Pos 3 /**< \brief (SUPC_INTFLAG) BODCORE Ready */
#define SUPC_INTFLAG_BODCORERDY (_U_(0x1) << SUPC_INTFLAG_BODCORERDY_Pos)
#define SUPC_INTFLAG_BODCOREDET_Pos 4 /**< \brief (SUPC_INTFLAG) BODCORE Detection */
#define SUPC_INTFLAG_BODCOREDET (_U_(0x1) << SUPC_INTFLAG_BODCOREDET_Pos)
#define SUPC_INTFLAG_BCORESRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BODCORE Synchronization Ready */
#define SUPC_INTFLAG_BCORESRDY (_U_(0x1) << SUPC_INTFLAG_BCORESRDY_Pos)
#define SUPC_INTFLAG_MASK _U_(0x0000003F) /**< \brief (SUPC_INTFLAG) MASK Register */
/* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */
uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */
uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */
uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */
uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */
uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */
uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */
#define SUPC_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */
#define SUPC_STATUS_BODVDDRDY_Pos 0 /**< \brief (SUPC_STATUS) BODVDD Ready */
#define SUPC_STATUS_BODVDDRDY (_U_(0x1) << SUPC_STATUS_BODVDDRDY_Pos)
#define SUPC_STATUS_BODVDDDET_Pos 1 /**< \brief (SUPC_STATUS) BODVDD Detection */
#define SUPC_STATUS_BODVDDDET (_U_(0x1) << SUPC_STATUS_BODVDDDET_Pos)
#define SUPC_STATUS_BVDDSRDY_Pos 2 /**< \brief (SUPC_STATUS) BODVDD Synchronization Ready */
#define SUPC_STATUS_BVDDSRDY (_U_(0x1) << SUPC_STATUS_BVDDSRDY_Pos)
#define SUPC_STATUS_BODCORERDY_Pos 3 /**< \brief (SUPC_STATUS) BODCORE Ready */
#define SUPC_STATUS_BODCORERDY (_U_(0x1) << SUPC_STATUS_BODCORERDY_Pos)
#define SUPC_STATUS_BODCOREDET_Pos 4 /**< \brief (SUPC_STATUS) BODCORE Detection */
#define SUPC_STATUS_BODCOREDET (_U_(0x1) << SUPC_STATUS_BODCOREDET_Pos)
#define SUPC_STATUS_BCORESRDY_Pos 5 /**< \brief (SUPC_STATUS) BODCORE Synchronization Ready */
#define SUPC_STATUS_BCORESRDY (_U_(0x1) << SUPC_STATUS_BCORESRDY_Pos)
#define SUPC_STATUS_MASK _U_(0x0000003F) /**< \brief (SUPC_STATUS) MASK Register */
/* -------- SUPC_BODVDD : (SUPC Offset: 0x10) (R/W 32) BODVDD Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */
uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */
uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */
uint32_t :3; /*!< bit: 9..11 Reserved */
uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level for VDD */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_BODVDD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_BODVDD_OFFSET 0x10 /**< \brief (SUPC_BODVDD offset) BODVDD Control */
#define SUPC_BODVDD_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BODVDD reset_value) BODVDD Control */
#define SUPC_BODVDD_ENABLE_Pos 1 /**< \brief (SUPC_BODVDD) Enable */
#define SUPC_BODVDD_ENABLE (_U_(0x1) << SUPC_BODVDD_ENABLE_Pos)
#define SUPC_BODVDD_HYST_Pos 2 /**< \brief (SUPC_BODVDD) Hysteresis Enable */
#define SUPC_BODVDD_HYST (_U_(0x1) << SUPC_BODVDD_HYST_Pos)
#define SUPC_BODVDD_ACTION_Pos 3 /**< \brief (SUPC_BODVDD) Action when Threshold Crossed */
#define SUPC_BODVDD_ACTION_Msk (_U_(0x3) << SUPC_BODVDD_ACTION_Pos)
#define SUPC_BODVDD_ACTION(value) (SUPC_BODVDD_ACTION_Msk & ((value) << SUPC_BODVDD_ACTION_Pos))
#define SUPC_BODVDD_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BODVDD) No action */
#define SUPC_BODVDD_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BODVDD) The BOD33 generates a reset */
#define SUPC_BODVDD_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BODVDD) The BOD33 generates an interrupt */
#define SUPC_BODVDD_ACTION_NONE (SUPC_BODVDD_ACTION_NONE_Val << SUPC_BODVDD_ACTION_Pos)
#define SUPC_BODVDD_ACTION_RESET (SUPC_BODVDD_ACTION_RESET_Val << SUPC_BODVDD_ACTION_Pos)
#define SUPC_BODVDD_ACTION_INT (SUPC_BODVDD_ACTION_INT_Val << SUPC_BODVDD_ACTION_Pos)
#define SUPC_BODVDD_STDBYCFG_Pos 5 /**< \brief (SUPC_BODVDD) Configuration in Standby mode */
#define SUPC_BODVDD_STDBYCFG (_U_(0x1) << SUPC_BODVDD_STDBYCFG_Pos)
#define SUPC_BODVDD_RUNSTDBY_Pos 6 /**< \brief (SUPC_BODVDD) Run during Standby */
#define SUPC_BODVDD_RUNSTDBY (_U_(0x1) << SUPC_BODVDD_RUNSTDBY_Pos)
#define SUPC_BODVDD_ACTCFG_Pos 8 /**< \brief (SUPC_BODVDD) Configuration in Active mode */
#define SUPC_BODVDD_ACTCFG (_U_(0x1) << SUPC_BODVDD_ACTCFG_Pos)
#define SUPC_BODVDD_PSEL_Pos 12 /**< \brief (SUPC_BODVDD) Prescaler Select */
#define SUPC_BODVDD_PSEL_Msk (_U_(0xF) << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL(value) (SUPC_BODVDD_PSEL_Msk & ((value) << SUPC_BODVDD_PSEL_Pos))
#define SUPC_BODVDD_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BODVDD) Divide clock by 2 */
#define SUPC_BODVDD_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BODVDD) Divide clock by 4 */
#define SUPC_BODVDD_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BODVDD) Divide clock by 8 */
#define SUPC_BODVDD_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BODVDD) Divide clock by 16 */
#define SUPC_BODVDD_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BODVDD) Divide clock by 32 */
#define SUPC_BODVDD_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BODVDD) Divide clock by 64 */
#define SUPC_BODVDD_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BODVDD) Divide clock by 128 */
#define SUPC_BODVDD_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BODVDD) Divide clock by 256 */
#define SUPC_BODVDD_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BODVDD) Divide clock by 512 */
#define SUPC_BODVDD_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BODVDD) Divide clock by 1024 */
#define SUPC_BODVDD_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BODVDD) Divide clock by 2048 */
#define SUPC_BODVDD_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BODVDD) Divide clock by 4096 */
#define SUPC_BODVDD_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BODVDD) Divide clock by 8192 */
#define SUPC_BODVDD_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BODVDD) Divide clock by 16384 */
#define SUPC_BODVDD_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BODVDD) Divide clock by 32768 */
#define SUPC_BODVDD_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BODVDD) Divide clock by 65536 */
#define SUPC_BODVDD_PSEL_DIV2 (SUPC_BODVDD_PSEL_DIV2_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV4 (SUPC_BODVDD_PSEL_DIV4_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV8 (SUPC_BODVDD_PSEL_DIV8_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV16 (SUPC_BODVDD_PSEL_DIV16_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV32 (SUPC_BODVDD_PSEL_DIV32_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV64 (SUPC_BODVDD_PSEL_DIV64_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV128 (SUPC_BODVDD_PSEL_DIV128_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV256 (SUPC_BODVDD_PSEL_DIV256_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV512 (SUPC_BODVDD_PSEL_DIV512_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV1024 (SUPC_BODVDD_PSEL_DIV1024_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV2048 (SUPC_BODVDD_PSEL_DIV2048_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV4096 (SUPC_BODVDD_PSEL_DIV4096_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV8192 (SUPC_BODVDD_PSEL_DIV8192_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV16384 (SUPC_BODVDD_PSEL_DIV16384_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV32768 (SUPC_BODVDD_PSEL_DIV32768_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_PSEL_DIV65536 (SUPC_BODVDD_PSEL_DIV65536_Val << SUPC_BODVDD_PSEL_Pos)
#define SUPC_BODVDD_LEVEL_Pos 16 /**< \brief (SUPC_BODVDD) Threshold Level for VDD */
#define SUPC_BODVDD_LEVEL_Msk (_U_(0x3F) << SUPC_BODVDD_LEVEL_Pos)
#define SUPC_BODVDD_LEVEL(value) (SUPC_BODVDD_LEVEL_Msk & ((value) << SUPC_BODVDD_LEVEL_Pos))
#define SUPC_BODVDD_MASK _U_(0x003FF17E) /**< \brief (SUPC_BODVDD) MASK Register */
/* -------- SUPC_BODCORE : (SUPC Offset: 0x14) (R/W 32) BODCORE Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */
uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */
uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */
uint32_t :3; /*!< bit: 9..11 Reserved */
uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_BODCORE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_BODCORE_OFFSET 0x14 /**< \brief (SUPC_BODCORE offset) BODCORE Control */
#define SUPC_BODCORE_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BODCORE reset_value) BODCORE Control */
#define SUPC_BODCORE_ENABLE_Pos 1 /**< \brief (SUPC_BODCORE) Enable */
#define SUPC_BODCORE_ENABLE (_U_(0x1) << SUPC_BODCORE_ENABLE_Pos)
#define SUPC_BODCORE_HYST_Pos 2 /**< \brief (SUPC_BODCORE) Hysteresis Enable */
#define SUPC_BODCORE_HYST (_U_(0x1) << SUPC_BODCORE_HYST_Pos)
#define SUPC_BODCORE_ACTION_Pos 3 /**< \brief (SUPC_BODCORE) Action when Threshold Crossed */
#define SUPC_BODCORE_ACTION_Msk (_U_(0x3) << SUPC_BODCORE_ACTION_Pos)
#define SUPC_BODCORE_ACTION(value) (SUPC_BODCORE_ACTION_Msk & ((value) << SUPC_BODCORE_ACTION_Pos))
#define SUPC_BODCORE_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BODCORE) No action */
#define SUPC_BODCORE_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BODCORE) The BOD12 generates a reset */
#define SUPC_BODCORE_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BODCORE) The BOD12 generates an interrupt */
#define SUPC_BODCORE_ACTION_NONE (SUPC_BODCORE_ACTION_NONE_Val << SUPC_BODCORE_ACTION_Pos)
#define SUPC_BODCORE_ACTION_RESET (SUPC_BODCORE_ACTION_RESET_Val << SUPC_BODCORE_ACTION_Pos)
#define SUPC_BODCORE_ACTION_INT (SUPC_BODCORE_ACTION_INT_Val << SUPC_BODCORE_ACTION_Pos)
#define SUPC_BODCORE_STDBYCFG_Pos 5 /**< \brief (SUPC_BODCORE) Configuration in Standby mode */
#define SUPC_BODCORE_STDBYCFG (_U_(0x1) << SUPC_BODCORE_STDBYCFG_Pos)
#define SUPC_BODCORE_RUNSTDBY_Pos 6 /**< \brief (SUPC_BODCORE) Run during Standby */
#define SUPC_BODCORE_RUNSTDBY (_U_(0x1) << SUPC_BODCORE_RUNSTDBY_Pos)
#define SUPC_BODCORE_ACTCFG_Pos 8 /**< \brief (SUPC_BODCORE) Configuration in Active mode */
#define SUPC_BODCORE_ACTCFG (_U_(0x1) << SUPC_BODCORE_ACTCFG_Pos)
#define SUPC_BODCORE_PSEL_Pos 12 /**< \brief (SUPC_BODCORE) Prescaler Select */
#define SUPC_BODCORE_PSEL_Msk (_U_(0xF) << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL(value) (SUPC_BODCORE_PSEL_Msk & ((value) << SUPC_BODCORE_PSEL_Pos))
#define SUPC_BODCORE_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BODCORE) Divide clock by 2 */
#define SUPC_BODCORE_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BODCORE) Divide clock by 4 */
#define SUPC_BODCORE_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BODCORE) Divide clock by 8 */
#define SUPC_BODCORE_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BODCORE) Divide clock by 16 */
#define SUPC_BODCORE_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BODCORE) Divide clock by 32 */
#define SUPC_BODCORE_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BODCORE) Divide clock by 64 */
#define SUPC_BODCORE_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BODCORE) Divide clock by 128 */
#define SUPC_BODCORE_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BODCORE) Divide clock by 256 */
#define SUPC_BODCORE_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BODCORE) Divide clock by 512 */
#define SUPC_BODCORE_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BODCORE) Divide clock by 1024 */
#define SUPC_BODCORE_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BODCORE) Divide clock by 2048 */
#define SUPC_BODCORE_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BODCORE) Divide clock by 4096 */
#define SUPC_BODCORE_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BODCORE) Divide clock by 8192 */
#define SUPC_BODCORE_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BODCORE) Divide clock by 16384 */
#define SUPC_BODCORE_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BODCORE) Divide clock by 32768 */
#define SUPC_BODCORE_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BODCORE) Divide clock by 65536 */
#define SUPC_BODCORE_PSEL_DIV2 (SUPC_BODCORE_PSEL_DIV2_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV4 (SUPC_BODCORE_PSEL_DIV4_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV8 (SUPC_BODCORE_PSEL_DIV8_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV16 (SUPC_BODCORE_PSEL_DIV16_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV32 (SUPC_BODCORE_PSEL_DIV32_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV64 (SUPC_BODCORE_PSEL_DIV64_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV128 (SUPC_BODCORE_PSEL_DIV128_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV256 (SUPC_BODCORE_PSEL_DIV256_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV512 (SUPC_BODCORE_PSEL_DIV512_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV1024 (SUPC_BODCORE_PSEL_DIV1024_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV2048 (SUPC_BODCORE_PSEL_DIV2048_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV4096 (SUPC_BODCORE_PSEL_DIV4096_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV8192 (SUPC_BODCORE_PSEL_DIV8192_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV16384 (SUPC_BODCORE_PSEL_DIV16384_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV32768 (SUPC_BODCORE_PSEL_DIV32768_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_PSEL_DIV65536 (SUPC_BODCORE_PSEL_DIV65536_Val << SUPC_BODCORE_PSEL_Pos)
#define SUPC_BODCORE_LEVEL_Pos 16 /**< \brief (SUPC_BODCORE) Threshold Level */
#define SUPC_BODCORE_LEVEL_Msk (_U_(0x3F) << SUPC_BODCORE_LEVEL_Pos)
#define SUPC_BODCORE_LEVEL(value) (SUPC_BODCORE_LEVEL_Msk & ((value) << SUPC_BODCORE_LEVEL_Pos))
#define SUPC_BODCORE_MASK _U_(0x003FF17E) /**< \brief (SUPC_BODCORE) MASK Register */
/* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t :4; /*!< bit: 2.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_VREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */
#define SUPC_VREG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREG reset_value) VREG Control */
#define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */
#define SUPC_VREG_ENABLE (_U_(0x1) << SUPC_VREG_ENABLE_Pos)
#define SUPC_VREG_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREG) Run during Standby */
#define SUPC_VREG_RUNSTDBY (_U_(0x1) << SUPC_VREG_RUNSTDBY_Pos)
#define SUPC_VREG_MASK _U_(0x00000042) /**< \brief (SUPC_VREG) MASK Register */
/* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */
uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */
uint32_t :3; /*!< bit: 3.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */
uint32_t :8; /*!< bit: 8..15 Reserved */
uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SUPC_VREF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */
#define SUPC_VREF_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */
#define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */
#define SUPC_VREF_TSEN (_U_(0x1) << SUPC_VREF_TSEN_Pos)
#define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */
#define SUPC_VREF_VREFOE (_U_(0x1) << SUPC_VREF_VREFOE_Pos)
#define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */
#define SUPC_VREF_RUNSTDBY (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos)
#define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */
#define SUPC_VREF_ONDEMAND (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos)
#define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */
#define SUPC_VREF_SEL_Msk (_U_(0xF) << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))
#define SUPC_VREF_SEL_1V024_Val _U_(0x0) /**< \brief (SUPC_VREF) 1.024V voltage reference typical value */
#define SUPC_VREF_SEL_2V048_Val _U_(0x2) /**< \brief (SUPC_VREF) 2.048V voltage reference typical value */
#define SUPC_VREF_SEL_4V096_Val _U_(0x3) /**< \brief (SUPC_VREF) 4.096V voltage reference typical value */
#define SUPC_VREF_SEL_1V024 (SUPC_VREF_SEL_1V024_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL_2V048 (SUPC_VREF_SEL_2V048_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_SEL_4V096 (SUPC_VREF_SEL_4V096_Val << SUPC_VREF_SEL_Pos)
#define SUPC_VREF_MASK _U_(0x000F00C6) /**< \brief (SUPC_VREF) MASK Register */
/** \brief SUPC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO SUPC_BODVDD_Type BODVDD; /**< \brief Offset: 0x10 (R/W 32) BODVDD Control */
__IO SUPC_BODCORE_Type BODCORE; /**< \brief Offset: 0x14 (R/W 32) BODCORE Control */
__IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */
__IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */
} Supc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_SUPC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for TC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC_COMPONENT_
#define _SAMC21_TC_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR TC */
/* ========================================================================== */
/** \addtogroup SAMC21_TC Basic Timer Counter */
/*@{*/
#define TC_U2249
#define REV_TC 0x200
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */
uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */
uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */
uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */
uint32_t :2; /*!< bit: 18..19 Reserved */
uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */
uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */
uint32_t :2; /*!< bit: 18..19 Reserved */
uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */
uint32_t :10; /*!< bit: 22..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */
#define TC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */
#define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */
#define TC_CTRLA_SWRST (_U_(0x1) << TC_CTRLA_SWRST_Pos)
#define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */
#define TC_CTRLA_ENABLE (_U_(0x1) << TC_CTRLA_ENABLE_Pos)
#define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */
#define TC_CTRLA_MODE_Msk (_U_(0x3) << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos))
#define TC_CTRLA_MODE_COUNT16_Val _U_(0x0) /**< \brief (TC_CTRLA) Counter in 16-bit mode */
#define TC_CTRLA_MODE_COUNT8_Val _U_(0x1) /**< \brief (TC_CTRLA) Counter in 8-bit mode */
#define TC_CTRLA_MODE_COUNT32_Val _U_(0x2) /**< \brief (TC_CTRLA) Counter in 32-bit mode */
#define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos)
#define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */
#define TC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos))
#define TC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */
#define TC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */
#define TC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */
#define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos)
#define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */
#define TC_CTRLA_RUNSTDBY (_U_(0x1) << TC_CTRLA_RUNSTDBY_Pos)
#define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */
#define TC_CTRLA_ONDEMAND (_U_(0x1) << TC_CTRLA_ONDEMAND_Pos)
#define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */
#define TC_CTRLA_PRESCALER_Msk (_U_(0x7) << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos))
#define TC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */
#define TC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */
#define TC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */
#define TC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */
#define TC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */
#define TC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */
#define TC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */
#define TC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */
#define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos)
#define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */
#define TC_CTRLA_ALOCK (_U_(0x1) << TC_CTRLA_ALOCK_Pos)
#define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */
#define TC_CTRLA_CAPTEN0 (_U_(1) << TC_CTRLA_CAPTEN0_Pos)
#define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */
#define TC_CTRLA_CAPTEN1 (_U_(1) << TC_CTRLA_CAPTEN1_Pos)
#define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */
#define TC_CTRLA_CAPTEN_Msk (_U_(0x3) << TC_CTRLA_CAPTEN_Pos)
#define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos))
#define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */
#define TC_CTRLA_COPEN0 (_U_(1) << TC_CTRLA_COPEN0_Pos)
#define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */
#define TC_CTRLA_COPEN1 (_U_(1) << TC_CTRLA_COPEN1_Pos)
#define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */
#define TC_CTRLA_COPEN_Msk (_U_(0x3) << TC_CTRLA_COPEN_Pos)
#define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos))
#define TC_CTRLA_MASK _U_(0x00330FFF) /**< \brief (TC_CTRLA) MASK Register */
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t LUPD:1; /*!< bit: 1 Lock Update */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
uint8_t :2; /*!< bit: 3.. 4 Reserved */
uint8_t CMD:3; /*!< bit: 5.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */
#define TC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */
#define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */
#define TC_CTRLBCLR_DIR (_U_(0x1) << TC_CTRLBCLR_DIR_Pos)
#define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */
#define TC_CTRLBCLR_LUPD (_U_(0x1) << TC_CTRLBCLR_LUPD_Pos)
#define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */
#define TC_CTRLBCLR_ONESHOT (_U_(0x1) << TC_CTRLBCLR_ONESHOT_Pos)
#define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */
#define TC_CTRLBCLR_CMD_Msk (_U_(0x7) << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos))
#define TC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBCLR) No action */
#define TC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */
#define TC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBCLR) Force a stop */
#define TC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */
#define TC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */
#define TC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */
#define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos)
#define TC_CTRLBCLR_MASK _U_(0xE7) /**< \brief (TC_CTRLBCLR) MASK Register */
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t LUPD:1; /*!< bit: 1 Lock Update */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
uint8_t :2; /*!< bit: 3.. 4 Reserved */
uint8_t CMD:3; /*!< bit: 5.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */
#define TC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TC_CTRLBSET reset_value) Control B Set */
#define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */
#define TC_CTRLBSET_DIR (_U_(0x1) << TC_CTRLBSET_DIR_Pos)
#define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */
#define TC_CTRLBSET_LUPD (_U_(0x1) << TC_CTRLBSET_LUPD_Pos)
#define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */
#define TC_CTRLBSET_ONESHOT (_U_(0x1) << TC_CTRLBSET_ONESHOT_Pos)
#define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */
#define TC_CTRLBSET_CMD_Msk (_U_(0x7) << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos))
#define TC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TC_CTRLBSET) No action */
#define TC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */
#define TC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TC_CTRLBSET) Force a stop */
#define TC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TC_CTRLBSET) Force update of double-buffered register */
#define TC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */
#define TC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TC_CTRLBSET) One-shot DMA trigger */
#define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos)
#define TC_CTRLBSET_MASK _U_(0xE7) /**< \brief (TC_CTRLBSET) MASK Register */
/* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
uint16_t :1; /*!< bit: 3 Reserved */
uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */
uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */
uint16_t :3; /*!< bit: 9..11 Reserved */
uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */
uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :12; /*!< bit: 0..11 Reserved */
uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */
#define TC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (TC_EVCTRL reset_value) Event Control */
#define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */
#define TC_EVCTRL_EVACT_Msk (_U_(0x7) << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos))
#define TC_EVCTRL_EVACT_OFF_Val _U_(0x0) /**< \brief (TC_EVCTRL) Event action disabled */
#define TC_EVCTRL_EVACT_RETRIGGER_Val _U_(0x1) /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */
#define TC_EVCTRL_EVACT_COUNT_Val _U_(0x2) /**< \brief (TC_EVCTRL) Count on event */
#define TC_EVCTRL_EVACT_START_Val _U_(0x3) /**< \brief (TC_EVCTRL) Start TC on event */
#define TC_EVCTRL_EVACT_STAMP_Val _U_(0x4) /**< \brief (TC_EVCTRL) Time stamp capture */
#define TC_EVCTRL_EVACT_PPW_Val _U_(0x5) /**< \brief (TC_EVCTRL) Period catured in CC0, pulse width in CC1 */
#define TC_EVCTRL_EVACT_PWP_Val _U_(0x6) /**< \brief (TC_EVCTRL) Period catured in CC1, pulse width in CC0 */
#define TC_EVCTRL_EVACT_PW_Val _U_(0x7) /**< \brief (TC_EVCTRL) Pulse width capture */
#define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos)
#define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */
#define TC_EVCTRL_TCINV (_U_(0x1) << TC_EVCTRL_TCINV_Pos)
#define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */
#define TC_EVCTRL_TCEI (_U_(0x1) << TC_EVCTRL_TCEI_Pos)
#define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */
#define TC_EVCTRL_OVFEO (_U_(0x1) << TC_EVCTRL_OVFEO_Pos)
#define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */
#define TC_EVCTRL_MCEO0 (_U_(1) << TC_EVCTRL_MCEO0_Pos)
#define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */
#define TC_EVCTRL_MCEO1 (_U_(1) << TC_EVCTRL_MCEO1_Pos)
#define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */
#define TC_EVCTRL_MCEO_Msk (_U_(0x3) << TC_EVCTRL_MCEO_Pos)
#define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos))
#define TC_EVCTRL_MASK _U_(0x3137) /**< \brief (TC_EVCTRL) MASK Register */
/* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */
uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */
uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */
#define TC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */
#define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */
#define TC_INTENCLR_OVF (_U_(0x1) << TC_INTENCLR_OVF_Pos)
#define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */
#define TC_INTENCLR_ERR (_U_(0x1) << TC_INTENCLR_ERR_Pos)
#define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */
#define TC_INTENCLR_MC0 (_U_(1) << TC_INTENCLR_MC0_Pos)
#define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */
#define TC_INTENCLR_MC1 (_U_(1) << TC_INTENCLR_MC1_Pos)
#define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */
#define TC_INTENCLR_MC_Msk (_U_(0x3) << TC_INTENCLR_MC_Pos)
#define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos))
#define TC_INTENCLR_MASK _U_(0x33) /**< \brief (TC_INTENCLR) MASK Register */
/* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */
uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */
#define TC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */
#define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */
#define TC_INTENSET_OVF (_U_(0x1) << TC_INTENSET_OVF_Pos)
#define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */
#define TC_INTENSET_ERR (_U_(0x1) << TC_INTENSET_ERR_Pos)
#define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */
#define TC_INTENSET_MC0 (_U_(1) << TC_INTENSET_MC0_Pos)
#define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */
#define TC_INTENSET_MC1 (_U_(1) << TC_INTENSET_MC1_Pos)
#define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */
#define TC_INTENSET_MC_Msk (_U_(0x3) << TC_INTENSET_MC_Pos)
#define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos))
#define TC_INTENSET_MASK _U_(0x33) /**< \brief (TC_INTENSET) MASK Register */
/* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */
__I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
__I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */
__I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t :4; /*!< bit: 0.. 3 Reserved */
__I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */
__I uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */
#define TC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */
#define TC_INTFLAG_OVF (_U_(0x1) << TC_INTFLAG_OVF_Pos)
#define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */
#define TC_INTFLAG_ERR (_U_(0x1) << TC_INTFLAG_ERR_Pos)
#define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */
#define TC_INTFLAG_MC0 (_U_(1) << TC_INTFLAG_MC0_Pos)
#define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */
#define TC_INTFLAG_MC1 (_U_(1) << TC_INTFLAG_MC1_Pos)
#define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */
#define TC_INTFLAG_MC_Msk (_U_(0x3) << TC_INTFLAG_MC_Pos)
#define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos))
#define TC_INTFLAG_MASK _U_(0x33) /**< \brief (TC_INTFLAG) MASK Register */
/* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */
uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */
uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */
uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */
#define TC_STATUS_RESETVALUE _U_(0x01) /**< \brief (TC_STATUS reset_value) Status */
#define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */
#define TC_STATUS_STOP (_U_(0x1) << TC_STATUS_STOP_Pos)
#define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */
#define TC_STATUS_SLAVE (_U_(0x1) << TC_STATUS_SLAVE_Pos)
#define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */
#define TC_STATUS_PERBUFV (_U_(0x1) << TC_STATUS_PERBUFV_Pos)
#define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */
#define TC_STATUS_CCBUFV0 (_U_(1) << TC_STATUS_CCBUFV0_Pos)
#define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */
#define TC_STATUS_CCBUFV1 (_U_(1) << TC_STATUS_CCBUFV1_Pos)
#define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */
#define TC_STATUS_CCBUFV_Msk (_U_(0x3) << TC_STATUS_CCBUFV_Pos)
#define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos))
#define TC_STATUS_MASK _U_(0x3B) /**< \brief (TC_STATUS) MASK Register */
/* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_WAVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */
#define TC_WAVE_RESETVALUE _U_(0x00) /**< \brief (TC_WAVE reset_value) Waveform Generation Control */
#define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */
#define TC_WAVE_WAVEGEN_Msk (_U_(0x3) << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos))
#define TC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TC_WAVE) Normal frequency */
#define TC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TC_WAVE) Match frequency */
#define TC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TC_WAVE) Normal PWM */
#define TC_WAVE_WAVEGEN_MPWM_Val _U_(0x3) /**< \brief (TC_WAVE) Match PWM */
#define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos)
#define TC_WAVE_MASK _U_(0x03) /**< \brief (TC_WAVE) MASK Register */
/* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */
uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_DRVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */
#define TC_DRVCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DRVCTRL reset_value) Control C */
#define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */
#define TC_DRVCTRL_INVEN0 (_U_(1) << TC_DRVCTRL_INVEN0_Pos)
#define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */
#define TC_DRVCTRL_INVEN1 (_U_(1) << TC_DRVCTRL_INVEN1_Pos)
#define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */
#define TC_DRVCTRL_INVEN_Msk (_U_(0x3) << TC_DRVCTRL_INVEN_Pos)
#define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos))
#define TC_DRVCTRL_MASK _U_(0x03) /**< \brief (TC_DRVCTRL) MASK Register */
/* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */
#define TC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TC_DBGCTRL reset_value) Debug Control */
#define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */
#define TC_DBGCTRL_DBGRUN (_U_(0x1) << TC_DBGCTRL_DBGRUN_Pos)
#define TC_DBGCTRL_MASK _U_(0x01) /**< \brief (TC_DBGCTRL) MASK Register */
/* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 swrst */
uint32_t ENABLE:1; /*!< bit: 1 enable */
uint32_t CTRLB:1; /*!< bit: 2 CTRLB */
uint32_t STATUS:1; /*!< bit: 3 STATUS */
uint32_t COUNT:1; /*!< bit: 4 Counter */
uint32_t PER:1; /*!< bit: 5 Period */
uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */
uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :6; /*!< bit: 0.. 5 Reserved */
uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */
uint32_t :24; /*!< bit: 8..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} TC_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */
#define TC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */
#define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */
#define TC_SYNCBUSY_SWRST (_U_(0x1) << TC_SYNCBUSY_SWRST_Pos)
#define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */
#define TC_SYNCBUSY_ENABLE (_U_(0x1) << TC_SYNCBUSY_ENABLE_Pos)
#define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */
#define TC_SYNCBUSY_CTRLB (_U_(0x1) << TC_SYNCBUSY_CTRLB_Pos)
#define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */
#define TC_SYNCBUSY_STATUS (_U_(0x1) << TC_SYNCBUSY_STATUS_Pos)
#define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */
#define TC_SYNCBUSY_COUNT (_U_(0x1) << TC_SYNCBUSY_COUNT_Pos)
#define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */
#define TC_SYNCBUSY_PER (_U_(0x1) << TC_SYNCBUSY_PER_Pos)
#define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */
#define TC_SYNCBUSY_CC0 (_U_(1) << TC_SYNCBUSY_CC0_Pos)
#define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */
#define TC_SYNCBUSY_CC1 (_U_(1) << TC_SYNCBUSY_CC1_Pos)
#define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */
#define TC_SYNCBUSY_CC_Msk (_U_(0x3) << TC_SYNCBUSY_CC_Pos)
#define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos))
#define TC_SYNCBUSY_MASK _U_(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */
#define TC_COUNT16_COUNT_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */
#define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */
#define TC_COUNT16_COUNT_COUNT_Msk (_U_(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos)
#define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos))
#define TC_COUNT16_COUNT_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_COUNT) MASK Register */
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */
#define TC_COUNT32_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */
#define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */
#define TC_COUNT32_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos)
#define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos))
#define TC_COUNT32_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */
#define TC_COUNT8_COUNT_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */
#define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */
#define TC_COUNT8_COUNT_COUNT_Msk (_U_(0xFF) << TC_COUNT8_COUNT_COUNT_Pos)
#define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos))
#define TC_COUNT8_COUNT_MASK _U_(0xFF) /**< \brief (TC_COUNT8_COUNT) MASK Register */
/* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */
#define TC_COUNT8_PER_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */
#define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */
#define TC_COUNT8_PER_PER_Msk (_U_(0xFF) << TC_COUNT8_PER_PER_Pos)
#define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos))
#define TC_COUNT8_PER_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PER) MASK Register */
/* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */
#define TC_COUNT16_CC_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */
#define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */
#define TC_COUNT16_CC_CC_Msk (_U_(0xFFFF) << TC_COUNT16_CC_CC_Pos)
#define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos))
#define TC_COUNT16_CC_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CC) MASK Register */
/* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */
#define TC_COUNT32_CC_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */
#define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */
#define TC_COUNT32_CC_CC_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos)
#define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos))
#define TC_COUNT32_CC_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */
/* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */
#define TC_COUNT8_CC_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */
#define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */
#define TC_COUNT8_CC_CC_Msk (_U_(0xFF) << TC_COUNT8_CC_CC_Pos)
#define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos))
#define TC_COUNT8_CC_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CC) MASK Register */
/* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PERBUF:8; /*!< bit: 0.. 7 Period Buffer Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PERBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */
#define TC_COUNT8_PERBUF_RESETVALUE _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */
#define TC_COUNT8_PERBUF_PERBUF_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */
#define TC_COUNT8_PERBUF_PERBUF_Msk (_U_(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos)
#define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos))
#define TC_COUNT8_PERBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_PERBUF) MASK Register */
/* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */
#define TC_COUNT16_CCBUF_RESETVALUE _U_(0x0000) /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */
#define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */
#define TC_COUNT16_CCBUF_CCBUF_Msk (_U_(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos)
#define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos))
#define TC_COUNT16_CCBUF_MASK _U_(0xFFFF) /**< \brief (TC_COUNT16_CCBUF) MASK Register */
/* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */
#define TC_COUNT32_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */
#define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */
#define TC_COUNT32_CCBUF_CCBUF_Msk (_U_(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos)
#define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos))
#define TC_COUNT32_CCBUF_MASK _U_(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */
/* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CCBUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */
#define TC_COUNT8_CCBUF_RESETVALUE _U_(0x00) /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */
#define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */
#define TC_COUNT8_CCBUF_CCBUF_Msk (_U_(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos)
#define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos))
#define TC_COUNT8_CCBUF_MASK _U_(0xFF) /**< \brief (TC_COUNT8_CCBUF) MASK Register */
/** \brief TC_COUNT8 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
__IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
__IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
__I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
__IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */
RoReg8 Reserved2[0x6];
__IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */
__IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */
RoReg8 Reserved3[0x11];
__IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */
__IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT16 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
__IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
__IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
__I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
__IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */
RoReg8 Reserved2[0x6];
__IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */
RoReg8 Reserved3[0x10];
__IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT32 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
__IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */
__IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */
__IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */
__I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */
__IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */
RoReg8 Reserved2[0x4];
__IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */
RoReg8 Reserved3[0xC];
__IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_TC_COMPONENT_ */

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/**
* \file
*
* \brief Component description for TSENS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TSENS_COMPONENT_
#define _SAMC21_TSENS_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR TSENS */
/* ========================================================================== */
/** \addtogroup SAMC21_TSENS Temperature Sensor */
/*@{*/
#define TSENS_U2261
#define REV_TSENS 0x101
/* -------- TSENS_CTRLA : (TSENS Offset: 0x00) (R/W 8) Control A Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TSENS_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_CTRLA_OFFSET 0x00 /**< \brief (TSENS_CTRLA offset) Control A Register */
#define TSENS_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TSENS_CTRLA reset_value) Control A Register */
#define TSENS_CTRLA_SWRST_Pos 0 /**< \brief (TSENS_CTRLA) Software Reset */
#define TSENS_CTRLA_SWRST (_U_(0x1) << TSENS_CTRLA_SWRST_Pos)
#define TSENS_CTRLA_ENABLE_Pos 1 /**< \brief (TSENS_CTRLA) Enable */
#define TSENS_CTRLA_ENABLE (_U_(0x1) << TSENS_CTRLA_ENABLE_Pos)
#define TSENS_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TSENS_CTRLA) Run in Standby */
#define TSENS_CTRLA_RUNSTDBY (_U_(0x1) << TSENS_CTRLA_RUNSTDBY_Pos)
#define TSENS_CTRLA_MASK _U_(0x43) /**< \brief (TSENS_CTRLA) MASK Register */
/* -------- TSENS_CTRLB : (TSENS Offset: 0x01) ( /W 8) Control B Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START:1; /*!< bit: 0 Start Measurement */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TSENS_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_CTRLB_OFFSET 0x01 /**< \brief (TSENS_CTRLB offset) Control B Register */
#define TSENS_CTRLB_RESETVALUE _U_(0x00) /**< \brief (TSENS_CTRLB reset_value) Control B Register */
#define TSENS_CTRLB_START_Pos 0 /**< \brief (TSENS_CTRLB) Start Measurement */
#define TSENS_CTRLB_START (_U_(0x1) << TSENS_CTRLB_START_Pos)
#define TSENS_CTRLB_MASK _U_(0x01) /**< \brief (TSENS_CTRLB) MASK Register */
/* -------- TSENS_CTRLC : (TSENS Offset: 0x02) (R/W 8) Control C Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t FREERUN:1; /*!< bit: 4 Free Running Measurement */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TSENS_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_CTRLC_OFFSET 0x02 /**< \brief (TSENS_CTRLC offset) Control C Register */
#define TSENS_CTRLC_RESETVALUE _U_(0x00) /**< \brief (TSENS_CTRLC reset_value) Control C Register */
#define TSENS_CTRLC_WINMODE_Pos 0 /**< \brief (TSENS_CTRLC) Window Monitor Mode */
#define TSENS_CTRLC_WINMODE_Msk (_U_(0x7) << TSENS_CTRLC_WINMODE_Pos)
#define TSENS_CTRLC_WINMODE(value) (TSENS_CTRLC_WINMODE_Msk & ((value) << TSENS_CTRLC_WINMODE_Pos))
#define TSENS_CTRLC_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (TSENS_CTRLC) No window mode (default) */
#define TSENS_CTRLC_WINMODE_ABOVE_Val _U_(0x1) /**< \brief (TSENS_CTRLC) VALUE greater than WINLT */
#define TSENS_CTRLC_WINMODE_BELOW_Val _U_(0x2) /**< \brief (TSENS_CTRLC) VALUE less than WINUT */
#define TSENS_CTRLC_WINMODE_INSIDE_Val _U_(0x3) /**< \brief (TSENS_CTRLC) VALUE greater than WINLT and VALUE less than WINUT */
#define TSENS_CTRLC_WINMODE_OUTSIDE_Val _U_(0x4) /**< \brief (TSENS_CTRLC) VALUE less than WINLT or VALUE greater than WINUT */
#define TSENS_CTRLC_WINMODE_HYST_ABOVE_Val _U_(0x5) /**< \brief (TSENS_CTRLC) VALUE greater than WINUT with hysteresis to WINLT */
#define TSENS_CTRLC_WINMODE_HYST_BELOW_Val _U_(0x6) /**< \brief (TSENS_CTRLC) VALUE less than WINLST with hysteresis to WINUT */
#define TSENS_CTRLC_WINMODE_DISABLE (TSENS_CTRLC_WINMODE_DISABLE_Val << TSENS_CTRLC_WINMODE_Pos)
#define TSENS_CTRLC_WINMODE_ABOVE (TSENS_CTRLC_WINMODE_ABOVE_Val << TSENS_CTRLC_WINMODE_Pos)
#define TSENS_CTRLC_WINMODE_BELOW (TSENS_CTRLC_WINMODE_BELOW_Val << TSENS_CTRLC_WINMODE_Pos)
#define TSENS_CTRLC_WINMODE_INSIDE (TSENS_CTRLC_WINMODE_INSIDE_Val << TSENS_CTRLC_WINMODE_Pos)
#define TSENS_CTRLC_WINMODE_OUTSIDE (TSENS_CTRLC_WINMODE_OUTSIDE_Val << TSENS_CTRLC_WINMODE_Pos)
#define TSENS_CTRLC_WINMODE_HYST_ABOVE (TSENS_CTRLC_WINMODE_HYST_ABOVE_Val << TSENS_CTRLC_WINMODE_Pos)
#define TSENS_CTRLC_WINMODE_HYST_BELOW (TSENS_CTRLC_WINMODE_HYST_BELOW_Val << TSENS_CTRLC_WINMODE_Pos)
#define TSENS_CTRLC_FREERUN_Pos 4 /**< \brief (TSENS_CTRLC) Free Running Measurement */
#define TSENS_CTRLC_FREERUN (_U_(0x1) << TSENS_CTRLC_FREERUN_Pos)
#define TSENS_CTRLC_MASK _U_(0x17) /**< \brief (TSENS_CTRLC) MASK Register */
/* -------- TSENS_EVCTRL : (TSENS Offset: 0x03) (R/W 8) Event Control Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input Enable */
uint8_t STARTINV:1; /*!< bit: 1 Start Conversion Event Invert Enable */
uint8_t WINEO:1; /*!< bit: 2 Window Monitor Event Out */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TSENS_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_EVCTRL_OFFSET 0x03 /**< \brief (TSENS_EVCTRL offset) Event Control Register */
#define TSENS_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (TSENS_EVCTRL reset_value) Event Control Register */
#define TSENS_EVCTRL_STARTEI_Pos 0 /**< \brief (TSENS_EVCTRL) Start Conversion Event Input Enable */
#define TSENS_EVCTRL_STARTEI (_U_(0x1) << TSENS_EVCTRL_STARTEI_Pos)
#define TSENS_EVCTRL_STARTINV_Pos 1 /**< \brief (TSENS_EVCTRL) Start Conversion Event Invert Enable */
#define TSENS_EVCTRL_STARTINV (_U_(0x1) << TSENS_EVCTRL_STARTINV_Pos)
#define TSENS_EVCTRL_WINEO_Pos 2 /**< \brief (TSENS_EVCTRL) Window Monitor Event Out */
#define TSENS_EVCTRL_WINEO (_U_(0x1) << TSENS_EVCTRL_WINEO_Pos)
#define TSENS_EVCTRL_MASK _U_(0x07) /**< \brief (TSENS_EVCTRL) MASK Register */
/* -------- TSENS_INTENCLR : (TSENS Offset: 0x04) (R/W 8) Interrupt Enable Clear Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t OVF:1; /*!< bit: 3 Overflow Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TSENS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_INTENCLR_OFFSET 0x04 /**< \brief (TSENS_INTENCLR offset) Interrupt Enable Clear Register */
#define TSENS_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TSENS_INTENCLR reset_value) Interrupt Enable Clear Register */
#define TSENS_INTENCLR_RESRDY_Pos 0 /**< \brief (TSENS_INTENCLR) Result Ready Interrupt Enable */
#define TSENS_INTENCLR_RESRDY (_U_(0x1) << TSENS_INTENCLR_RESRDY_Pos)
#define TSENS_INTENCLR_OVERRUN_Pos 1 /**< \brief (TSENS_INTENCLR) Overrun Interrupt Enable */
#define TSENS_INTENCLR_OVERRUN (_U_(0x1) << TSENS_INTENCLR_OVERRUN_Pos)
#define TSENS_INTENCLR_WINMON_Pos 2 /**< \brief (TSENS_INTENCLR) Window Monitor Interrupt Enable */
#define TSENS_INTENCLR_WINMON (_U_(0x1) << TSENS_INTENCLR_WINMON_Pos)
#define TSENS_INTENCLR_OVF_Pos 3 /**< \brief (TSENS_INTENCLR) Overflow Interrupt Enable */
#define TSENS_INTENCLR_OVF (_U_(0x1) << TSENS_INTENCLR_OVF_Pos)
#define TSENS_INTENCLR_MASK _U_(0x0F) /**< \brief (TSENS_INTENCLR) MASK Register */
/* -------- TSENS_INTENSET : (TSENS Offset: 0x05) (R/W 8) Interrupt Enable Set Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t OVF:1; /*!< bit: 3 Overflow Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TSENS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_INTENSET_OFFSET 0x05 /**< \brief (TSENS_INTENSET offset) Interrupt Enable Set Register */
#define TSENS_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TSENS_INTENSET reset_value) Interrupt Enable Set Register */
#define TSENS_INTENSET_RESRDY_Pos 0 /**< \brief (TSENS_INTENSET) Result Ready Interrupt Enable */
#define TSENS_INTENSET_RESRDY (_U_(0x1) << TSENS_INTENSET_RESRDY_Pos)
#define TSENS_INTENSET_OVERRUN_Pos 1 /**< \brief (TSENS_INTENSET) Overrun Interrupt Enable */
#define TSENS_INTENSET_OVERRUN (_U_(0x1) << TSENS_INTENSET_OVERRUN_Pos)
#define TSENS_INTENSET_WINMON_Pos 2 /**< \brief (TSENS_INTENSET) Window Monitor Interrupt Enable */
#define TSENS_INTENSET_WINMON (_U_(0x1) << TSENS_INTENSET_WINMON_Pos)
#define TSENS_INTENSET_OVF_Pos 3 /**< \brief (TSENS_INTENSET) Overflow Interrupt Enable */
#define TSENS_INTENSET_OVF (_U_(0x1) << TSENS_INTENSET_OVF_Pos)
#define TSENS_INTENSET_MASK _U_(0x0F) /**< \brief (TSENS_INTENSET) MASK Register */
/* -------- TSENS_INTFLAG : (TSENS Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
__I uint8_t OVF:1; /*!< bit: 3 Overflow */
__I uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TSENS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_INTFLAG_OFFSET 0x06 /**< \brief (TSENS_INTFLAG offset) Interrupt Flag Status and Clear Register */
#define TSENS_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TSENS_INTFLAG reset_value) Interrupt Flag Status and Clear Register */
#define TSENS_INTFLAG_RESRDY_Pos 0 /**< \brief (TSENS_INTFLAG) Result Ready */
#define TSENS_INTFLAG_RESRDY (_U_(0x1) << TSENS_INTFLAG_RESRDY_Pos)
#define TSENS_INTFLAG_OVERRUN_Pos 1 /**< \brief (TSENS_INTFLAG) Overrun */
#define TSENS_INTFLAG_OVERRUN (_U_(0x1) << TSENS_INTFLAG_OVERRUN_Pos)
#define TSENS_INTFLAG_WINMON_Pos 2 /**< \brief (TSENS_INTFLAG) Window Monitor */
#define TSENS_INTFLAG_WINMON (_U_(0x1) << TSENS_INTFLAG_WINMON_Pos)
#define TSENS_INTFLAG_OVF_Pos 3 /**< \brief (TSENS_INTFLAG) Overflow */
#define TSENS_INTFLAG_OVF (_U_(0x1) << TSENS_INTFLAG_OVF_Pos)
#define TSENS_INTFLAG_MASK _U_(0x0F) /**< \brief (TSENS_INTFLAG) MASK Register */
/* -------- TSENS_STATUS : (TSENS Offset: 0x07) (R/ 8) Status Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Result Overflow */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TSENS_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_STATUS_OFFSET 0x07 /**< \brief (TSENS_STATUS offset) Status Register */
#define TSENS_STATUS_RESETVALUE _U_(0x00) /**< \brief (TSENS_STATUS reset_value) Status Register */
#define TSENS_STATUS_OVF_Pos 0 /**< \brief (TSENS_STATUS) Result Overflow */
#define TSENS_STATUS_OVF (_U_(0x1) << TSENS_STATUS_OVF_Pos)
#define TSENS_STATUS_MASK _U_(0x01) /**< \brief (TSENS_STATUS) MASK Register */
/* -------- TSENS_SYNCBUSY : (TSENS Offset: 0x08) (R/ 32) Synchronization Busy Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWRST:1; /*!< bit: 0 Software Reset Busy */
uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TSENS_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_SYNCBUSY_OFFSET 0x08 /**< \brief (TSENS_SYNCBUSY offset) Synchronization Busy Register */
#define TSENS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_SYNCBUSY reset_value) Synchronization Busy Register */
#define TSENS_SYNCBUSY_SWRST_Pos 0 /**< \brief (TSENS_SYNCBUSY) Software Reset Busy */
#define TSENS_SYNCBUSY_SWRST (_U_(0x1) << TSENS_SYNCBUSY_SWRST_Pos)
#define TSENS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TSENS_SYNCBUSY) Enable Busy */
#define TSENS_SYNCBUSY_ENABLE (_U_(0x1) << TSENS_SYNCBUSY_ENABLE_Pos)
#define TSENS_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (TSENS_SYNCBUSY) MASK Register */
/* -------- TSENS_VALUE : (TSENS Offset: 0x0C) (R/ 32) Value Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TSENS_VALUE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_VALUE_OFFSET 0x0C /**< \brief (TSENS_VALUE offset) Value Register */
#define TSENS_VALUE_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_VALUE reset_value) Value Register */
#define TSENS_VALUE_VALUE_Pos 0 /**< \brief (TSENS_VALUE) Measurement Value */
#define TSENS_VALUE_VALUE_Msk (_U_(0xFFFFFF) << TSENS_VALUE_VALUE_Pos)
#define TSENS_VALUE_VALUE(value) (TSENS_VALUE_VALUE_Msk & ((value) << TSENS_VALUE_VALUE_Pos))
#define TSENS_VALUE_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_VALUE) MASK Register */
/* -------- TSENS_WINLT : (TSENS Offset: 0x10) (R/W 32) Window Monitor Lower Threshold Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WINLT:24; /*!< bit: 0..23 Window Lower Threshold */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TSENS_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_WINLT_OFFSET 0x10 /**< \brief (TSENS_WINLT offset) Window Monitor Lower Threshold Register */
#define TSENS_WINLT_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_WINLT reset_value) Window Monitor Lower Threshold Register */
#define TSENS_WINLT_WINLT_Pos 0 /**< \brief (TSENS_WINLT) Window Lower Threshold */
#define TSENS_WINLT_WINLT_Msk (_U_(0xFFFFFF) << TSENS_WINLT_WINLT_Pos)
#define TSENS_WINLT_WINLT(value) (TSENS_WINLT_WINLT_Msk & ((value) << TSENS_WINLT_WINLT_Pos))
#define TSENS_WINLT_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_WINLT) MASK Register */
/* -------- TSENS_WINUT : (TSENS Offset: 0x14) (R/W 32) Window Monitor Upper Threshold Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WINUT:24; /*!< bit: 0..23 Window Upper Threshold */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TSENS_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_WINUT_OFFSET 0x14 /**< \brief (TSENS_WINUT offset) Window Monitor Upper Threshold Register */
#define TSENS_WINUT_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_WINUT reset_value) Window Monitor Upper Threshold Register */
#define TSENS_WINUT_WINUT_Pos 0 /**< \brief (TSENS_WINUT) Window Upper Threshold */
#define TSENS_WINUT_WINUT_Msk (_U_(0xFFFFFF) << TSENS_WINUT_WINUT_Pos)
#define TSENS_WINUT_WINUT(value) (TSENS_WINUT_WINUT_Msk & ((value) << TSENS_WINUT_WINUT_Pos))
#define TSENS_WINUT_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_WINUT) MASK Register */
/* -------- TSENS_GAIN : (TSENS Offset: 0x18) (R/W 32) Gain Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t GAIN:24; /*!< bit: 0..23 Time Amplifier Gain */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TSENS_GAIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_GAIN_OFFSET 0x18 /**< \brief (TSENS_GAIN offset) Gain Register */
#define TSENS_GAIN_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_GAIN reset_value) Gain Register */
#define TSENS_GAIN_GAIN_Pos 0 /**< \brief (TSENS_GAIN) Time Amplifier Gain */
#define TSENS_GAIN_GAIN_Msk (_U_(0xFFFFFF) << TSENS_GAIN_GAIN_Pos)
#define TSENS_GAIN_GAIN(value) (TSENS_GAIN_GAIN_Msk & ((value) << TSENS_GAIN_GAIN_Pos))
#define TSENS_GAIN_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_GAIN) MASK Register */
/* -------- TSENS_OFFSET : (TSENS Offset: 0x1C) (R/W 32) Offset Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OFFSETC:24; /*!< bit: 0..23 Offset Correction */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TSENS_OFFSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_OFFSET_OFFSET 0x1C /**< \brief (TSENS_OFFSET offset) Offset Register */
#define TSENS_OFFSET_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_OFFSET reset_value) Offset Register */
#define TSENS_OFFSET_OFFSETC_Pos 0 /**< \brief (TSENS_OFFSET) Offset Correction */
#define TSENS_OFFSET_OFFSETC_Msk (_U_(0xFFFFFF) << TSENS_OFFSET_OFFSETC_Pos)
#define TSENS_OFFSET_OFFSETC(value) (TSENS_OFFSET_OFFSETC_Msk & ((value) << TSENS_OFFSET_OFFSETC_Pos))
#define TSENS_OFFSET_MASK _U_(0x00FFFFFF) /**< \brief (TSENS_OFFSET) MASK Register */
/* -------- TSENS_CAL : (TSENS Offset: 0x20) (R/W 32) Calibration Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FCAL:6; /*!< bit: 0.. 5 Frequency Calibration */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t TCAL:6; /*!< bit: 8..13 Temperature Calibration */
uint32_t :18; /*!< bit: 14..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TSENS_CAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_CAL_OFFSET 0x20 /**< \brief (TSENS_CAL offset) Calibration Register */
#define TSENS_CAL_RESETVALUE _U_(0x00000000) /**< \brief (TSENS_CAL reset_value) Calibration Register */
#define TSENS_CAL_FCAL_Pos 0 /**< \brief (TSENS_CAL) Frequency Calibration */
#define TSENS_CAL_FCAL_Msk (_U_(0x3F) << TSENS_CAL_FCAL_Pos)
#define TSENS_CAL_FCAL(value) (TSENS_CAL_FCAL_Msk & ((value) << TSENS_CAL_FCAL_Pos))
#define TSENS_CAL_TCAL_Pos 8 /**< \brief (TSENS_CAL) Temperature Calibration */
#define TSENS_CAL_TCAL_Msk (_U_(0x3F) << TSENS_CAL_TCAL_Pos)
#define TSENS_CAL_TCAL(value) (TSENS_CAL_TCAL_Msk & ((value) << TSENS_CAL_TCAL_Pos))
#define TSENS_CAL_MASK _U_(0x00003F3F) /**< \brief (TSENS_CAL) MASK Register */
/* -------- TSENS_DBGCTRL : (TSENS Offset: 0x24) (R/W 8) Debug Control Register -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TSENS_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define TSENS_DBGCTRL_OFFSET 0x24 /**< \brief (TSENS_DBGCTRL offset) Debug Control Register */
#define TSENS_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TSENS_DBGCTRL reset_value) Debug Control Register */
#define TSENS_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TSENS_DBGCTRL) Debug Run */
#define TSENS_DBGCTRL_DBGRUN (_U_(0x1) << TSENS_DBGCTRL_DBGRUN_Pos)
#define TSENS_DBGCTRL_MASK _U_(0x01) /**< \brief (TSENS_DBGCTRL) MASK Register */
/** \brief TSENS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO TSENS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */
__O TSENS_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */
__IO TSENS_CTRLC_Type CTRLC; /**< \brief Offset: 0x02 (R/W 8) Control C Register */
__IO TSENS_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x03 (R/W 8) Event Control Register */
__IO TSENS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear Register */
__IO TSENS_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set Register */
__IO TSENS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear Register */
__I TSENS_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status Register */
__I TSENS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy Register */
__I TSENS_VALUE_Type VALUE; /**< \brief Offset: 0x0C (R/ 32) Value Register */
__IO TSENS_WINLT_Type WINLT; /**< \brief Offset: 0x10 (R/W 32) Window Monitor Lower Threshold Register */
__IO TSENS_WINUT_Type WINUT; /**< \brief Offset: 0x14 (R/W 32) Window Monitor Upper Threshold Register */
__IO TSENS_GAIN_Type GAIN; /**< \brief Offset: 0x18 (R/W 32) Gain Register */
__IO TSENS_OFFSET_Type OFFSET; /**< \brief Offset: 0x1C (R/W 32) Offset Register */
__IO TSENS_CAL_Type CAL; /**< \brief Offset: 0x20 (R/W 32) Calibration Register */
__IO TSENS_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x24 (R/W 8) Debug Control Register */
} Tsens;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_TSENS_COMPONENT_ */

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/**
* \file
*
* \brief Component description for WDT
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_WDT_COMPONENT_
#define _SAMC21_WDT_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR WDT */
/* ========================================================================== */
/** \addtogroup SAMC21_WDT Watchdog Timer */
/*@{*/
#define WDT_U2251
#define REV_WDT 0x101
/* -------- WDT_CTRLA : (WDT Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CTRLA_OFFSET 0x0 /**< \brief (WDT_CTRLA offset) Control */
#define WDT_CTRLA_RESETVALUE _U_(0x00) /**< \brief (WDT_CTRLA reset_value) Control */
#define WDT_CTRLA_ENABLE_Pos 1 /**< \brief (WDT_CTRLA) Enable */
#define WDT_CTRLA_ENABLE (_U_(0x1) << WDT_CTRLA_ENABLE_Pos)
#define WDT_CTRLA_WEN_Pos 2 /**< \brief (WDT_CTRLA) Watchdog Timer Window Mode Enable */
#define WDT_CTRLA_WEN (_U_(0x1) << WDT_CTRLA_WEN_Pos)
#define WDT_CTRLA_ALWAYSON_Pos 7 /**< \brief (WDT_CTRLA) Always-On */
#define WDT_CTRLA_ALWAYSON (_U_(0x1) << WDT_CTRLA_ALWAYSON_Pos)
#define WDT_CTRLA_MASK _U_(0x86) /**< \brief (WDT_CTRLA) MASK Register */
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
#define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */
#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
#define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
#define WDT_CONFIG_PER_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
#define WDT_CONFIG_PER_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
#define WDT_CONFIG_PER_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
#define WDT_CONFIG_PER_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
#define WDT_CONFIG_PER_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
#define WDT_CONFIG_PER_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
#define WDT_CONFIG_PER_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
#define WDT_CONFIG_PER_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
#define WDT_CONFIG_PER_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
#define WDT_CONFIG_PER_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
#define WDT_CONFIG_PER_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
#define WDT_CONFIG_PER_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
#define WDT_CONFIG_PER_CYC8 (WDT_CONFIG_PER_CYC8_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC16 (WDT_CONFIG_PER_CYC16_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC32 (WDT_CONFIG_PER_CYC32_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC64 (WDT_CONFIG_PER_CYC64_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC128 (WDT_CONFIG_PER_CYC128_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC256 (WDT_CONFIG_PER_CYC256_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC512 (WDT_CONFIG_PER_CYC512_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC1024 (WDT_CONFIG_PER_CYC1024_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC2048 (WDT_CONFIG_PER_CYC2048_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC4096 (WDT_CONFIG_PER_CYC4096_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC8192 (WDT_CONFIG_PER_CYC8192_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_PER_CYC16384 (WDT_CONFIG_PER_CYC16384_Val << WDT_CONFIG_PER_Pos)
#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
#define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
#define WDT_CONFIG_WINDOW_CYC8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
#define WDT_CONFIG_WINDOW_CYC16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
#define WDT_CONFIG_WINDOW_CYC32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
#define WDT_CONFIG_WINDOW_CYC64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
#define WDT_CONFIG_WINDOW_CYC128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
#define WDT_CONFIG_WINDOW_CYC256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
#define WDT_CONFIG_WINDOW_CYC512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
#define WDT_CONFIG_WINDOW_CYC1024_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
#define WDT_CONFIG_WINDOW_CYC2048_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
#define WDT_CONFIG_WINDOW_CYC4096_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
#define WDT_CONFIG_WINDOW_CYC8192_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
#define WDT_CONFIG_WINDOW_CYC16384_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
#define WDT_CONFIG_WINDOW_CYC8 (WDT_CONFIG_WINDOW_CYC8_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC16 (WDT_CONFIG_WINDOW_CYC16_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC32 (WDT_CONFIG_WINDOW_CYC32_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC64 (WDT_CONFIG_WINDOW_CYC64_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC128 (WDT_CONFIG_WINDOW_CYC128_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC256 (WDT_CONFIG_WINDOW_CYC256_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC512 (WDT_CONFIG_WINDOW_CYC512_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC1024 (WDT_CONFIG_WINDOW_CYC1024_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC2048 (WDT_CONFIG_WINDOW_CYC2048_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC4096 (WDT_CONFIG_WINDOW_CYC4096_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC8192 (WDT_CONFIG_WINDOW_CYC8192_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_WINDOW_CYC16384 (WDT_CONFIG_WINDOW_CYC16384_Val << WDT_CONFIG_WINDOW_Pos)
#define WDT_CONFIG_MASK _U_(0xFF) /**< \brief (WDT_CONFIG) MASK Register */
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_EWCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
#define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
#define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
#define WDT_EWCTRL_EWOFFSET_CYC8_Val _U_(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC16_Val _U_(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC32_Val _U_(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC64_Val _U_(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC128_Val _U_(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC256_Val _U_(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC512_Val _U_(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC1024_Val _U_(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC2048_Val _U_(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC4096_Val _U_(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC8192_Val _U_(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC16384_Val _U_(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */
#define WDT_EWCTRL_EWOFFSET_CYC8 (WDT_EWCTRL_EWOFFSET_CYC8_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC16 (WDT_EWCTRL_EWOFFSET_CYC16_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC32 (WDT_EWCTRL_EWOFFSET_CYC32_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC64 (WDT_EWCTRL_EWOFFSET_CYC64_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC128 (WDT_EWCTRL_EWOFFSET_CYC128_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC256 (WDT_EWCTRL_EWOFFSET_CYC256_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC512 (WDT_EWCTRL_EWOFFSET_CYC512_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC1024 (WDT_EWCTRL_EWOFFSET_CYC1024_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC2048 (WDT_EWCTRL_EWOFFSET_CYC2048_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC4096 (WDT_EWCTRL_EWOFFSET_CYC4096_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC8192 (WDT_EWCTRL_EWOFFSET_CYC8192_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_EWOFFSET_CYC16384 (WDT_EWCTRL_EWOFFSET_CYC16384_Val << WDT_EWCTRL_EWOFFSET_Pos)
#define WDT_EWCTRL_MASK _U_(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
#define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
#define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos)
#define WDT_INTENCLR_MASK _U_(0x01) /**< \brief (WDT_INTENCLR) MASK Register */
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
#define WDT_INTENSET_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
#define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos)
#define WDT_INTENSET_MASK _U_(0x01) /**< \brief (WDT_INTENSET) MASK Register */
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t EW:1; /*!< bit: 0 Early Warning */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
#define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
#define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos)
#define WDT_INTFLAG_MASK _U_(0x01) /**< \brief (WDT_INTFLAG) MASK Register */
/* -------- WDT_SYNCBUSY : (WDT Offset: 0x8) (R/ 32) Synchronization Busy -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */
uint32_t WEN:1; /*!< bit: 2 Window Enable Busy */
uint32_t ALWAYSON:1; /*!< bit: 3 Always-On Busy */
uint32_t CLEAR:1; /*!< bit: 4 Clear Busy */
uint32_t :27; /*!< bit: 5..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} WDT_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_SYNCBUSY_OFFSET 0x8 /**< \brief (WDT_SYNCBUSY offset) Synchronization Busy */
#define WDT_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (WDT_SYNCBUSY reset_value) Synchronization Busy */
#define WDT_SYNCBUSY_ENABLE_Pos 1 /**< \brief (WDT_SYNCBUSY) Enable Busy */
#define WDT_SYNCBUSY_ENABLE (_U_(0x1) << WDT_SYNCBUSY_ENABLE_Pos)
#define WDT_SYNCBUSY_WEN_Pos 2 /**< \brief (WDT_SYNCBUSY) Window Enable Busy */
#define WDT_SYNCBUSY_WEN (_U_(0x1) << WDT_SYNCBUSY_WEN_Pos)
#define WDT_SYNCBUSY_ALWAYSON_Pos 3 /**< \brief (WDT_SYNCBUSY) Always-On Busy */
#define WDT_SYNCBUSY_ALWAYSON (_U_(0x1) << WDT_SYNCBUSY_ALWAYSON_Pos)
#define WDT_SYNCBUSY_CLEAR_Pos 4 /**< \brief (WDT_SYNCBUSY) Clear Busy */
#define WDT_SYNCBUSY_CLEAR (_U_(0x1) << WDT_SYNCBUSY_CLEAR_Pos)
#define WDT_SYNCBUSY_MASK _U_(0x0000001E) /**< \brief (WDT_SYNCBUSY) MASK Register */
/* -------- WDT_CLEAR : (WDT Offset: 0xC) ( /W 8) Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CLEAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define WDT_CLEAR_OFFSET 0xC /**< \brief (WDT_CLEAR offset) Clear */
#define WDT_CLEAR_RESETVALUE _U_(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */
#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
#define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
#define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< \brief (WDT_CLEAR) Clear Key */
#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
#define WDT_CLEAR_MASK _U_(0xFF) /**< \brief (WDT_CLEAR) MASK Register */
/** \brief WDT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO WDT_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control */
__IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
__IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
RoReg8 Reserved1[0x1];
__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved2[0x1];
__I WDT_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x8 (R/ 32) Synchronization Busy */
__O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0xC ( /W 8) Clear */
} Wdt;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
#endif /* _SAMC21_WDT_COMPONENT_ */

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/**
* \file
*
* \brief Instance description for AC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_AC_INSTANCE_
#define _SAMC21_AC_INSTANCE_
/* ========== Register definition for AC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AC_CTRLA (0x42005000) /**< \brief (AC) Control A */
#define REG_AC_CTRLB (0x42005001) /**< \brief (AC) Control B */
#define REG_AC_EVCTRL (0x42005002) /**< \brief (AC) Event Control */
#define REG_AC_INTENCLR (0x42005004) /**< \brief (AC) Interrupt Enable Clear */
#define REG_AC_INTENSET (0x42005005) /**< \brief (AC) Interrupt Enable Set */
#define REG_AC_INTFLAG (0x42005006) /**< \brief (AC) Interrupt Flag Status and Clear */
#define REG_AC_STATUSA (0x42005007) /**< \brief (AC) Status A */
#define REG_AC_STATUSB (0x42005008) /**< \brief (AC) Status B */
#define REG_AC_DBGCTRL (0x42005009) /**< \brief (AC) Debug Control */
#define REG_AC_WINCTRL (0x4200500A) /**< \brief (AC) Window Control */
#define REG_AC_SCALER0 (0x4200500C) /**< \brief (AC) Scaler 0 */
#define REG_AC_SCALER1 (0x4200500D) /**< \brief (AC) Scaler 1 */
#define REG_AC_SCALER2 (0x4200500E) /**< \brief (AC) Scaler 2 */
#define REG_AC_SCALER3 (0x4200500F) /**< \brief (AC) Scaler 3 */
#define REG_AC_COMPCTRL0 (0x42005010) /**< \brief (AC) Comparator Control 0 */
#define REG_AC_COMPCTRL1 (0x42005014) /**< \brief (AC) Comparator Control 1 */
#define REG_AC_COMPCTRL2 (0x42005018) /**< \brief (AC) Comparator Control 2 */
#define REG_AC_COMPCTRL3 (0x4200501C) /**< \brief (AC) Comparator Control 3 */
#define REG_AC_SYNCBUSY (0x42005020) /**< \brief (AC) Synchronization Busy */
#else
#define REG_AC_CTRLA (*(RwReg8 *)0x42005000UL) /**< \brief (AC) Control A */
#define REG_AC_CTRLB (*(WoReg8 *)0x42005001UL) /**< \brief (AC) Control B */
#define REG_AC_EVCTRL (*(RwReg16*)0x42005002UL) /**< \brief (AC) Event Control */
#define REG_AC_INTENCLR (*(RwReg8 *)0x42005004UL) /**< \brief (AC) Interrupt Enable Clear */
#define REG_AC_INTENSET (*(RwReg8 *)0x42005005UL) /**< \brief (AC) Interrupt Enable Set */
#define REG_AC_INTFLAG (*(RwReg8 *)0x42005006UL) /**< \brief (AC) Interrupt Flag Status and Clear */
#define REG_AC_STATUSA (*(RoReg8 *)0x42005007UL) /**< \brief (AC) Status A */
#define REG_AC_STATUSB (*(RoReg8 *)0x42005008UL) /**< \brief (AC) Status B */
#define REG_AC_DBGCTRL (*(RwReg8 *)0x42005009UL) /**< \brief (AC) Debug Control */
#define REG_AC_WINCTRL (*(RwReg8 *)0x4200500AUL) /**< \brief (AC) Window Control */
#define REG_AC_SCALER0 (*(RwReg8 *)0x4200500CUL) /**< \brief (AC) Scaler 0 */
#define REG_AC_SCALER1 (*(RwReg8 *)0x4200500DUL) /**< \brief (AC) Scaler 1 */
#define REG_AC_SCALER2 (*(RwReg8 *)0x4200500EUL) /**< \brief (AC) Scaler 2 */
#define REG_AC_SCALER3 (*(RwReg8 *)0x4200500FUL) /**< \brief (AC) Scaler 3 */
#define REG_AC_COMPCTRL0 (*(RwReg *)0x42005010UL) /**< \brief (AC) Comparator Control 0 */
#define REG_AC_COMPCTRL1 (*(RwReg *)0x42005014UL) /**< \brief (AC) Comparator Control 1 */
#define REG_AC_COMPCTRL2 (*(RwReg *)0x42005018UL) /**< \brief (AC) Comparator Control 2 */
#define REG_AC_COMPCTRL3 (*(RwReg *)0x4200501CUL) /**< \brief (AC) Comparator Control 3 */
#define REG_AC_SYNCBUSY (*(RoReg *)0x42005020UL) /**< \brief (AC) Synchronization Busy */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for AC peripheral ========== */
#define AC_COMPCTRL_MUXNEG_OPAMP 7 // OPAMP selection for MUXNEG
#define AC_GCLK_ID 40 // Index of Generic Clock
#define AC_NUM_CMP 4 // Number of comparators
#define AC_SPEED_LEVELS 2 // Number of speed values
#endif /* _SAMC21_AC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for ADC0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_ADC0_INSTANCE_
#define _SAMC21_ADC0_INSTANCE_
/* ========== Register definition for ADC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ADC0_CTRLA (0x42004400) /**< \brief (ADC0) Control A */
#define REG_ADC0_CTRLB (0x42004401) /**< \brief (ADC0) Control B */
#define REG_ADC0_REFCTRL (0x42004402) /**< \brief (ADC0) Reference Control */
#define REG_ADC0_EVCTRL (0x42004403) /**< \brief (ADC0) Event Control */
#define REG_ADC0_INTENCLR (0x42004404) /**< \brief (ADC0) Interrupt Enable Clear */
#define REG_ADC0_INTENSET (0x42004405) /**< \brief (ADC0) Interrupt Enable Set */
#define REG_ADC0_INTFLAG (0x42004406) /**< \brief (ADC0) Interrupt Flag Status and Clear */
#define REG_ADC0_SEQSTATUS (0x42004407) /**< \brief (ADC0) Sequence Status */
#define REG_ADC0_INPUTCTRL (0x42004408) /**< \brief (ADC0) Input Control */
#define REG_ADC0_CTRLC (0x4200440A) /**< \brief (ADC0) Control C */
#define REG_ADC0_AVGCTRL (0x4200440C) /**< \brief (ADC0) Average Control */
#define REG_ADC0_SAMPCTRL (0x4200440D) /**< \brief (ADC0) Sample Time Control */
#define REG_ADC0_WINLT (0x4200440E) /**< \brief (ADC0) Window Monitor Lower Threshold */
#define REG_ADC0_WINUT (0x42004410) /**< \brief (ADC0) Window Monitor Upper Threshold */
#define REG_ADC0_GAINCORR (0x42004412) /**< \brief (ADC0) Gain Correction */
#define REG_ADC0_OFFSETCORR (0x42004414) /**< \brief (ADC0) Offset Correction */
#define REG_ADC0_SWTRIG (0x42004418) /**< \brief (ADC0) Software Trigger */
#define REG_ADC0_DBGCTRL (0x4200441C) /**< \brief (ADC0) Debug Control */
#define REG_ADC0_SYNCBUSY (0x42004420) /**< \brief (ADC0) Synchronization Busy */
#define REG_ADC0_RESULT (0x42004424) /**< \brief (ADC0) Result */
#define REG_ADC0_SEQCTRL (0x42004428) /**< \brief (ADC0) Sequence Control */
#define REG_ADC0_CALIB (0x4200442C) /**< \brief (ADC0) Calibration */
#else
#define REG_ADC0_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (ADC0) Control A */
#define REG_ADC0_CTRLB (*(RwReg8 *)0x42004401UL) /**< \brief (ADC0) Control B */
#define REG_ADC0_REFCTRL (*(RwReg8 *)0x42004402UL) /**< \brief (ADC0) Reference Control */
#define REG_ADC0_EVCTRL (*(RwReg8 *)0x42004403UL) /**< \brief (ADC0) Event Control */
#define REG_ADC0_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (ADC0) Interrupt Enable Clear */
#define REG_ADC0_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (ADC0) Interrupt Enable Set */
#define REG_ADC0_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (ADC0) Interrupt Flag Status and Clear */
#define REG_ADC0_SEQSTATUS (*(RoReg8 *)0x42004407UL) /**< \brief (ADC0) Sequence Status */
#define REG_ADC0_INPUTCTRL (*(RwReg16*)0x42004408UL) /**< \brief (ADC0) Input Control */
#define REG_ADC0_CTRLC (*(RwReg16*)0x4200440AUL) /**< \brief (ADC0) Control C */
#define REG_ADC0_AVGCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (ADC0) Average Control */
#define REG_ADC0_SAMPCTRL (*(RwReg8 *)0x4200440DUL) /**< \brief (ADC0) Sample Time Control */
#define REG_ADC0_WINLT (*(RwReg16*)0x4200440EUL) /**< \brief (ADC0) Window Monitor Lower Threshold */
#define REG_ADC0_WINUT (*(RwReg16*)0x42004410UL) /**< \brief (ADC0) Window Monitor Upper Threshold */
#define REG_ADC0_GAINCORR (*(RwReg16*)0x42004412UL) /**< \brief (ADC0) Gain Correction */
#define REG_ADC0_OFFSETCORR (*(RwReg16*)0x42004414UL) /**< \brief (ADC0) Offset Correction */
#define REG_ADC0_SWTRIG (*(RwReg8 *)0x42004418UL) /**< \brief (ADC0) Software Trigger */
#define REG_ADC0_DBGCTRL (*(RwReg8 *)0x4200441CUL) /**< \brief (ADC0) Debug Control */
#define REG_ADC0_SYNCBUSY (*(RoReg16*)0x42004420UL) /**< \brief (ADC0) Synchronization Busy */
#define REG_ADC0_RESULT (*(RoReg16*)0x42004424UL) /**< \brief (ADC0) Result */
#define REG_ADC0_SEQCTRL (*(RwReg *)0x42004428UL) /**< \brief (ADC0) Sequence Control */
#define REG_ADC0_CALIB (*(RwReg16*)0x4200442CUL) /**< \brief (ADC0) Calibration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for ADC0 peripheral ========== */
#define ADC0_DMAC_ID_RESRDY 42 // index of DMA RESRDY trigger
#define ADC0_EXTCHANNEL_MSB 11 // Number of external channels
#define ADC0_GCLK_ID 33 // index of Generic Clock
#define ADC0_INT_CH30 0 // Select OPAMP or CTAT on Channel 30
#define ADC0_MASTER_SLAVE_MODE 1 // ADC Master/Slave Mode
#endif /* _SAMC21_ADC0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for ADC1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_ADC1_INSTANCE_
#define _SAMC21_ADC1_INSTANCE_
/* ========== Register definition for ADC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ADC1_CTRLA (0x42004800) /**< \brief (ADC1) Control A */
#define REG_ADC1_CTRLB (0x42004801) /**< \brief (ADC1) Control B */
#define REG_ADC1_REFCTRL (0x42004802) /**< \brief (ADC1) Reference Control */
#define REG_ADC1_EVCTRL (0x42004803) /**< \brief (ADC1) Event Control */
#define REG_ADC1_INTENCLR (0x42004804) /**< \brief (ADC1) Interrupt Enable Clear */
#define REG_ADC1_INTENSET (0x42004805) /**< \brief (ADC1) Interrupt Enable Set */
#define REG_ADC1_INTFLAG (0x42004806) /**< \brief (ADC1) Interrupt Flag Status and Clear */
#define REG_ADC1_SEQSTATUS (0x42004807) /**< \brief (ADC1) Sequence Status */
#define REG_ADC1_INPUTCTRL (0x42004808) /**< \brief (ADC1) Input Control */
#define REG_ADC1_CTRLC (0x4200480A) /**< \brief (ADC1) Control C */
#define REG_ADC1_AVGCTRL (0x4200480C) /**< \brief (ADC1) Average Control */
#define REG_ADC1_SAMPCTRL (0x4200480D) /**< \brief (ADC1) Sample Time Control */
#define REG_ADC1_WINLT (0x4200480E) /**< \brief (ADC1) Window Monitor Lower Threshold */
#define REG_ADC1_WINUT (0x42004810) /**< \brief (ADC1) Window Monitor Upper Threshold */
#define REG_ADC1_GAINCORR (0x42004812) /**< \brief (ADC1) Gain Correction */
#define REG_ADC1_OFFSETCORR (0x42004814) /**< \brief (ADC1) Offset Correction */
#define REG_ADC1_SWTRIG (0x42004818) /**< \brief (ADC1) Software Trigger */
#define REG_ADC1_DBGCTRL (0x4200481C) /**< \brief (ADC1) Debug Control */
#define REG_ADC1_SYNCBUSY (0x42004820) /**< \brief (ADC1) Synchronization Busy */
#define REG_ADC1_RESULT (0x42004824) /**< \brief (ADC1) Result */
#define REG_ADC1_SEQCTRL (0x42004828) /**< \brief (ADC1) Sequence Control */
#define REG_ADC1_CALIB (0x4200482C) /**< \brief (ADC1) Calibration */
#else
#define REG_ADC1_CTRLA (*(RwReg8 *)0x42004800UL) /**< \brief (ADC1) Control A */
#define REG_ADC1_CTRLB (*(RwReg8 *)0x42004801UL) /**< \brief (ADC1) Control B */
#define REG_ADC1_REFCTRL (*(RwReg8 *)0x42004802UL) /**< \brief (ADC1) Reference Control */
#define REG_ADC1_EVCTRL (*(RwReg8 *)0x42004803UL) /**< \brief (ADC1) Event Control */
#define REG_ADC1_INTENCLR (*(RwReg8 *)0x42004804UL) /**< \brief (ADC1) Interrupt Enable Clear */
#define REG_ADC1_INTENSET (*(RwReg8 *)0x42004805UL) /**< \brief (ADC1) Interrupt Enable Set */
#define REG_ADC1_INTFLAG (*(RwReg8 *)0x42004806UL) /**< \brief (ADC1) Interrupt Flag Status and Clear */
#define REG_ADC1_SEQSTATUS (*(RoReg8 *)0x42004807UL) /**< \brief (ADC1) Sequence Status */
#define REG_ADC1_INPUTCTRL (*(RwReg16*)0x42004808UL) /**< \brief (ADC1) Input Control */
#define REG_ADC1_CTRLC (*(RwReg16*)0x4200480AUL) /**< \brief (ADC1) Control C */
#define REG_ADC1_AVGCTRL (*(RwReg8 *)0x4200480CUL) /**< \brief (ADC1) Average Control */
#define REG_ADC1_SAMPCTRL (*(RwReg8 *)0x4200480DUL) /**< \brief (ADC1) Sample Time Control */
#define REG_ADC1_WINLT (*(RwReg16*)0x4200480EUL) /**< \brief (ADC1) Window Monitor Lower Threshold */
#define REG_ADC1_WINUT (*(RwReg16*)0x42004810UL) /**< \brief (ADC1) Window Monitor Upper Threshold */
#define REG_ADC1_GAINCORR (*(RwReg16*)0x42004812UL) /**< \brief (ADC1) Gain Correction */
#define REG_ADC1_OFFSETCORR (*(RwReg16*)0x42004814UL) /**< \brief (ADC1) Offset Correction */
#define REG_ADC1_SWTRIG (*(RwReg8 *)0x42004818UL) /**< \brief (ADC1) Software Trigger */
#define REG_ADC1_DBGCTRL (*(RwReg8 *)0x4200481CUL) /**< \brief (ADC1) Debug Control */
#define REG_ADC1_SYNCBUSY (*(RoReg16*)0x42004820UL) /**< \brief (ADC1) Synchronization Busy */
#define REG_ADC1_RESULT (*(RoReg16*)0x42004824UL) /**< \brief (ADC1) Result */
#define REG_ADC1_SEQCTRL (*(RwReg *)0x42004828UL) /**< \brief (ADC1) Sequence Control */
#define REG_ADC1_CALIB (*(RwReg16*)0x4200482CUL) /**< \brief (ADC1) Calibration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for ADC1 peripheral ========== */
#define ADC1_DMAC_ID_RESRDY 43 // index of DMA RESRDY trigger
#define ADC1_EXTCHANNEL_MSB 11 // Number of external channels
#define ADC1_GCLK_ID 34 // index of Generic Clock
#define ADC1_INT_CH30 0 // Select OPAMP or CTAT on Channel 30
#define ADC1_MASTER_SLAVE_MODE 2 // ADC Master/Slave Mode
#endif /* _SAMC21_ADC1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for CAN0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_CAN0_INSTANCE_
#define _SAMC21_CAN0_INSTANCE_
/* ========== Register definition for CAN0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CAN0_CREL (0x42001C00) /**< \brief (CAN0) Core Release */
#define REG_CAN0_ENDN (0x42001C04) /**< \brief (CAN0) Endian */
#define REG_CAN0_MRCFG (0x42001C08) /**< \brief (CAN0) Message RAM Configuration */
#define REG_CAN0_DBTP (0x42001C0C) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
#define REG_CAN0_TEST (0x42001C10) /**< \brief (CAN0) Test */
#define REG_CAN0_RWD (0x42001C14) /**< \brief (CAN0) RAM Watchdog */
#define REG_CAN0_CCCR (0x42001C18) /**< \brief (CAN0) CC Control */
#define REG_CAN0_NBTP (0x42001C1C) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
#define REG_CAN0_TSCC (0x42001C20) /**< \brief (CAN0) Timestamp Counter Configuration */
#define REG_CAN0_TSCV (0x42001C24) /**< \brief (CAN0) Timestamp Counter Value */
#define REG_CAN0_TOCC (0x42001C28) /**< \brief (CAN0) Timeout Counter Configuration */
#define REG_CAN0_TOCV (0x42001C2C) /**< \brief (CAN0) Timeout Counter Value */
#define REG_CAN0_ECR (0x42001C40) /**< \brief (CAN0) Error Counter */
#define REG_CAN0_PSR (0x42001C44) /**< \brief (CAN0) Protocol Status */
#define REG_CAN0_TDCR (0x42001C48) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_IR (0x42001C50) /**< \brief (CAN0) Interrupt */
#define REG_CAN0_IE (0x42001C54) /**< \brief (CAN0) Interrupt Enable */
#define REG_CAN0_ILS (0x42001C58) /**< \brief (CAN0) Interrupt Line Select */
#define REG_CAN0_ILE (0x42001C5C) /**< \brief (CAN0) Interrupt Line Enable */
#define REG_CAN0_GFC (0x42001C80) /**< \brief (CAN0) Global Filter Configuration */
#define REG_CAN0_SIDFC (0x42001C84) /**< \brief (CAN0) Standard ID Filter Configuration */
#define REG_CAN0_XIDFC (0x42001C88) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_XIDAM (0x42001C90) /**< \brief (CAN0) Extended ID AND Mask */
#define REG_CAN0_HPMS (0x42001C94) /**< \brief (CAN0) High Priority Message Status */
#define REG_CAN0_NDAT1 (0x42001C98) /**< \brief (CAN0) New Data 1 */
#define REG_CAN0_NDAT2 (0x42001C9C) /**< \brief (CAN0) New Data 2 */
#define REG_CAN0_RXF0C (0x42001CA0) /**< \brief (CAN0) Rx FIFO 0 Configuration */
#define REG_CAN0_RXF0S (0x42001CA4) /**< \brief (CAN0) Rx FIFO 0 Status */
#define REG_CAN0_RXF0A (0x42001CA8) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
#define REG_CAN0_RXBC (0x42001CAC) /**< \brief (CAN0) Rx Buffer Configuration */
#define REG_CAN0_RXF1C (0x42001CB0) /**< \brief (CAN0) Rx FIFO 1 Configuration */
#define REG_CAN0_RXF1S (0x42001CB4) /**< \brief (CAN0) Rx FIFO 1 Status */
#define REG_CAN0_RXF1A (0x42001CB8) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
#define REG_CAN0_RXESC (0x42001CBC) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN0_TXBC (0x42001CC0) /**< \brief (CAN0) Tx Buffer Configuration */
#define REG_CAN0_TXFQS (0x42001CC4) /**< \brief (CAN0) Tx FIFO / Queue Status */
#define REG_CAN0_TXESC (0x42001CC8) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
#define REG_CAN0_TXBRP (0x42001CCC) /**< \brief (CAN0) Tx Buffer Request Pending */
#define REG_CAN0_TXBAR (0x42001CD0) /**< \brief (CAN0) Tx Buffer Add Request */
#define REG_CAN0_TXBCR (0x42001CD4) /**< \brief (CAN0) Tx Buffer Cancellation Request */
#define REG_CAN0_TXBTO (0x42001CD8) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
#define REG_CAN0_TXBCF (0x42001CDC) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
#define REG_CAN0_TXBTIE (0x42001CE0) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN0_TXBCIE (0x42001CE4) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN0_TXEFC (0x42001CF0) /**< \brief (CAN0) Tx Event FIFO Configuration */
#define REG_CAN0_TXEFS (0x42001CF4) /**< \brief (CAN0) Tx Event FIFO Status */
#define REG_CAN0_TXEFA (0x42001CF8) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
#else
#define REG_CAN0_CREL (*(RoReg *)0x42001C00UL) /**< \brief (CAN0) Core Release */
#define REG_CAN0_ENDN (*(RoReg *)0x42001C04UL) /**< \brief (CAN0) Endian */
#define REG_CAN0_MRCFG (*(RwReg *)0x42001C08UL) /**< \brief (CAN0) Message RAM Configuration */
#define REG_CAN0_DBTP (*(RwReg *)0x42001C0CUL) /**< \brief (CAN0) Fast Bit Timing and Prescaler */
#define REG_CAN0_TEST (*(RwReg *)0x42001C10UL) /**< \brief (CAN0) Test */
#define REG_CAN0_RWD (*(RwReg *)0x42001C14UL) /**< \brief (CAN0) RAM Watchdog */
#define REG_CAN0_CCCR (*(RwReg *)0x42001C18UL) /**< \brief (CAN0) CC Control */
#define REG_CAN0_NBTP (*(RwReg *)0x42001C1CUL) /**< \brief (CAN0) Nominal Bit Timing and Prescaler */
#define REG_CAN0_TSCC (*(RwReg *)0x42001C20UL) /**< \brief (CAN0) Timestamp Counter Configuration */
#define REG_CAN0_TSCV (*(RoReg *)0x42001C24UL) /**< \brief (CAN0) Timestamp Counter Value */
#define REG_CAN0_TOCC (*(RwReg *)0x42001C28UL) /**< \brief (CAN0) Timeout Counter Configuration */
#define REG_CAN0_TOCV (*(RwReg *)0x42001C2CUL) /**< \brief (CAN0) Timeout Counter Value */
#define REG_CAN0_ECR (*(RoReg *)0x42001C40UL) /**< \brief (CAN0) Error Counter */
#define REG_CAN0_PSR (*(RoReg *)0x42001C44UL) /**< \brief (CAN0) Protocol Status */
#define REG_CAN0_TDCR (*(RwReg *)0x42001C48UL) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_IR (*(RwReg *)0x42001C50UL) /**< \brief (CAN0) Interrupt */
#define REG_CAN0_IE (*(RwReg *)0x42001C54UL) /**< \brief (CAN0) Interrupt Enable */
#define REG_CAN0_ILS (*(RwReg *)0x42001C58UL) /**< \brief (CAN0) Interrupt Line Select */
#define REG_CAN0_ILE (*(RwReg *)0x42001C5CUL) /**< \brief (CAN0) Interrupt Line Enable */
#define REG_CAN0_GFC (*(RwReg *)0x42001C80UL) /**< \brief (CAN0) Global Filter Configuration */
#define REG_CAN0_SIDFC (*(RwReg *)0x42001C84UL) /**< \brief (CAN0) Standard ID Filter Configuration */
#define REG_CAN0_XIDFC (*(RwReg *)0x42001C88UL) /**< \brief (CAN0) Extended ID Filter Configuration */
#define REG_CAN0_XIDAM (*(RwReg *)0x42001C90UL) /**< \brief (CAN0) Extended ID AND Mask */
#define REG_CAN0_HPMS (*(RoReg *)0x42001C94UL) /**< \brief (CAN0) High Priority Message Status */
#define REG_CAN0_NDAT1 (*(RwReg *)0x42001C98UL) /**< \brief (CAN0) New Data 1 */
#define REG_CAN0_NDAT2 (*(RwReg *)0x42001C9CUL) /**< \brief (CAN0) New Data 2 */
#define REG_CAN0_RXF0C (*(RwReg *)0x42001CA0UL) /**< \brief (CAN0) Rx FIFO 0 Configuration */
#define REG_CAN0_RXF0S (*(RoReg *)0x42001CA4UL) /**< \brief (CAN0) Rx FIFO 0 Status */
#define REG_CAN0_RXF0A (*(RwReg *)0x42001CA8UL) /**< \brief (CAN0) Rx FIFO 0 Acknowledge */
#define REG_CAN0_RXBC (*(RwReg *)0x42001CACUL) /**< \brief (CAN0) Rx Buffer Configuration */
#define REG_CAN0_RXF1C (*(RwReg *)0x42001CB0UL) /**< \brief (CAN0) Rx FIFO 1 Configuration */
#define REG_CAN0_RXF1S (*(RoReg *)0x42001CB4UL) /**< \brief (CAN0) Rx FIFO 1 Status */
#define REG_CAN0_RXF1A (*(RwReg *)0x42001CB8UL) /**< \brief (CAN0) Rx FIFO 1 Acknowledge */
#define REG_CAN0_RXESC (*(RwReg *)0x42001CBCUL) /**< \brief (CAN0) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN0_TXBC (*(RwReg *)0x42001CC0UL) /**< \brief (CAN0) Tx Buffer Configuration */
#define REG_CAN0_TXFQS (*(RoReg *)0x42001CC4UL) /**< \brief (CAN0) Tx FIFO / Queue Status */
#define REG_CAN0_TXESC (*(RwReg *)0x42001CC8UL) /**< \brief (CAN0) Tx Buffer Element Size Configuration */
#define REG_CAN0_TXBRP (*(RoReg *)0x42001CCCUL) /**< \brief (CAN0) Tx Buffer Request Pending */
#define REG_CAN0_TXBAR (*(RwReg *)0x42001CD0UL) /**< \brief (CAN0) Tx Buffer Add Request */
#define REG_CAN0_TXBCR (*(RwReg *)0x42001CD4UL) /**< \brief (CAN0) Tx Buffer Cancellation Request */
#define REG_CAN0_TXBTO (*(RoReg *)0x42001CD8UL) /**< \brief (CAN0) Tx Buffer Transmission Occurred */
#define REG_CAN0_TXBCF (*(RoReg *)0x42001CDCUL) /**< \brief (CAN0) Tx Buffer Cancellation Finished */
#define REG_CAN0_TXBTIE (*(RwReg *)0x42001CE0UL) /**< \brief (CAN0) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN0_TXBCIE (*(RwReg *)0x42001CE4UL) /**< \brief (CAN0) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN0_TXEFC (*(RwReg *)0x42001CF0UL) /**< \brief (CAN0) Tx Event FIFO Configuration */
#define REG_CAN0_TXEFS (*(RoReg *)0x42001CF4UL) /**< \brief (CAN0) Tx Event FIFO Status */
#define REG_CAN0_TXEFA (*(RwReg *)0x42001CF8UL) /**< \brief (CAN0) Tx Event FIFO Acknowledge */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for CAN0 peripheral ========== */
#define CAN0_CLK_AHB_ID 8 // Index of AHB clock
#define CAN0_DMAC_ID_DEBUG 14 // DMA CAN Debug Req
#define CAN0_GCLK_ID 26 // Index of Generic Clock
#define CAN0_MSG_RAM_ADDR 0x200000000
#define CAN0_QOS_RESET_VAL 2 // QOS reset value
#endif /* _SAMC21_CAN0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for CAN1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_CAN1_INSTANCE_
#define _SAMC21_CAN1_INSTANCE_
/* ========== Register definition for CAN1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CAN1_CREL (0x42002000) /**< \brief (CAN1) Core Release */
#define REG_CAN1_ENDN (0x42002004) /**< \brief (CAN1) Endian */
#define REG_CAN1_MRCFG (0x42002008) /**< \brief (CAN1) Message RAM Configuration */
#define REG_CAN1_DBTP (0x4200200C) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
#define REG_CAN1_TEST (0x42002010) /**< \brief (CAN1) Test */
#define REG_CAN1_RWD (0x42002014) /**< \brief (CAN1) RAM Watchdog */
#define REG_CAN1_CCCR (0x42002018) /**< \brief (CAN1) CC Control */
#define REG_CAN1_NBTP (0x4200201C) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
#define REG_CAN1_TSCC (0x42002020) /**< \brief (CAN1) Timestamp Counter Configuration */
#define REG_CAN1_TSCV (0x42002024) /**< \brief (CAN1) Timestamp Counter Value */
#define REG_CAN1_TOCC (0x42002028) /**< \brief (CAN1) Timeout Counter Configuration */
#define REG_CAN1_TOCV (0x4200202C) /**< \brief (CAN1) Timeout Counter Value */
#define REG_CAN1_ECR (0x42002040) /**< \brief (CAN1) Error Counter */
#define REG_CAN1_PSR (0x42002044) /**< \brief (CAN1) Protocol Status */
#define REG_CAN1_TDCR (0x42002048) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_IR (0x42002050) /**< \brief (CAN1) Interrupt */
#define REG_CAN1_IE (0x42002054) /**< \brief (CAN1) Interrupt Enable */
#define REG_CAN1_ILS (0x42002058) /**< \brief (CAN1) Interrupt Line Select */
#define REG_CAN1_ILE (0x4200205C) /**< \brief (CAN1) Interrupt Line Enable */
#define REG_CAN1_GFC (0x42002080) /**< \brief (CAN1) Global Filter Configuration */
#define REG_CAN1_SIDFC (0x42002084) /**< \brief (CAN1) Standard ID Filter Configuration */
#define REG_CAN1_XIDFC (0x42002088) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_XIDAM (0x42002090) /**< \brief (CAN1) Extended ID AND Mask */
#define REG_CAN1_HPMS (0x42002094) /**< \brief (CAN1) High Priority Message Status */
#define REG_CAN1_NDAT1 (0x42002098) /**< \brief (CAN1) New Data 1 */
#define REG_CAN1_NDAT2 (0x4200209C) /**< \brief (CAN1) New Data 2 */
#define REG_CAN1_RXF0C (0x420020A0) /**< \brief (CAN1) Rx FIFO 0 Configuration */
#define REG_CAN1_RXF0S (0x420020A4) /**< \brief (CAN1) Rx FIFO 0 Status */
#define REG_CAN1_RXF0A (0x420020A8) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
#define REG_CAN1_RXBC (0x420020AC) /**< \brief (CAN1) Rx Buffer Configuration */
#define REG_CAN1_RXF1C (0x420020B0) /**< \brief (CAN1) Rx FIFO 1 Configuration */
#define REG_CAN1_RXF1S (0x420020B4) /**< \brief (CAN1) Rx FIFO 1 Status */
#define REG_CAN1_RXF1A (0x420020B8) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
#define REG_CAN1_RXESC (0x420020BC) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN1_TXBC (0x420020C0) /**< \brief (CAN1) Tx Buffer Configuration */
#define REG_CAN1_TXFQS (0x420020C4) /**< \brief (CAN1) Tx FIFO / Queue Status */
#define REG_CAN1_TXESC (0x420020C8) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
#define REG_CAN1_TXBRP (0x420020CC) /**< \brief (CAN1) Tx Buffer Request Pending */
#define REG_CAN1_TXBAR (0x420020D0) /**< \brief (CAN1) Tx Buffer Add Request */
#define REG_CAN1_TXBCR (0x420020D4) /**< \brief (CAN1) Tx Buffer Cancellation Request */
#define REG_CAN1_TXBTO (0x420020D8) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
#define REG_CAN1_TXBCF (0x420020DC) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
#define REG_CAN1_TXBTIE (0x420020E0) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN1_TXBCIE (0x420020E4) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN1_TXEFC (0x420020F0) /**< \brief (CAN1) Tx Event FIFO Configuration */
#define REG_CAN1_TXEFS (0x420020F4) /**< \brief (CAN1) Tx Event FIFO Status */
#define REG_CAN1_TXEFA (0x420020F8) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
#else
#define REG_CAN1_CREL (*(RoReg *)0x42002000UL) /**< \brief (CAN1) Core Release */
#define REG_CAN1_ENDN (*(RoReg *)0x42002004UL) /**< \brief (CAN1) Endian */
#define REG_CAN1_MRCFG (*(RwReg *)0x42002008UL) /**< \brief (CAN1) Message RAM Configuration */
#define REG_CAN1_DBTP (*(RwReg *)0x4200200CUL) /**< \brief (CAN1) Fast Bit Timing and Prescaler */
#define REG_CAN1_TEST (*(RwReg *)0x42002010UL) /**< \brief (CAN1) Test */
#define REG_CAN1_RWD (*(RwReg *)0x42002014UL) /**< \brief (CAN1) RAM Watchdog */
#define REG_CAN1_CCCR (*(RwReg *)0x42002018UL) /**< \brief (CAN1) CC Control */
#define REG_CAN1_NBTP (*(RwReg *)0x4200201CUL) /**< \brief (CAN1) Nominal Bit Timing and Prescaler */
#define REG_CAN1_TSCC (*(RwReg *)0x42002020UL) /**< \brief (CAN1) Timestamp Counter Configuration */
#define REG_CAN1_TSCV (*(RoReg *)0x42002024UL) /**< \brief (CAN1) Timestamp Counter Value */
#define REG_CAN1_TOCC (*(RwReg *)0x42002028UL) /**< \brief (CAN1) Timeout Counter Configuration */
#define REG_CAN1_TOCV (*(RwReg *)0x4200202CUL) /**< \brief (CAN1) Timeout Counter Value */
#define REG_CAN1_ECR (*(RoReg *)0x42002040UL) /**< \brief (CAN1) Error Counter */
#define REG_CAN1_PSR (*(RoReg *)0x42002044UL) /**< \brief (CAN1) Protocol Status */
#define REG_CAN1_TDCR (*(RwReg *)0x42002048UL) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_IR (*(RwReg *)0x42002050UL) /**< \brief (CAN1) Interrupt */
#define REG_CAN1_IE (*(RwReg *)0x42002054UL) /**< \brief (CAN1) Interrupt Enable */
#define REG_CAN1_ILS (*(RwReg *)0x42002058UL) /**< \brief (CAN1) Interrupt Line Select */
#define REG_CAN1_ILE (*(RwReg *)0x4200205CUL) /**< \brief (CAN1) Interrupt Line Enable */
#define REG_CAN1_GFC (*(RwReg *)0x42002080UL) /**< \brief (CAN1) Global Filter Configuration */
#define REG_CAN1_SIDFC (*(RwReg *)0x42002084UL) /**< \brief (CAN1) Standard ID Filter Configuration */
#define REG_CAN1_XIDFC (*(RwReg *)0x42002088UL) /**< \brief (CAN1) Extended ID Filter Configuration */
#define REG_CAN1_XIDAM (*(RwReg *)0x42002090UL) /**< \brief (CAN1) Extended ID AND Mask */
#define REG_CAN1_HPMS (*(RoReg *)0x42002094UL) /**< \brief (CAN1) High Priority Message Status */
#define REG_CAN1_NDAT1 (*(RwReg *)0x42002098UL) /**< \brief (CAN1) New Data 1 */
#define REG_CAN1_NDAT2 (*(RwReg *)0x4200209CUL) /**< \brief (CAN1) New Data 2 */
#define REG_CAN1_RXF0C (*(RwReg *)0x420020A0UL) /**< \brief (CAN1) Rx FIFO 0 Configuration */
#define REG_CAN1_RXF0S (*(RoReg *)0x420020A4UL) /**< \brief (CAN1) Rx FIFO 0 Status */
#define REG_CAN1_RXF0A (*(RwReg *)0x420020A8UL) /**< \brief (CAN1) Rx FIFO 0 Acknowledge */
#define REG_CAN1_RXBC (*(RwReg *)0x420020ACUL) /**< \brief (CAN1) Rx Buffer Configuration */
#define REG_CAN1_RXF1C (*(RwReg *)0x420020B0UL) /**< \brief (CAN1) Rx FIFO 1 Configuration */
#define REG_CAN1_RXF1S (*(RoReg *)0x420020B4UL) /**< \brief (CAN1) Rx FIFO 1 Status */
#define REG_CAN1_RXF1A (*(RwReg *)0x420020B8UL) /**< \brief (CAN1) Rx FIFO 1 Acknowledge */
#define REG_CAN1_RXESC (*(RwReg *)0x420020BCUL) /**< \brief (CAN1) Rx Buffer / FIFO Element Size Configuration */
#define REG_CAN1_TXBC (*(RwReg *)0x420020C0UL) /**< \brief (CAN1) Tx Buffer Configuration */
#define REG_CAN1_TXFQS (*(RoReg *)0x420020C4UL) /**< \brief (CAN1) Tx FIFO / Queue Status */
#define REG_CAN1_TXESC (*(RwReg *)0x420020C8UL) /**< \brief (CAN1) Tx Buffer Element Size Configuration */
#define REG_CAN1_TXBRP (*(RoReg *)0x420020CCUL) /**< \brief (CAN1) Tx Buffer Request Pending */
#define REG_CAN1_TXBAR (*(RwReg *)0x420020D0UL) /**< \brief (CAN1) Tx Buffer Add Request */
#define REG_CAN1_TXBCR (*(RwReg *)0x420020D4UL) /**< \brief (CAN1) Tx Buffer Cancellation Request */
#define REG_CAN1_TXBTO (*(RoReg *)0x420020D8UL) /**< \brief (CAN1) Tx Buffer Transmission Occurred */
#define REG_CAN1_TXBCF (*(RoReg *)0x420020DCUL) /**< \brief (CAN1) Tx Buffer Cancellation Finished */
#define REG_CAN1_TXBTIE (*(RwReg *)0x420020E0UL) /**< \brief (CAN1) Tx Buffer Transmission Interrupt Enable */
#define REG_CAN1_TXBCIE (*(RwReg *)0x420020E4UL) /**< \brief (CAN1) Tx Buffer Cancellation Finished Interrupt Enable */
#define REG_CAN1_TXEFC (*(RwReg *)0x420020F0UL) /**< \brief (CAN1) Tx Event FIFO Configuration */
#define REG_CAN1_TXEFS (*(RoReg *)0x420020F4UL) /**< \brief (CAN1) Tx Event FIFO Status */
#define REG_CAN1_TXEFA (*(RwReg *)0x420020F8UL) /**< \brief (CAN1) Tx Event FIFO Acknowledge */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for CAN1 peripheral ========== */
#define CAN1_CLK_AHB_ID 9 // Index of AHB clock
#define CAN1_DMAC_ID_DEBUG 15 // DMA CAN Debug Req
#define CAN1_GCLK_ID 27 // Index of Generic Clock
#define CAN1_MSG_RAM_ADDR 0x200000000
#define CAN1_QOS_RESET_VAL 2 // QOS reset value
#endif /* _SAMC21_CAN1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for CCL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_CCL_INSTANCE_
#define _SAMC21_CCL_INSTANCE_
/* ========== Register definition for CCL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CCL_CTRL (0x42005C00) /**< \brief (CCL) Control */
#define REG_CCL_SEQCTRL0 (0x42005C04) /**< \brief (CCL) SEQ Control x 0 */
#define REG_CCL_SEQCTRL1 (0x42005C05) /**< \brief (CCL) SEQ Control x 1 */
#define REG_CCL_LUTCTRL0 (0x42005C08) /**< \brief (CCL) LUT Control x 0 */
#define REG_CCL_LUTCTRL1 (0x42005C0C) /**< \brief (CCL) LUT Control x 1 */
#define REG_CCL_LUTCTRL2 (0x42005C10) /**< \brief (CCL) LUT Control x 2 */
#define REG_CCL_LUTCTRL3 (0x42005C14) /**< \brief (CCL) LUT Control x 3 */
#else
#define REG_CCL_CTRL (*(RwReg8 *)0x42005C00UL) /**< \brief (CCL) Control */
#define REG_CCL_SEQCTRL0 (*(RwReg8 *)0x42005C04UL) /**< \brief (CCL) SEQ Control x 0 */
#define REG_CCL_SEQCTRL1 (*(RwReg8 *)0x42005C05UL) /**< \brief (CCL) SEQ Control x 1 */
#define REG_CCL_LUTCTRL0 (*(RwReg *)0x42005C08UL) /**< \brief (CCL) LUT Control x 0 */
#define REG_CCL_LUTCTRL1 (*(RwReg *)0x42005C0CUL) /**< \brief (CCL) LUT Control x 1 */
#define REG_CCL_LUTCTRL2 (*(RwReg *)0x42005C10UL) /**< \brief (CCL) LUT Control x 2 */
#define REG_CCL_LUTCTRL3 (*(RwReg *)0x42005C14UL) /**< \brief (CCL) LUT Control x 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for CCL peripheral ========== */
#define CCL_GCLK_ID 38 // GCLK index for CCL
#define CCL_IO_NUM 12 // Numer of input pins
#define CCL_LUT_NUM 4 // Number of LUT in a CCL
#define CCL_SEQ_NUM 2 // Number of SEQ in a CCL
#endif /* _SAMC21_CCL_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for DAC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DAC_INSTANCE_
#define _SAMC21_DAC_INSTANCE_
/* ========== Register definition for DAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DAC_CTRLA (0x42005400) /**< \brief (DAC) Control A */
#define REG_DAC_CTRLB (0x42005401) /**< \brief (DAC) Control B */
#define REG_DAC_EVCTRL (0x42005402) /**< \brief (DAC) Event Control */
#define REG_DAC_INTENCLR (0x42005404) /**< \brief (DAC) Interrupt Enable Clear */
#define REG_DAC_INTENSET (0x42005405) /**< \brief (DAC) Interrupt Enable Set */
#define REG_DAC_INTFLAG (0x42005406) /**< \brief (DAC) Interrupt Flag Status and Clear */
#define REG_DAC_STATUS (0x42005407) /**< \brief (DAC) Status */
#define REG_DAC_DATA (0x42005408) /**< \brief (DAC) Data */
#define REG_DAC_DATABUF (0x4200540C) /**< \brief (DAC) Data Buffer */
#define REG_DAC_SYNCBUSY (0x42005410) /**< \brief (DAC) Synchronization Busy */
#define REG_DAC_DBGCTRL (0x42005414) /**< \brief (DAC) Debug Control */
#else
#define REG_DAC_CTRLA (*(RwReg8 *)0x42005400UL) /**< \brief (DAC) Control A */
#define REG_DAC_CTRLB (*(RwReg8 *)0x42005401UL) /**< \brief (DAC) Control B */
#define REG_DAC_EVCTRL (*(RwReg8 *)0x42005402UL) /**< \brief (DAC) Event Control */
#define REG_DAC_INTENCLR (*(RwReg8 *)0x42005404UL) /**< \brief (DAC) Interrupt Enable Clear */
#define REG_DAC_INTENSET (*(RwReg8 *)0x42005405UL) /**< \brief (DAC) Interrupt Enable Set */
#define REG_DAC_INTFLAG (*(RwReg8 *)0x42005406UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
#define REG_DAC_STATUS (*(RoReg8 *)0x42005407UL) /**< \brief (DAC) Status */
#define REG_DAC_DATA (*(WoReg16*)0x42005408UL) /**< \brief (DAC) Data */
#define REG_DAC_DATABUF (*(WoReg16*)0x4200540CUL) /**< \brief (DAC) Data Buffer */
#define REG_DAC_SYNCBUSY (*(RoReg *)0x42005410UL) /**< \brief (DAC) Synchronization Busy */
#define REG_DAC_DBGCTRL (*(RwReg8 *)0x42005414UL) /**< \brief (DAC) Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DAC peripheral ========== */
#define DAC_DMAC_ID_EMPTY 45 // Index of DMA EMPTY trigger
#define DAC_GCLK_ID 36
#endif /* _SAMC21_DAC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for DIVAS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DIVAS_INSTANCE_
#define _SAMC21_DIVAS_INSTANCE_
/* ========== Register definition for DIVAS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DIVAS_CTRLA (0x48000000) /**< \brief (DIVAS) Control */
#define REG_DIVAS_STATUS (0x48000004) /**< \brief (DIVAS) Status */
#define REG_DIVAS_DIVIDEND (0x48000008) /**< \brief (DIVAS) Dividend */
#define REG_DIVAS_DIVISOR (0x4800000C) /**< \brief (DIVAS) Divisor */
#define REG_DIVAS_RESULT (0x48000010) /**< \brief (DIVAS) Result */
#define REG_DIVAS_REM (0x48000014) /**< \brief (DIVAS) Remainder */
#define REG_DIVAS_SQRNUM (0x48000018) /**< \brief (DIVAS) Square Root Input */
#else
#define REG_DIVAS_CTRLA (*(RwReg8 *)0x48000000UL) /**< \brief (DIVAS) Control */
#define REG_DIVAS_STATUS (*(RwReg8 *)0x48000004UL) /**< \brief (DIVAS) Status */
#define REG_DIVAS_DIVIDEND (*(RwReg *)0x48000008UL) /**< \brief (DIVAS) Dividend */
#define REG_DIVAS_DIVISOR (*(RwReg *)0x4800000CUL) /**< \brief (DIVAS) Divisor */
#define REG_DIVAS_RESULT (*(RoReg *)0x48000010UL) /**< \brief (DIVAS) Result */
#define REG_DIVAS_REM (*(RoReg *)0x48000014UL) /**< \brief (DIVAS) Remainder */
#define REG_DIVAS_SQRNUM (*(RwReg *)0x48000018UL) /**< \brief (DIVAS) Square Root Input */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DIVAS peripheral ========== */
#define DIVAS_CLK_AHB_ID 12 // AHB clock index
#endif /* _SAMC21_DIVAS_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for DMAC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DMAC_INSTANCE_
#define _SAMC21_DMAC_INSTANCE_
/* ========== Register definition for DMAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DMAC_CTRL (0x41006000) /**< \brief (DMAC) Control */
#define REG_DMAC_CRCCTRL (0x41006002) /**< \brief (DMAC) CRC Control */
#define REG_DMAC_CRCDATAIN (0x41006004) /**< \brief (DMAC) CRC Data Input */
#define REG_DMAC_CRCCHKSUM (0x41006008) /**< \brief (DMAC) CRC Checksum */
#define REG_DMAC_CRCSTATUS (0x4100600C) /**< \brief (DMAC) CRC Status */
#define REG_DMAC_DBGCTRL (0x4100600D) /**< \brief (DMAC) Debug Control */
#define REG_DMAC_QOSCTRL (0x4100600E) /**< \brief (DMAC) QOS Control */
#define REG_DMAC_SWTRIGCTRL (0x41006010) /**< \brief (DMAC) Software Trigger Control */
#define REG_DMAC_PRICTRL0 (0x41006014) /**< \brief (DMAC) Priority Control 0 */
#define REG_DMAC_INTPEND (0x41006020) /**< \brief (DMAC) Interrupt Pending */
#define REG_DMAC_INTSTATUS (0x41006024) /**< \brief (DMAC) Interrupt Status */
#define REG_DMAC_BUSYCH (0x41006028) /**< \brief (DMAC) Busy Channels */
#define REG_DMAC_PENDCH (0x4100602C) /**< \brief (DMAC) Pending Channels */
#define REG_DMAC_ACTIVE (0x41006030) /**< \brief (DMAC) Active Channel and Levels */
#define REG_DMAC_BASEADDR (0x41006034) /**< \brief (DMAC) Descriptor Memory Section Base Address */
#define REG_DMAC_WRBADDR (0x41006038) /**< \brief (DMAC) Write-Back Memory Section Base Address */
#define REG_DMAC_CHID (0x4100603F) /**< \brief (DMAC) Channel ID */
#define REG_DMAC_CHCTRLA (0x41006040) /**< \brief (DMAC) Channel Control A */
#define REG_DMAC_CHCTRLB (0x41006044) /**< \brief (DMAC) Channel Control B */
#define REG_DMAC_CHINTENCLR (0x4100604C) /**< \brief (DMAC) Channel Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET (0x4100604D) /**< \brief (DMAC) Channel Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG (0x4100604E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS (0x4100604F) /**< \brief (DMAC) Channel Status */
#else
#define REG_DMAC_CTRL (*(RwReg16*)0x41006000UL) /**< \brief (DMAC) Control */
#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41006002UL) /**< \brief (DMAC) CRC Control */
#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41006004UL) /**< \brief (DMAC) CRC Data Input */
#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41006008UL) /**< \brief (DMAC) CRC Checksum */
#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100600CUL) /**< \brief (DMAC) CRC Status */
#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100600DUL) /**< \brief (DMAC) Debug Control */
#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100600EUL) /**< \brief (DMAC) QOS Control */
#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41006010UL) /**< \brief (DMAC) Software Trigger Control */
#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41006014UL) /**< \brief (DMAC) Priority Control 0 */
#define REG_DMAC_INTPEND (*(RwReg16*)0x41006020UL) /**< \brief (DMAC) Interrupt Pending */
#define REG_DMAC_INTSTATUS (*(RoReg *)0x41006024UL) /**< \brief (DMAC) Interrupt Status */
#define REG_DMAC_BUSYCH (*(RoReg *)0x41006028UL) /**< \brief (DMAC) Busy Channels */
#define REG_DMAC_PENDCH (*(RoReg *)0x4100602CUL) /**< \brief (DMAC) Pending Channels */
#define REG_DMAC_ACTIVE (*(RoReg *)0x41006030UL) /**< \brief (DMAC) Active Channel and Levels */
#define REG_DMAC_BASEADDR (*(RwReg *)0x41006034UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
#define REG_DMAC_WRBADDR (*(RwReg *)0x41006038UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
#define REG_DMAC_CHID (*(RwReg8 *)0x4100603FUL) /**< \brief (DMAC) Channel ID */
#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41006040UL) /**< \brief (DMAC) Channel Control A */
#define REG_DMAC_CHCTRLB (*(RwReg *)0x41006044UL) /**< \brief (DMAC) Channel Control B */
#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100604CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */
#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100604DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */
#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100604EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100604FUL) /**< \brief (DMAC) Channel Status */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DMAC peripheral ========== */
#define DMAC_CH_BITS 4 // Number of bits to select channel
#define DMAC_CLK_AHB_ID 7 // AHB clock index
#define DMAC_EVIN_NUM 4 // Number of input events
#define DMAC_EVOUT_NUM 4 // Number of output events
#define DMAC_LVL_BITS 2 // Number of bit to select level priority
#define DMAC_LVL_NUM 4 // Enable priority level number
#define DMAC_QOSCTRL_D_RESETVALUE 2 // QOS dmac ahb interface reset value
#define DMAC_QOSCTRL_F_RESETVALUE 2 // QOS dmac fetch interface reset value
#define DMAC_QOSCTRL_WRB_RESETVALUE 2 // QOS dmac write back interface reset value
#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
#define DMAC_TRIG_NUM 49 // Number of peripheral triggers
#endif /* _SAMC21_DMAC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for DSU
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_DSU_INSTANCE_
#define _SAMC21_DSU_INSTANCE_
/* ========== Register definition for DSU peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */
#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */
#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */
#define REG_DSU_STATUSC (0x41002003) /**< \brief (DSU) Status C */
#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */
#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */
#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */
#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */
#define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */
#define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */
#define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */
#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
#define REG_DSU_PID5 (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */
#define REG_DSU_PID6 (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */
#define REG_DSU_PID7 (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */
#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
#else
#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
#define REG_DSU_STATUSC (*(RoReg8 *)0x41002003UL) /**< \brief (DSU) Status C */
#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */
#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */
#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */
#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */
#define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */
#define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */
#define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */
#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
#define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */
#define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */
#define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */
#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for DSU peripheral ========== */
#define DSU_CLK_AHB_ID 3
#endif /* _SAMC21_DSU_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for EIC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_EIC_INSTANCE_
#define _SAMC21_EIC_INSTANCE_
/* ========== Register definition for EIC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EIC_CTRLA (0x40002800) /**< \brief (EIC) Control */
#define REG_EIC_NMICTRL (0x40002801) /**< \brief (EIC) NMI Control */
#define REG_EIC_NMIFLAG (0x40002802) /**< \brief (EIC) NMI Interrupt Flag */
#define REG_EIC_SYNCBUSY (0x40002804) /**< \brief (EIC) Syncbusy register */
#define REG_EIC_EVCTRL (0x40002808) /**< \brief (EIC) Event Control */
#define REG_EIC_INTENCLR (0x4000280C) /**< \brief (EIC) Interrupt Enable Clear */
#define REG_EIC_INTENSET (0x40002810) /**< \brief (EIC) Interrupt Enable Set */
#define REG_EIC_INTFLAG (0x40002814) /**< \brief (EIC) Interrupt Flag Status and Clear */
#define REG_EIC_ASYNCH (0x40002818) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */
#define REG_EIC_CONFIG0 (0x4000281C) /**< \brief (EIC) Configuration 0 */
#define REG_EIC_CONFIG1 (0x40002820) /**< \brief (EIC) Configuration 1 */
#else
#define REG_EIC_CTRLA (*(RwReg8 *)0x40002800UL) /**< \brief (EIC) Control */
#define REG_EIC_NMICTRL (*(RwReg8 *)0x40002801UL) /**< \brief (EIC) NMI Control */
#define REG_EIC_NMIFLAG (*(RwReg16*)0x40002802UL) /**< \brief (EIC) NMI Interrupt Flag */
#define REG_EIC_SYNCBUSY (*(RoReg *)0x40002804UL) /**< \brief (EIC) Syncbusy register */
#define REG_EIC_EVCTRL (*(RwReg *)0x40002808UL) /**< \brief (EIC) Event Control */
#define REG_EIC_INTENCLR (*(RwReg *)0x4000280CUL) /**< \brief (EIC) Interrupt Enable Clear */
#define REG_EIC_INTENSET (*(RwReg *)0x40002810UL) /**< \brief (EIC) Interrupt Enable Set */
#define REG_EIC_INTFLAG (*(RwReg *)0x40002814UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
#define REG_EIC_ASYNCH (*(RwReg *)0x40002818UL) /**< \brief (EIC) EIC Asynchronous edge Detection Enable */
#define REG_EIC_CONFIG0 (*(RwReg *)0x4000281CUL) /**< \brief (EIC) Configuration 0 */
#define REG_EIC_CONFIG1 (*(RwReg *)0x40002820UL) /**< \brief (EIC) Configuration 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for EIC peripheral ========== */
#define EIC_EXTINT_NUM 16
#define EIC_GCLK_ID 2
#define EIC_NUMBER_OF_CONFIG_REGS 2
#define EIC_NUMBER_OF_INTERRUPTS 16
#endif /* _SAMC21_EIC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for EVSYS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_EVSYS_INSTANCE_
#define _SAMC21_EVSYS_INSTANCE_
/* ========== Register definition for EVSYS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EVSYS_CTRLA (0x42000000) /**< \brief (EVSYS) Control */
#define REG_EVSYS_CHSTATUS (0x4200000C) /**< \brief (EVSYS) Channel Status */
#define REG_EVSYS_INTENCLR (0x42000010) /**< \brief (EVSYS) Interrupt Enable Clear */
#define REG_EVSYS_INTENSET (0x42000014) /**< \brief (EVSYS) Interrupt Enable Set */
#define REG_EVSYS_INTFLAG (0x42000018) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
#define REG_EVSYS_SWEVT (0x4200001C) /**< \brief (EVSYS) Software Event */
#define REG_EVSYS_CHANNEL0 (0x42000020) /**< \brief (EVSYS) Channel 0 */
#define REG_EVSYS_CHANNEL1 (0x42000024) /**< \brief (EVSYS) Channel 1 */
#define REG_EVSYS_CHANNEL2 (0x42000028) /**< \brief (EVSYS) Channel 2 */
#define REG_EVSYS_CHANNEL3 (0x4200002C) /**< \brief (EVSYS) Channel 3 */
#define REG_EVSYS_CHANNEL4 (0x42000030) /**< \brief (EVSYS) Channel 4 */
#define REG_EVSYS_CHANNEL5 (0x42000034) /**< \brief (EVSYS) Channel 5 */
#define REG_EVSYS_CHANNEL6 (0x42000038) /**< \brief (EVSYS) Channel 6 */
#define REG_EVSYS_CHANNEL7 (0x4200003C) /**< \brief (EVSYS) Channel 7 */
#define REG_EVSYS_CHANNEL8 (0x42000040) /**< \brief (EVSYS) Channel 8 */
#define REG_EVSYS_CHANNEL9 (0x42000044) /**< \brief (EVSYS) Channel 9 */
#define REG_EVSYS_CHANNEL10 (0x42000048) /**< \brief (EVSYS) Channel 10 */
#define REG_EVSYS_CHANNEL11 (0x4200004C) /**< \brief (EVSYS) Channel 11 */
#define REG_EVSYS_USER0 (0x42000080) /**< \brief (EVSYS) User Multiplexer 0 */
#define REG_EVSYS_USER1 (0x42000084) /**< \brief (EVSYS) User Multiplexer 1 */
#define REG_EVSYS_USER2 (0x42000088) /**< \brief (EVSYS) User Multiplexer 2 */
#define REG_EVSYS_USER3 (0x4200008C) /**< \brief (EVSYS) User Multiplexer 3 */
#define REG_EVSYS_USER4 (0x42000090) /**< \brief (EVSYS) User Multiplexer 4 */
#define REG_EVSYS_USER5 (0x42000094) /**< \brief (EVSYS) User Multiplexer 5 */
#define REG_EVSYS_USER6 (0x42000098) /**< \brief (EVSYS) User Multiplexer 6 */
#define REG_EVSYS_USER7 (0x4200009C) /**< \brief (EVSYS) User Multiplexer 7 */
#define REG_EVSYS_USER8 (0x420000A0) /**< \brief (EVSYS) User Multiplexer 8 */
#define REG_EVSYS_USER9 (0x420000A4) /**< \brief (EVSYS) User Multiplexer 9 */
#define REG_EVSYS_USER10 (0x420000A8) /**< \brief (EVSYS) User Multiplexer 10 */
#define REG_EVSYS_USER11 (0x420000AC) /**< \brief (EVSYS) User Multiplexer 11 */
#define REG_EVSYS_USER12 (0x420000B0) /**< \brief (EVSYS) User Multiplexer 12 */
#define REG_EVSYS_USER13 (0x420000B4) /**< \brief (EVSYS) User Multiplexer 13 */
#define REG_EVSYS_USER14 (0x420000B8) /**< \brief (EVSYS) User Multiplexer 14 */
#define REG_EVSYS_USER15 (0x420000BC) /**< \brief (EVSYS) User Multiplexer 15 */
#define REG_EVSYS_USER16 (0x420000C0) /**< \brief (EVSYS) User Multiplexer 16 */
#define REG_EVSYS_USER17 (0x420000C4) /**< \brief (EVSYS) User Multiplexer 17 */
#define REG_EVSYS_USER18 (0x420000C8) /**< \brief (EVSYS) User Multiplexer 18 */
#define REG_EVSYS_USER19 (0x420000CC) /**< \brief (EVSYS) User Multiplexer 19 */
#define REG_EVSYS_USER20 (0x420000D0) /**< \brief (EVSYS) User Multiplexer 20 */
#define REG_EVSYS_USER21 (0x420000D4) /**< \brief (EVSYS) User Multiplexer 21 */
#define REG_EVSYS_USER22 (0x420000D8) /**< \brief (EVSYS) User Multiplexer 22 */
#define REG_EVSYS_USER23 (0x420000DC) /**< \brief (EVSYS) User Multiplexer 23 */
#define REG_EVSYS_USER24 (0x420000E0) /**< \brief (EVSYS) User Multiplexer 24 */
#define REG_EVSYS_USER25 (0x420000E4) /**< \brief (EVSYS) User Multiplexer 25 */
#define REG_EVSYS_USER26 (0x420000E8) /**< \brief (EVSYS) User Multiplexer 26 */
#define REG_EVSYS_USER27 (0x420000EC) /**< \brief (EVSYS) User Multiplexer 27 */
#define REG_EVSYS_USER28 (0x420000F0) /**< \brief (EVSYS) User Multiplexer 28 */
#define REG_EVSYS_USER29 (0x420000F4) /**< \brief (EVSYS) User Multiplexer 29 */
#define REG_EVSYS_USER30 (0x420000F8) /**< \brief (EVSYS) User Multiplexer 30 */
#define REG_EVSYS_USER31 (0x420000FC) /**< \brief (EVSYS) User Multiplexer 31 */
#define REG_EVSYS_USER32 (0x42000100) /**< \brief (EVSYS) User Multiplexer 32 */
#define REG_EVSYS_USER33 (0x42000104) /**< \brief (EVSYS) User Multiplexer 33 */
#define REG_EVSYS_USER34 (0x42000108) /**< \brief (EVSYS) User Multiplexer 34 */
#define REG_EVSYS_USER35 (0x4200010C) /**< \brief (EVSYS) User Multiplexer 35 */
#define REG_EVSYS_USER36 (0x42000110) /**< \brief (EVSYS) User Multiplexer 36 */
#define REG_EVSYS_USER37 (0x42000114) /**< \brief (EVSYS) User Multiplexer 37 */
#define REG_EVSYS_USER38 (0x42000118) /**< \brief (EVSYS) User Multiplexer 38 */
#define REG_EVSYS_USER39 (0x4200011C) /**< \brief (EVSYS) User Multiplexer 39 */
#define REG_EVSYS_USER40 (0x42000120) /**< \brief (EVSYS) User Multiplexer 40 */
#define REG_EVSYS_USER41 (0x42000124) /**< \brief (EVSYS) User Multiplexer 41 */
#define REG_EVSYS_USER42 (0x42000128) /**< \brief (EVSYS) User Multiplexer 42 */
#define REG_EVSYS_USER43 (0x4200012C) /**< \brief (EVSYS) User Multiplexer 43 */
#define REG_EVSYS_USER44 (0x42000130) /**< \brief (EVSYS) User Multiplexer 44 */
#define REG_EVSYS_USER45 (0x42000134) /**< \brief (EVSYS) User Multiplexer 45 */
#define REG_EVSYS_USER46 (0x42000138) /**< \brief (EVSYS) User Multiplexer 46 */
#else
#define REG_EVSYS_CTRLA (*(RwReg8 *)0x42000000UL) /**< \brief (EVSYS) Control */
#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200000CUL) /**< \brief (EVSYS) Channel Status */
#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000010UL) /**< \brief (EVSYS) Interrupt Enable Clear */
#define REG_EVSYS_INTENSET (*(RwReg *)0x42000014UL) /**< \brief (EVSYS) Interrupt Enable Set */
#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000018UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
#define REG_EVSYS_SWEVT (*(WoReg *)0x4200001CUL) /**< \brief (EVSYS) Software Event */
#define REG_EVSYS_CHANNEL0 (*(RwReg *)0x42000020UL) /**< \brief (EVSYS) Channel 0 */
#define REG_EVSYS_CHANNEL1 (*(RwReg *)0x42000024UL) /**< \brief (EVSYS) Channel 1 */
#define REG_EVSYS_CHANNEL2 (*(RwReg *)0x42000028UL) /**< \brief (EVSYS) Channel 2 */
#define REG_EVSYS_CHANNEL3 (*(RwReg *)0x4200002CUL) /**< \brief (EVSYS) Channel 3 */
#define REG_EVSYS_CHANNEL4 (*(RwReg *)0x42000030UL) /**< \brief (EVSYS) Channel 4 */
#define REG_EVSYS_CHANNEL5 (*(RwReg *)0x42000034UL) /**< \brief (EVSYS) Channel 5 */
#define REG_EVSYS_CHANNEL6 (*(RwReg *)0x42000038UL) /**< \brief (EVSYS) Channel 6 */
#define REG_EVSYS_CHANNEL7 (*(RwReg *)0x4200003CUL) /**< \brief (EVSYS) Channel 7 */
#define REG_EVSYS_CHANNEL8 (*(RwReg *)0x42000040UL) /**< \brief (EVSYS) Channel 8 */
#define REG_EVSYS_CHANNEL9 (*(RwReg *)0x42000044UL) /**< \brief (EVSYS) Channel 9 */
#define REG_EVSYS_CHANNEL10 (*(RwReg *)0x42000048UL) /**< \brief (EVSYS) Channel 10 */
#define REG_EVSYS_CHANNEL11 (*(RwReg *)0x4200004CUL) /**< \brief (EVSYS) Channel 11 */
#define REG_EVSYS_USER0 (*(RwReg *)0x42000080UL) /**< \brief (EVSYS) User Multiplexer 0 */
#define REG_EVSYS_USER1 (*(RwReg *)0x42000084UL) /**< \brief (EVSYS) User Multiplexer 1 */
#define REG_EVSYS_USER2 (*(RwReg *)0x42000088UL) /**< \brief (EVSYS) User Multiplexer 2 */
#define REG_EVSYS_USER3 (*(RwReg *)0x4200008CUL) /**< \brief (EVSYS) User Multiplexer 3 */
#define REG_EVSYS_USER4 (*(RwReg *)0x42000090UL) /**< \brief (EVSYS) User Multiplexer 4 */
#define REG_EVSYS_USER5 (*(RwReg *)0x42000094UL) /**< \brief (EVSYS) User Multiplexer 5 */
#define REG_EVSYS_USER6 (*(RwReg *)0x42000098UL) /**< \brief (EVSYS) User Multiplexer 6 */
#define REG_EVSYS_USER7 (*(RwReg *)0x4200009CUL) /**< \brief (EVSYS) User Multiplexer 7 */
#define REG_EVSYS_USER8 (*(RwReg *)0x420000A0UL) /**< \brief (EVSYS) User Multiplexer 8 */
#define REG_EVSYS_USER9 (*(RwReg *)0x420000A4UL) /**< \brief (EVSYS) User Multiplexer 9 */
#define REG_EVSYS_USER10 (*(RwReg *)0x420000A8UL) /**< \brief (EVSYS) User Multiplexer 10 */
#define REG_EVSYS_USER11 (*(RwReg *)0x420000ACUL) /**< \brief (EVSYS) User Multiplexer 11 */
#define REG_EVSYS_USER12 (*(RwReg *)0x420000B0UL) /**< \brief (EVSYS) User Multiplexer 12 */
#define REG_EVSYS_USER13 (*(RwReg *)0x420000B4UL) /**< \brief (EVSYS) User Multiplexer 13 */
#define REG_EVSYS_USER14 (*(RwReg *)0x420000B8UL) /**< \brief (EVSYS) User Multiplexer 14 */
#define REG_EVSYS_USER15 (*(RwReg *)0x420000BCUL) /**< \brief (EVSYS) User Multiplexer 15 */
#define REG_EVSYS_USER16 (*(RwReg *)0x420000C0UL) /**< \brief (EVSYS) User Multiplexer 16 */
#define REG_EVSYS_USER17 (*(RwReg *)0x420000C4UL) /**< \brief (EVSYS) User Multiplexer 17 */
#define REG_EVSYS_USER18 (*(RwReg *)0x420000C8UL) /**< \brief (EVSYS) User Multiplexer 18 */
#define REG_EVSYS_USER19 (*(RwReg *)0x420000CCUL) /**< \brief (EVSYS) User Multiplexer 19 */
#define REG_EVSYS_USER20 (*(RwReg *)0x420000D0UL) /**< \brief (EVSYS) User Multiplexer 20 */
#define REG_EVSYS_USER21 (*(RwReg *)0x420000D4UL) /**< \brief (EVSYS) User Multiplexer 21 */
#define REG_EVSYS_USER22 (*(RwReg *)0x420000D8UL) /**< \brief (EVSYS) User Multiplexer 22 */
#define REG_EVSYS_USER23 (*(RwReg *)0x420000DCUL) /**< \brief (EVSYS) User Multiplexer 23 */
#define REG_EVSYS_USER24 (*(RwReg *)0x420000E0UL) /**< \brief (EVSYS) User Multiplexer 24 */
#define REG_EVSYS_USER25 (*(RwReg *)0x420000E4UL) /**< \brief (EVSYS) User Multiplexer 25 */
#define REG_EVSYS_USER26 (*(RwReg *)0x420000E8UL) /**< \brief (EVSYS) User Multiplexer 26 */
#define REG_EVSYS_USER27 (*(RwReg *)0x420000ECUL) /**< \brief (EVSYS) User Multiplexer 27 */
#define REG_EVSYS_USER28 (*(RwReg *)0x420000F0UL) /**< \brief (EVSYS) User Multiplexer 28 */
#define REG_EVSYS_USER29 (*(RwReg *)0x420000F4UL) /**< \brief (EVSYS) User Multiplexer 29 */
#define REG_EVSYS_USER30 (*(RwReg *)0x420000F8UL) /**< \brief (EVSYS) User Multiplexer 30 */
#define REG_EVSYS_USER31 (*(RwReg *)0x420000FCUL) /**< \brief (EVSYS) User Multiplexer 31 */
#define REG_EVSYS_USER32 (*(RwReg *)0x42000100UL) /**< \brief (EVSYS) User Multiplexer 32 */
#define REG_EVSYS_USER33 (*(RwReg *)0x42000104UL) /**< \brief (EVSYS) User Multiplexer 33 */
#define REG_EVSYS_USER34 (*(RwReg *)0x42000108UL) /**< \brief (EVSYS) User Multiplexer 34 */
#define REG_EVSYS_USER35 (*(RwReg *)0x4200010CUL) /**< \brief (EVSYS) User Multiplexer 35 */
#define REG_EVSYS_USER36 (*(RwReg *)0x42000110UL) /**< \brief (EVSYS) User Multiplexer 36 */
#define REG_EVSYS_USER37 (*(RwReg *)0x42000114UL) /**< \brief (EVSYS) User Multiplexer 37 */
#define REG_EVSYS_USER38 (*(RwReg *)0x42000118UL) /**< \brief (EVSYS) User Multiplexer 38 */
#define REG_EVSYS_USER39 (*(RwReg *)0x4200011CUL) /**< \brief (EVSYS) User Multiplexer 39 */
#define REG_EVSYS_USER40 (*(RwReg *)0x42000120UL) /**< \brief (EVSYS) User Multiplexer 40 */
#define REG_EVSYS_USER41 (*(RwReg *)0x42000124UL) /**< \brief (EVSYS) User Multiplexer 41 */
#define REG_EVSYS_USER42 (*(RwReg *)0x42000128UL) /**< \brief (EVSYS) User Multiplexer 42 */
#define REG_EVSYS_USER43 (*(RwReg *)0x4200012CUL) /**< \brief (EVSYS) User Multiplexer 43 */
#define REG_EVSYS_USER44 (*(RwReg *)0x42000130UL) /**< \brief (EVSYS) User Multiplexer 44 */
#define REG_EVSYS_USER45 (*(RwReg *)0x42000134UL) /**< \brief (EVSYS) User Multiplexer 45 */
#define REG_EVSYS_USER46 (*(RwReg *)0x42000138UL) /**< \brief (EVSYS) User Multiplexer 46 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for EVSYS peripheral ========== */
#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel
#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1
#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators
#define EVSYS_GCLK_ID_0 6
#define EVSYS_GCLK_ID_1 7
#define EVSYS_GCLK_ID_2 8
#define EVSYS_GCLK_ID_3 9
#define EVSYS_GCLK_ID_4 10
#define EVSYS_GCLK_ID_5 11
#define EVSYS_GCLK_ID_6 12
#define EVSYS_GCLK_ID_7 13
#define EVSYS_GCLK_ID_8 14
#define EVSYS_GCLK_ID_9 15
#define EVSYS_GCLK_ID_10 16
#define EVSYS_GCLK_ID_11 17
#define EVSYS_GCLK_ID_LSB 6
#define EVSYS_GCLK_ID_MSB 17
#define EVSYS_GCLK_ID_SIZE 12
#define EVSYS_GENERATORS 87 // Total Number of Event Generators
#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator
#define EVSYS_USERS 47 // Total Number of Event Users
#define EVSYS_USERS_BITS 6 // Number of bits to select Event User
// GENERATORS
#define EVSYS_ID_GEN_OSCCTRL_XOSC_FAIL 1
#define EVSYS_ID_GEN_OSC32KCTRL_XOSC32K_FAIL 2
#define EVSYS_ID_GEN_RTC_CMP_0 3
#define EVSYS_ID_GEN_RTC_CMP_1 4
#define EVSYS_ID_GEN_RTC_OVF 5
#define EVSYS_ID_GEN_RTC_PER_0 6
#define EVSYS_ID_GEN_RTC_PER_1 7
#define EVSYS_ID_GEN_RTC_PER_2 8
#define EVSYS_ID_GEN_RTC_PER_3 9
#define EVSYS_ID_GEN_RTC_PER_4 10
#define EVSYS_ID_GEN_RTC_PER_5 11
#define EVSYS_ID_GEN_RTC_PER_6 12
#define EVSYS_ID_GEN_RTC_PER_7 13
#define EVSYS_ID_GEN_EIC_EXTINT_0 14
#define EVSYS_ID_GEN_EIC_EXTINT_1 15
#define EVSYS_ID_GEN_EIC_EXTINT_2 16
#define EVSYS_ID_GEN_EIC_EXTINT_3 17
#define EVSYS_ID_GEN_EIC_EXTINT_4 18
#define EVSYS_ID_GEN_EIC_EXTINT_5 19
#define EVSYS_ID_GEN_EIC_EXTINT_6 20
#define EVSYS_ID_GEN_EIC_EXTINT_7 21
#define EVSYS_ID_GEN_EIC_EXTINT_8 22
#define EVSYS_ID_GEN_EIC_EXTINT_9 23
#define EVSYS_ID_GEN_EIC_EXTINT_10 24
#define EVSYS_ID_GEN_EIC_EXTINT_11 25
#define EVSYS_ID_GEN_EIC_EXTINT_12 26
#define EVSYS_ID_GEN_EIC_EXTINT_13 27
#define EVSYS_ID_GEN_EIC_EXTINT_14 28
#define EVSYS_ID_GEN_EIC_EXTINT_15 29
#define EVSYS_ID_GEN_TSENS_WINMON 30
#define EVSYS_ID_GEN_DMAC_CH_0 31
#define EVSYS_ID_GEN_DMAC_CH_1 32
#define EVSYS_ID_GEN_DMAC_CH_2 33
#define EVSYS_ID_GEN_DMAC_CH_3 34
#define EVSYS_ID_GEN_TCC0_OVF 35
#define EVSYS_ID_GEN_TCC0_TRG 36
#define EVSYS_ID_GEN_TCC0_CNT 37
#define EVSYS_ID_GEN_TCC0_MCX_0 38
#define EVSYS_ID_GEN_TCC0_MCX_1 39
#define EVSYS_ID_GEN_TCC0_MCX_2 40
#define EVSYS_ID_GEN_TCC0_MCX_3 41
#define EVSYS_ID_GEN_TCC1_OVF 42
#define EVSYS_ID_GEN_TCC1_TRG 43
#define EVSYS_ID_GEN_TCC1_CNT 44
#define EVSYS_ID_GEN_TCC1_MCX_0 45
#define EVSYS_ID_GEN_TCC1_MCX_1 46
#define EVSYS_ID_GEN_TCC2_OVF 47
#define EVSYS_ID_GEN_TCC2_TRG 48
#define EVSYS_ID_GEN_TCC2_CNT 49
#define EVSYS_ID_GEN_TCC2_MCX_0 50
#define EVSYS_ID_GEN_TCC2_MCX_1 51
#define EVSYS_ID_GEN_TC0_OVF 52
#define EVSYS_ID_GEN_TC0_MCX_0 53
#define EVSYS_ID_GEN_TC0_MCX_1 54
#define EVSYS_ID_GEN_TC1_OVF 55
#define EVSYS_ID_GEN_TC1_MCX_0 56
#define EVSYS_ID_GEN_TC1_MCX_1 57
#define EVSYS_ID_GEN_TC2_OVF 58
#define EVSYS_ID_GEN_TC2_MCX_0 59
#define EVSYS_ID_GEN_TC2_MCX_1 60
#define EVSYS_ID_GEN_TC3_OVF 61
#define EVSYS_ID_GEN_TC3_MCX_0 62
#define EVSYS_ID_GEN_TC3_MCX_1 63
#define EVSYS_ID_GEN_TC4_OVF 64
#define EVSYS_ID_GEN_TC4_MCX_0 65
#define EVSYS_ID_GEN_TC4_MCX_1 66
#define EVSYS_ID_GEN_ADC0_RESRDY 67
#define EVSYS_ID_GEN_ADC0_WINMON 68
#define EVSYS_ID_GEN_ADC1_RESRDY 69
#define EVSYS_ID_GEN_ADC1_WINMON 70
#define EVSYS_ID_GEN_SDADC_RESRDY 71
#define EVSYS_ID_GEN_SDADC_WINMON 72
#define EVSYS_ID_GEN_AC_COMP_0 73
#define EVSYS_ID_GEN_AC_COMP_1 74
#define EVSYS_ID_GEN_AC_COMP_2 75
#define EVSYS_ID_GEN_AC_COMP_3 76
#define EVSYS_ID_GEN_AC_WIN_0 77
#define EVSYS_ID_GEN_AC_WIN_1 78
#define EVSYS_ID_GEN_DAC_EMPTY 79
#define EVSYS_ID_GEN_CCL_LUTOUT_0 82
#define EVSYS_ID_GEN_CCL_LUTOUT_1 83
#define EVSYS_ID_GEN_CCL_LUTOUT_2 84
#define EVSYS_ID_GEN_CCL_LUTOUT_3 85
#define EVSYS_ID_GEN_PAC_ACCERR 86
// USERS
#define EVSYS_ID_USER_TSENS_START 0
#define EVSYS_ID_USER_PORT_EV_0 1
#define EVSYS_ID_USER_PORT_EV_1 2
#define EVSYS_ID_USER_PORT_EV_2 3
#define EVSYS_ID_USER_PORT_EV_3 4
#define EVSYS_ID_USER_DMAC_CH_0 5
#define EVSYS_ID_USER_DMAC_CH_1 6
#define EVSYS_ID_USER_DMAC_CH_2 7
#define EVSYS_ID_USER_DMAC_CH_3 8
#define EVSYS_ID_USER_TCC0_EV_0 9
#define EVSYS_ID_USER_TCC0_EV_1 10
#define EVSYS_ID_USER_TCC0_MC_0 11
#define EVSYS_ID_USER_TCC0_MC_1 12
#define EVSYS_ID_USER_TCC0_MC_2 13
#define EVSYS_ID_USER_TCC0_MC_3 14
#define EVSYS_ID_USER_TCC1_EV_0 15
#define EVSYS_ID_USER_TCC1_EV_1 16
#define EVSYS_ID_USER_TCC1_MC_0 17
#define EVSYS_ID_USER_TCC1_MC_1 18
#define EVSYS_ID_USER_TCC2_EV_0 19
#define EVSYS_ID_USER_TCC2_EV_1 20
#define EVSYS_ID_USER_TCC2_MC_0 21
#define EVSYS_ID_USER_TCC2_MC_1 22
#define EVSYS_ID_USER_TC0_EVU 23
#define EVSYS_ID_USER_TC1_EVU 24
#define EVSYS_ID_USER_TC2_EVU 25
#define EVSYS_ID_USER_TC3_EVU 26
#define EVSYS_ID_USER_TC4_EVU 27
#define EVSYS_ID_USER_ADC0_START 28
#define EVSYS_ID_USER_ADC0_SYNC 29
#define EVSYS_ID_USER_ADC1_START 30
#define EVSYS_ID_USER_ADC1_SYNC 31
#define EVSYS_ID_USER_SDADC_START 32
#define EVSYS_ID_USER_SDADC_FLUSH 33
#define EVSYS_ID_USER_AC_SOC_0 34
#define EVSYS_ID_USER_AC_SOC_1 35
#define EVSYS_ID_USER_AC_SOC_2 36
#define EVSYS_ID_USER_AC_SOC_3 37
#define EVSYS_ID_USER_DAC_START 38
#define EVSYS_ID_USER_CCL_LUTIN_0 40
#define EVSYS_ID_USER_CCL_LUTIN_1 41
#define EVSYS_ID_USER_CCL_LUTIN_2 42
#define EVSYS_ID_USER_CCL_LUTIN_3 43
#define EVSYS_ID_USER_MTB_START 45
#define EVSYS_ID_USER_MTB_STOP 46
#endif /* _SAMC21_EVSYS_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for FREQM
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_FREQM_INSTANCE_
#define _SAMC21_FREQM_INSTANCE_
/* ========== Register definition for FREQM peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_FREQM_CTRLA (0x40002C00) /**< \brief (FREQM) Control A Register */
#define REG_FREQM_CTRLB (0x40002C01) /**< \brief (FREQM) Control B Register */
#define REG_FREQM_CFGA (0x40002C02) /**< \brief (FREQM) Config A register */
#define REG_FREQM_INTENCLR (0x40002C08) /**< \brief (FREQM) Interrupt Enable Clear Register */
#define REG_FREQM_INTENSET (0x40002C09) /**< \brief (FREQM) Interrupt Enable Set Register */
#define REG_FREQM_INTFLAG (0x40002C0A) /**< \brief (FREQM) Interrupt Flag Register */
#define REG_FREQM_STATUS (0x40002C0B) /**< \brief (FREQM) Status Register */
#define REG_FREQM_SYNCBUSY (0x40002C0C) /**< \brief (FREQM) Synchronization Busy Register */
#define REG_FREQM_VALUE (0x40002C10) /**< \brief (FREQM) Count Value Register */
#else
#define REG_FREQM_CTRLA (*(RwReg8 *)0x40002C00UL) /**< \brief (FREQM) Control A Register */
#define REG_FREQM_CTRLB (*(WoReg8 *)0x40002C01UL) /**< \brief (FREQM) Control B Register */
#define REG_FREQM_CFGA (*(RwReg16*)0x40002C02UL) /**< \brief (FREQM) Config A register */
#define REG_FREQM_INTENCLR (*(RwReg8 *)0x40002C08UL) /**< \brief (FREQM) Interrupt Enable Clear Register */
#define REG_FREQM_INTENSET (*(RwReg8 *)0x40002C09UL) /**< \brief (FREQM) Interrupt Enable Set Register */
#define REG_FREQM_INTFLAG (*(RwReg8 *)0x40002C0AUL) /**< \brief (FREQM) Interrupt Flag Register */
#define REG_FREQM_STATUS (*(RwReg8 *)0x40002C0BUL) /**< \brief (FREQM) Status Register */
#define REG_FREQM_SYNCBUSY (*(RoReg *)0x40002C0CUL) /**< \brief (FREQM) Synchronization Busy Register */
#define REG_FREQM_VALUE (*(RoReg *)0x40002C10UL) /**< \brief (FREQM) Count Value Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for FREQM peripheral ========== */
#define FREQM_GCLK_ID_MSR 3 // Index of measure generic clock
#define FREQM_GCLK_ID_REF 4 // Index of reference generic clock
#endif /* _SAMC21_FREQM_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for GCLK
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_GCLK_INSTANCE_
#define _SAMC21_GCLK_INSTANCE_
/* ========== Register definition for GCLK peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_GCLK_CTRLA (0x40001C00) /**< \brief (GCLK) Control */
#define REG_GCLK_SYNCBUSY (0x40001C04) /**< \brief (GCLK) Synchronization Busy */
#define REG_GCLK_GENCTRL0 (0x40001C20) /**< \brief (GCLK) Generic Clock Generator Control 0 */
#define REG_GCLK_GENCTRL1 (0x40001C24) /**< \brief (GCLK) Generic Clock Generator Control 1 */
#define REG_GCLK_GENCTRL2 (0x40001C28) /**< \brief (GCLK) Generic Clock Generator Control 2 */
#define REG_GCLK_GENCTRL3 (0x40001C2C) /**< \brief (GCLK) Generic Clock Generator Control 3 */
#define REG_GCLK_GENCTRL4 (0x40001C30) /**< \brief (GCLK) Generic Clock Generator Control 4 */
#define REG_GCLK_GENCTRL5 (0x40001C34) /**< \brief (GCLK) Generic Clock Generator Control 5 */
#define REG_GCLK_GENCTRL6 (0x40001C38) /**< \brief (GCLK) Generic Clock Generator Control 6 */
#define REG_GCLK_GENCTRL7 (0x40001C3C) /**< \brief (GCLK) Generic Clock Generator Control 7 */
#define REG_GCLK_GENCTRL8 (0x40001C40) /**< \brief (GCLK) Generic Clock Generator Control 8 */
#define REG_GCLK_PCHCTRL0 (0x40001C80) /**< \brief (GCLK) Peripheral Clock Control 0 */
#define REG_GCLK_PCHCTRL1 (0x40001C84) /**< \brief (GCLK) Peripheral Clock Control 1 */
#define REG_GCLK_PCHCTRL2 (0x40001C88) /**< \brief (GCLK) Peripheral Clock Control 2 */
#define REG_GCLK_PCHCTRL3 (0x40001C8C) /**< \brief (GCLK) Peripheral Clock Control 3 */
#define REG_GCLK_PCHCTRL4 (0x40001C90) /**< \brief (GCLK) Peripheral Clock Control 4 */
#define REG_GCLK_PCHCTRL5 (0x40001C94) /**< \brief (GCLK) Peripheral Clock Control 5 */
#define REG_GCLK_PCHCTRL6 (0x40001C98) /**< \brief (GCLK) Peripheral Clock Control 6 */
#define REG_GCLK_PCHCTRL7 (0x40001C9C) /**< \brief (GCLK) Peripheral Clock Control 7 */
#define REG_GCLK_PCHCTRL8 (0x40001CA0) /**< \brief (GCLK) Peripheral Clock Control 8 */
#define REG_GCLK_PCHCTRL9 (0x40001CA4) /**< \brief (GCLK) Peripheral Clock Control 9 */
#define REG_GCLK_PCHCTRL10 (0x40001CA8) /**< \brief (GCLK) Peripheral Clock Control 10 */
#define REG_GCLK_PCHCTRL11 (0x40001CAC) /**< \brief (GCLK) Peripheral Clock Control 11 */
#define REG_GCLK_PCHCTRL12 (0x40001CB0) /**< \brief (GCLK) Peripheral Clock Control 12 */
#define REG_GCLK_PCHCTRL13 (0x40001CB4) /**< \brief (GCLK) Peripheral Clock Control 13 */
#define REG_GCLK_PCHCTRL14 (0x40001CB8) /**< \brief (GCLK) Peripheral Clock Control 14 */
#define REG_GCLK_PCHCTRL15 (0x40001CBC) /**< \brief (GCLK) Peripheral Clock Control 15 */
#define REG_GCLK_PCHCTRL16 (0x40001CC0) /**< \brief (GCLK) Peripheral Clock Control 16 */
#define REG_GCLK_PCHCTRL17 (0x40001CC4) /**< \brief (GCLK) Peripheral Clock Control 17 */
#define REG_GCLK_PCHCTRL18 (0x40001CC8) /**< \brief (GCLK) Peripheral Clock Control 18 */
#define REG_GCLK_PCHCTRL19 (0x40001CCC) /**< \brief (GCLK) Peripheral Clock Control 19 */
#define REG_GCLK_PCHCTRL20 (0x40001CD0) /**< \brief (GCLK) Peripheral Clock Control 20 */
#define REG_GCLK_PCHCTRL21 (0x40001CD4) /**< \brief (GCLK) Peripheral Clock Control 21 */
#define REG_GCLK_PCHCTRL22 (0x40001CD8) /**< \brief (GCLK) Peripheral Clock Control 22 */
#define REG_GCLK_PCHCTRL23 (0x40001CDC) /**< \brief (GCLK) Peripheral Clock Control 23 */
#define REG_GCLK_PCHCTRL24 (0x40001CE0) /**< \brief (GCLK) Peripheral Clock Control 24 */
#define REG_GCLK_PCHCTRL25 (0x40001CE4) /**< \brief (GCLK) Peripheral Clock Control 25 */
#define REG_GCLK_PCHCTRL26 (0x40001CE8) /**< \brief (GCLK) Peripheral Clock Control 26 */
#define REG_GCLK_PCHCTRL27 (0x40001CEC) /**< \brief (GCLK) Peripheral Clock Control 27 */
#define REG_GCLK_PCHCTRL28 (0x40001CF0) /**< \brief (GCLK) Peripheral Clock Control 28 */
#define REG_GCLK_PCHCTRL29 (0x40001CF4) /**< \brief (GCLK) Peripheral Clock Control 29 */
#define REG_GCLK_PCHCTRL30 (0x40001CF8) /**< \brief (GCLK) Peripheral Clock Control 30 */
#define REG_GCLK_PCHCTRL31 (0x40001CFC) /**< \brief (GCLK) Peripheral Clock Control 31 */
#define REG_GCLK_PCHCTRL32 (0x40001D00) /**< \brief (GCLK) Peripheral Clock Control 32 */
#define REG_GCLK_PCHCTRL33 (0x40001D04) /**< \brief (GCLK) Peripheral Clock Control 33 */
#define REG_GCLK_PCHCTRL34 (0x40001D08) /**< \brief (GCLK) Peripheral Clock Control 34 */
#define REG_GCLK_PCHCTRL35 (0x40001D0C) /**< \brief (GCLK) Peripheral Clock Control 35 */
#define REG_GCLK_PCHCTRL36 (0x40001D10) /**< \brief (GCLK) Peripheral Clock Control 36 */
#define REG_GCLK_PCHCTRL37 (0x40001D14) /**< \brief (GCLK) Peripheral Clock Control 37 */
#define REG_GCLK_PCHCTRL38 (0x40001D18) /**< \brief (GCLK) Peripheral Clock Control 38 */
#define REG_GCLK_PCHCTRL39 (0x40001D1C) /**< \brief (GCLK) Peripheral Clock Control 39 */
#define REG_GCLK_PCHCTRL40 (0x40001D20) /**< \brief (GCLK) Peripheral Clock Control 40 */
#else
#define REG_GCLK_CTRLA (*(RwReg8 *)0x40001C00UL) /**< \brief (GCLK) Control */
#define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001C04UL) /**< \brief (GCLK) Synchronization Busy */
#define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001C20UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */
#define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001C24UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */
#define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001C28UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */
#define REG_GCLK_GENCTRL3 (*(RwReg *)0x40001C2CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */
#define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001C30UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */
#define REG_GCLK_GENCTRL5 (*(RwReg *)0x40001C34UL) /**< \brief (GCLK) Generic Clock Generator Control 5 */
#define REG_GCLK_GENCTRL6 (*(RwReg *)0x40001C38UL) /**< \brief (GCLK) Generic Clock Generator Control 6 */
#define REG_GCLK_GENCTRL7 (*(RwReg *)0x40001C3CUL) /**< \brief (GCLK) Generic Clock Generator Control 7 */
#define REG_GCLK_GENCTRL8 (*(RwReg *)0x40001C40UL) /**< \brief (GCLK) Generic Clock Generator Control 8 */
#define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001C80UL) /**< \brief (GCLK) Peripheral Clock Control 0 */
#define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001C84UL) /**< \brief (GCLK) Peripheral Clock Control 1 */
#define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001C88UL) /**< \brief (GCLK) Peripheral Clock Control 2 */
#define REG_GCLK_PCHCTRL3 (*(RwReg *)0x40001C8CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */
#define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001C90UL) /**< \brief (GCLK) Peripheral Clock Control 4 */
#define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001C94UL) /**< \brief (GCLK) Peripheral Clock Control 5 */
#define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001C98UL) /**< \brief (GCLK) Peripheral Clock Control 6 */
#define REG_GCLK_PCHCTRL7 (*(RwReg *)0x40001C9CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */
#define REG_GCLK_PCHCTRL8 (*(RwReg *)0x40001CA0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */
#define REG_GCLK_PCHCTRL9 (*(RwReg *)0x40001CA4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */
#define REG_GCLK_PCHCTRL10 (*(RwReg *)0x40001CA8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */
#define REG_GCLK_PCHCTRL11 (*(RwReg *)0x40001CACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */
#define REG_GCLK_PCHCTRL12 (*(RwReg *)0x40001CB0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */
#define REG_GCLK_PCHCTRL13 (*(RwReg *)0x40001CB4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */
#define REG_GCLK_PCHCTRL14 (*(RwReg *)0x40001CB8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */
#define REG_GCLK_PCHCTRL15 (*(RwReg *)0x40001CBCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */
#define REG_GCLK_PCHCTRL16 (*(RwReg *)0x40001CC0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */
#define REG_GCLK_PCHCTRL17 (*(RwReg *)0x40001CC4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */
#define REG_GCLK_PCHCTRL18 (*(RwReg *)0x40001CC8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */
#define REG_GCLK_PCHCTRL19 (*(RwReg *)0x40001CCCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */
#define REG_GCLK_PCHCTRL20 (*(RwReg *)0x40001CD0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */
#define REG_GCLK_PCHCTRL21 (*(RwReg *)0x40001CD4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */
#define REG_GCLK_PCHCTRL22 (*(RwReg *)0x40001CD8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */
#define REG_GCLK_PCHCTRL23 (*(RwReg *)0x40001CDCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */
#define REG_GCLK_PCHCTRL24 (*(RwReg *)0x40001CE0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */
#define REG_GCLK_PCHCTRL25 (*(RwReg *)0x40001CE4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */
#define REG_GCLK_PCHCTRL26 (*(RwReg *)0x40001CE8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */
#define REG_GCLK_PCHCTRL27 (*(RwReg *)0x40001CECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */
#define REG_GCLK_PCHCTRL28 (*(RwReg *)0x40001CF0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */
#define REG_GCLK_PCHCTRL29 (*(RwReg *)0x40001CF4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */
#define REG_GCLK_PCHCTRL30 (*(RwReg *)0x40001CF8UL) /**< \brief (GCLK) Peripheral Clock Control 30 */
#define REG_GCLK_PCHCTRL31 (*(RwReg *)0x40001CFCUL) /**< \brief (GCLK) Peripheral Clock Control 31 */
#define REG_GCLK_PCHCTRL32 (*(RwReg *)0x40001D00UL) /**< \brief (GCLK) Peripheral Clock Control 32 */
#define REG_GCLK_PCHCTRL33 (*(RwReg *)0x40001D04UL) /**< \brief (GCLK) Peripheral Clock Control 33 */
#define REG_GCLK_PCHCTRL34 (*(RwReg *)0x40001D08UL) /**< \brief (GCLK) Peripheral Clock Control 34 */
#define REG_GCLK_PCHCTRL35 (*(RwReg *)0x40001D0CUL) /**< \brief (GCLK) Peripheral Clock Control 35 */
#define REG_GCLK_PCHCTRL36 (*(RwReg *)0x40001D10UL) /**< \brief (GCLK) Peripheral Clock Control 36 */
#define REG_GCLK_PCHCTRL37 (*(RwReg *)0x40001D14UL) /**< \brief (GCLK) Peripheral Clock Control 37 */
#define REG_GCLK_PCHCTRL38 (*(RwReg *)0x40001D18UL) /**< \brief (GCLK) Peripheral Clock Control 38 */
#define REG_GCLK_PCHCTRL39 (*(RwReg *)0x40001D1CUL) /**< \brief (GCLK) Peripheral Clock Control 39 */
#define REG_GCLK_PCHCTRL40 (*(RwReg *)0x40001D20UL) /**< \brief (GCLK) Peripheral Clock Control 40 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_BITS 4
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
#define GCLK_GEN_SOURCE_NUM_MSB 7 // Number of Generic Clock Sources - 1
#define GCLK_NUM 41 // Number of Generic Clock Users
#define GCLK_SOURCE_BITS 3
#define GCLK_SOURCE_DPLL96M 7
#define GCLK_SOURCE_GCLKGEN1 2
#define GCLK_SOURCE_GCLKIN 1
#define GCLK_SOURCE_NUM 8 // Number of Generic Clock Sources
#define GCLK_SOURCE_OSCULP32K 3
#define GCLK_SOURCE_OSC32K 4
#define GCLK_SOURCE_OSC48M 6
#define GCLK_SOURCE_XOSC 0
#define GCLK_SOURCE_XOSC32K 5
#endif /* _SAMC21_GCLK_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for HMATRIXHS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_HMATRIXHS_INSTANCE_
#define _SAMC21_HMATRIXHS_INSTANCE_
/* ========== Register definition for HMATRIXHS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_HMATRIXHS_MCFG0 (0x4100A000) /**< \brief (HMATRIXHS) Master Configuration 0 */
#define REG_HMATRIXHS_MCFG1 (0x4100A004) /**< \brief (HMATRIXHS) Master Configuration 1 */
#define REG_HMATRIXHS_MCFG2 (0x4100A008) /**< \brief (HMATRIXHS) Master Configuration 2 */
#define REG_HMATRIXHS_MCFG3 (0x4100A00C) /**< \brief (HMATRIXHS) Master Configuration 3 */
#define REG_HMATRIXHS_MCFG4 (0x4100A010) /**< \brief (HMATRIXHS) Master Configuration 4 */
#define REG_HMATRIXHS_MCFG5 (0x4100A014) /**< \brief (HMATRIXHS) Master Configuration 5 */
#define REG_HMATRIXHS_MCFG6 (0x4100A018) /**< \brief (HMATRIXHS) Master Configuration 6 */
#define REG_HMATRIXHS_MCFG7 (0x4100A01C) /**< \brief (HMATRIXHS) Master Configuration 7 */
#define REG_HMATRIXHS_MCFG8 (0x4100A020) /**< \brief (HMATRIXHS) Master Configuration 8 */
#define REG_HMATRIXHS_MCFG9 (0x4100A024) /**< \brief (HMATRIXHS) Master Configuration 9 */
#define REG_HMATRIXHS_MCFG10 (0x4100A028) /**< \brief (HMATRIXHS) Master Configuration 10 */
#define REG_HMATRIXHS_MCFG11 (0x4100A02C) /**< \brief (HMATRIXHS) Master Configuration 11 */
#define REG_HMATRIXHS_MCFG12 (0x4100A030) /**< \brief (HMATRIXHS) Master Configuration 12 */
#define REG_HMATRIXHS_MCFG13 (0x4100A034) /**< \brief (HMATRIXHS) Master Configuration 13 */
#define REG_HMATRIXHS_MCFG14 (0x4100A038) /**< \brief (HMATRIXHS) Master Configuration 14 */
#define REG_HMATRIXHS_MCFG15 (0x4100A03C) /**< \brief (HMATRIXHS) Master Configuration 15 */
#define REG_HMATRIXHS_SCFG0 (0x4100A040) /**< \brief (HMATRIXHS) Slave Configuration 0 */
#define REG_HMATRIXHS_SCFG1 (0x4100A044) /**< \brief (HMATRIXHS) Slave Configuration 1 */
#define REG_HMATRIXHS_SCFG2 (0x4100A048) /**< \brief (HMATRIXHS) Slave Configuration 2 */
#define REG_HMATRIXHS_SCFG3 (0x4100A04C) /**< \brief (HMATRIXHS) Slave Configuration 3 */
#define REG_HMATRIXHS_SCFG4 (0x4100A050) /**< \brief (HMATRIXHS) Slave Configuration 4 */
#define REG_HMATRIXHS_SCFG5 (0x4100A054) /**< \brief (HMATRIXHS) Slave Configuration 5 */
#define REG_HMATRIXHS_SCFG6 (0x4100A058) /**< \brief (HMATRIXHS) Slave Configuration 6 */
#define REG_HMATRIXHS_SCFG7 (0x4100A05C) /**< \brief (HMATRIXHS) Slave Configuration 7 */
#define REG_HMATRIXHS_SCFG8 (0x4100A060) /**< \brief (HMATRIXHS) Slave Configuration 8 */
#define REG_HMATRIXHS_SCFG9 (0x4100A064) /**< \brief (HMATRIXHS) Slave Configuration 9 */
#define REG_HMATRIXHS_SCFG10 (0x4100A068) /**< \brief (HMATRIXHS) Slave Configuration 10 */
#define REG_HMATRIXHS_SCFG11 (0x4100A06C) /**< \brief (HMATRIXHS) Slave Configuration 11 */
#define REG_HMATRIXHS_SCFG12 (0x4100A070) /**< \brief (HMATRIXHS) Slave Configuration 12 */
#define REG_HMATRIXHS_SCFG13 (0x4100A074) /**< \brief (HMATRIXHS) Slave Configuration 13 */
#define REG_HMATRIXHS_SCFG14 (0x4100A078) /**< \brief (HMATRIXHS) Slave Configuration 14 */
#define REG_HMATRIXHS_SCFG15 (0x4100A07C) /**< \brief (HMATRIXHS) Slave Configuration 15 */
#define REG_HMATRIXHS_PRAS0 (0x4100A080) /**< \brief (HMATRIXHS) Priority A for Slave 0 */
#define REG_HMATRIXHS_PRBS0 (0x4100A084) /**< \brief (HMATRIXHS) Priority B for Slave 0 */
#define REG_HMATRIXHS_PRAS1 (0x4100A088) /**< \brief (HMATRIXHS) Priority A for Slave 1 */
#define REG_HMATRIXHS_PRBS1 (0x4100A08C) /**< \brief (HMATRIXHS) Priority B for Slave 1 */
#define REG_HMATRIXHS_PRAS2 (0x4100A090) /**< \brief (HMATRIXHS) Priority A for Slave 2 */
#define REG_HMATRIXHS_PRBS2 (0x4100A094) /**< \brief (HMATRIXHS) Priority B for Slave 2 */
#define REG_HMATRIXHS_PRAS3 (0x4100A098) /**< \brief (HMATRIXHS) Priority A for Slave 3 */
#define REG_HMATRIXHS_PRBS3 (0x4100A09C) /**< \brief (HMATRIXHS) Priority B for Slave 3 */
#define REG_HMATRIXHS_MRCR (0x4100A100) /**< \brief (HMATRIXHS) Master Remap Control */
#define REG_HMATRIXHS_SFR0 (0x4100A110) /**< \brief (HMATRIXHS) Special Function 0 */
#define REG_HMATRIXHS_SFR1 (0x4100A114) /**< \brief (HMATRIXHS) Special Function 1 */
#define REG_HMATRIXHS_SFR2 (0x4100A118) /**< \brief (HMATRIXHS) Special Function 2 */
#define REG_HMATRIXHS_SFR3 (0x4100A11C) /**< \brief (HMATRIXHS) Special Function 3 */
#define REG_HMATRIXHS_SFR4 (0x4100A120) /**< \brief (HMATRIXHS) Special Function 4 */
#define REG_HMATRIXHS_SFR5 (0x4100A124) /**< \brief (HMATRIXHS) Special Function 5 */
#define REG_HMATRIXHS_SFR6 (0x4100A128) /**< \brief (HMATRIXHS) Special Function 6 */
#define REG_HMATRIXHS_SFR7 (0x4100A12C) /**< \brief (HMATRIXHS) Special Function 7 */
#define REG_HMATRIXHS_SFR8 (0x4100A130) /**< \brief (HMATRIXHS) Special Function 8 */
#define REG_HMATRIXHS_SFR9 (0x4100A134) /**< \brief (HMATRIXHS) Special Function 9 */
#define REG_HMATRIXHS_SFR10 (0x4100A138) /**< \brief (HMATRIXHS) Special Function 10 */
#define REG_HMATRIXHS_SFR11 (0x4100A13C) /**< \brief (HMATRIXHS) Special Function 11 */
#define REG_HMATRIXHS_SFR12 (0x4100A140) /**< \brief (HMATRIXHS) Special Function 12 */
#define REG_HMATRIXHS_SFR13 (0x4100A144) /**< \brief (HMATRIXHS) Special Function 13 */
#define REG_HMATRIXHS_SFR14 (0x4100A148) /**< \brief (HMATRIXHS) Special Function 14 */
#define REG_HMATRIXHS_SFR15 (0x4100A14C) /**< \brief (HMATRIXHS) Special Function 15 */
#else
#define REG_HMATRIXHS_MCFG0 (*(RwReg *)0x4100A000UL) /**< \brief (HMATRIXHS) Master Configuration 0 */
#define REG_HMATRIXHS_MCFG1 (*(RwReg *)0x4100A004UL) /**< \brief (HMATRIXHS) Master Configuration 1 */
#define REG_HMATRIXHS_MCFG2 (*(RwReg *)0x4100A008UL) /**< \brief (HMATRIXHS) Master Configuration 2 */
#define REG_HMATRIXHS_MCFG3 (*(RwReg *)0x4100A00CUL) /**< \brief (HMATRIXHS) Master Configuration 3 */
#define REG_HMATRIXHS_MCFG4 (*(RwReg *)0x4100A010UL) /**< \brief (HMATRIXHS) Master Configuration 4 */
#define REG_HMATRIXHS_MCFG5 (*(RwReg *)0x4100A014UL) /**< \brief (HMATRIXHS) Master Configuration 5 */
#define REG_HMATRIXHS_MCFG6 (*(RwReg *)0x4100A018UL) /**< \brief (HMATRIXHS) Master Configuration 6 */
#define REG_HMATRIXHS_MCFG7 (*(RwReg *)0x4100A01CUL) /**< \brief (HMATRIXHS) Master Configuration 7 */
#define REG_HMATRIXHS_MCFG8 (*(RwReg *)0x4100A020UL) /**< \brief (HMATRIXHS) Master Configuration 8 */
#define REG_HMATRIXHS_MCFG9 (*(RwReg *)0x4100A024UL) /**< \brief (HMATRIXHS) Master Configuration 9 */
#define REG_HMATRIXHS_MCFG10 (*(RwReg *)0x4100A028UL) /**< \brief (HMATRIXHS) Master Configuration 10 */
#define REG_HMATRIXHS_MCFG11 (*(RwReg *)0x4100A02CUL) /**< \brief (HMATRIXHS) Master Configuration 11 */
#define REG_HMATRIXHS_MCFG12 (*(RwReg *)0x4100A030UL) /**< \brief (HMATRIXHS) Master Configuration 12 */
#define REG_HMATRIXHS_MCFG13 (*(RwReg *)0x4100A034UL) /**< \brief (HMATRIXHS) Master Configuration 13 */
#define REG_HMATRIXHS_MCFG14 (*(RwReg *)0x4100A038UL) /**< \brief (HMATRIXHS) Master Configuration 14 */
#define REG_HMATRIXHS_MCFG15 (*(RwReg *)0x4100A03CUL) /**< \brief (HMATRIXHS) Master Configuration 15 */
#define REG_HMATRIXHS_SCFG0 (*(RwReg *)0x4100A040UL) /**< \brief (HMATRIXHS) Slave Configuration 0 */
#define REG_HMATRIXHS_SCFG1 (*(RwReg *)0x4100A044UL) /**< \brief (HMATRIXHS) Slave Configuration 1 */
#define REG_HMATRIXHS_SCFG2 (*(RwReg *)0x4100A048UL) /**< \brief (HMATRIXHS) Slave Configuration 2 */
#define REG_HMATRIXHS_SCFG3 (*(RwReg *)0x4100A04CUL) /**< \brief (HMATRIXHS) Slave Configuration 3 */
#define REG_HMATRIXHS_SCFG4 (*(RwReg *)0x4100A050UL) /**< \brief (HMATRIXHS) Slave Configuration 4 */
#define REG_HMATRIXHS_SCFG5 (*(RwReg *)0x4100A054UL) /**< \brief (HMATRIXHS) Slave Configuration 5 */
#define REG_HMATRIXHS_SCFG6 (*(RwReg *)0x4100A058UL) /**< \brief (HMATRIXHS) Slave Configuration 6 */
#define REG_HMATRIXHS_SCFG7 (*(RwReg *)0x4100A05CUL) /**< \brief (HMATRIXHS) Slave Configuration 7 */
#define REG_HMATRIXHS_SCFG8 (*(RwReg *)0x4100A060UL) /**< \brief (HMATRIXHS) Slave Configuration 8 */
#define REG_HMATRIXHS_SCFG9 (*(RwReg *)0x4100A064UL) /**< \brief (HMATRIXHS) Slave Configuration 9 */
#define REG_HMATRIXHS_SCFG10 (*(RwReg *)0x4100A068UL) /**< \brief (HMATRIXHS) Slave Configuration 10 */
#define REG_HMATRIXHS_SCFG11 (*(RwReg *)0x4100A06CUL) /**< \brief (HMATRIXHS) Slave Configuration 11 */
#define REG_HMATRIXHS_SCFG12 (*(RwReg *)0x4100A070UL) /**< \brief (HMATRIXHS) Slave Configuration 12 */
#define REG_HMATRIXHS_SCFG13 (*(RwReg *)0x4100A074UL) /**< \brief (HMATRIXHS) Slave Configuration 13 */
#define REG_HMATRIXHS_SCFG14 (*(RwReg *)0x4100A078UL) /**< \brief (HMATRIXHS) Slave Configuration 14 */
#define REG_HMATRIXHS_SCFG15 (*(RwReg *)0x4100A07CUL) /**< \brief (HMATRIXHS) Slave Configuration 15 */
#define REG_HMATRIXHS_PRAS0 (*(RwReg *)0x4100A080UL) /**< \brief (HMATRIXHS) Priority A for Slave 0 */
#define REG_HMATRIXHS_PRBS0 (*(RwReg *)0x4100A084UL) /**< \brief (HMATRIXHS) Priority B for Slave 0 */
#define REG_HMATRIXHS_PRAS1 (*(RwReg *)0x4100A088UL) /**< \brief (HMATRIXHS) Priority A for Slave 1 */
#define REG_HMATRIXHS_PRBS1 (*(RwReg *)0x4100A08CUL) /**< \brief (HMATRIXHS) Priority B for Slave 1 */
#define REG_HMATRIXHS_PRAS2 (*(RwReg *)0x4100A090UL) /**< \brief (HMATRIXHS) Priority A for Slave 2 */
#define REG_HMATRIXHS_PRBS2 (*(RwReg *)0x4100A094UL) /**< \brief (HMATRIXHS) Priority B for Slave 2 */
#define REG_HMATRIXHS_PRAS3 (*(RwReg *)0x4100A098UL) /**< \brief (HMATRIXHS) Priority A for Slave 3 */
#define REG_HMATRIXHS_PRBS3 (*(RwReg *)0x4100A09CUL) /**< \brief (HMATRIXHS) Priority B for Slave 3 */
#define REG_HMATRIXHS_MRCR (*(RwReg *)0x4100A100UL) /**< \brief (HMATRIXHS) Master Remap Control */
#define REG_HMATRIXHS_SFR0 (*(RwReg *)0x4100A110UL) /**< \brief (HMATRIXHS) Special Function 0 */
#define REG_HMATRIXHS_SFR1 (*(RwReg *)0x4100A114UL) /**< \brief (HMATRIXHS) Special Function 1 */
#define REG_HMATRIXHS_SFR2 (*(RwReg *)0x4100A118UL) /**< \brief (HMATRIXHS) Special Function 2 */
#define REG_HMATRIXHS_SFR3 (*(RwReg *)0x4100A11CUL) /**< \brief (HMATRIXHS) Special Function 3 */
#define REG_HMATRIXHS_SFR4 (*(RwReg *)0x4100A120UL) /**< \brief (HMATRIXHS) Special Function 4 */
#define REG_HMATRIXHS_SFR5 (*(RwReg *)0x4100A124UL) /**< \brief (HMATRIXHS) Special Function 5 */
#define REG_HMATRIXHS_SFR6 (*(RwReg *)0x4100A128UL) /**< \brief (HMATRIXHS) Special Function 6 */
#define REG_HMATRIXHS_SFR7 (*(RwReg *)0x4100A12CUL) /**< \brief (HMATRIXHS) Special Function 7 */
#define REG_HMATRIXHS_SFR8 (*(RwReg *)0x4100A130UL) /**< \brief (HMATRIXHS) Special Function 8 */
#define REG_HMATRIXHS_SFR9 (*(RwReg *)0x4100A134UL) /**< \brief (HMATRIXHS) Special Function 9 */
#define REG_HMATRIXHS_SFR10 (*(RwReg *)0x4100A138UL) /**< \brief (HMATRIXHS) Special Function 10 */
#define REG_HMATRIXHS_SFR11 (*(RwReg *)0x4100A13CUL) /**< \brief (HMATRIXHS) Special Function 11 */
#define REG_HMATRIXHS_SFR12 (*(RwReg *)0x4100A140UL) /**< \brief (HMATRIXHS) Special Function 12 */
#define REG_HMATRIXHS_SFR13 (*(RwReg *)0x4100A144UL) /**< \brief (HMATRIXHS) Special Function 13 */
#define REG_HMATRIXHS_SFR14 (*(RwReg *)0x4100A148UL) /**< \brief (HMATRIXHS) Special Function 14 */
#define REG_HMATRIXHS_SFR15 (*(RwReg *)0x4100A14CUL) /**< \brief (HMATRIXHS) Special Function 15 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for HMATRIXHS peripheral ========== */
#define HMATRIXHS_CLK_AHB_ID 4 // Index of AHB Clock in MCLK.AHBMASK register (MASK may be tied to 1 depending on chip integration)
#define HMATRIXHS_DEFINED
#endif /* _SAMC21_HMATRIXHS_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for MCLK
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_MCLK_INSTANCE_
#define _SAMC21_MCLK_INSTANCE_
/* ========== Register definition for MCLK peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MCLK_INTENCLR (0x40000801) /**< \brief (MCLK) Interrupt Enable Clear */
#define REG_MCLK_INTENSET (0x40000802) /**< \brief (MCLK) Interrupt Enable Set */
#define REG_MCLK_INTFLAG (0x40000803) /**< \brief (MCLK) Interrupt Flag Status and Clear */
#define REG_MCLK_CPUDIV (0x40000804) /**< \brief (MCLK) CPU Clock Division */
#define REG_MCLK_AHBMASK (0x40000810) /**< \brief (MCLK) AHB Mask */
#define REG_MCLK_APBAMASK (0x40000814) /**< \brief (MCLK) APBA Mask */
#define REG_MCLK_APBBMASK (0x40000818) /**< \brief (MCLK) APBB Mask */
#define REG_MCLK_APBCMASK (0x4000081C) /**< \brief (MCLK) APBC Mask */
#else
#define REG_MCLK_INTENCLR (*(RwReg8 *)0x40000801UL) /**< \brief (MCLK) Interrupt Enable Clear */
#define REG_MCLK_INTENSET (*(RwReg8 *)0x40000802UL) /**< \brief (MCLK) Interrupt Enable Set */
#define REG_MCLK_INTFLAG (*(RwReg8 *)0x40000803UL) /**< \brief (MCLK) Interrupt Flag Status and Clear */
#define REG_MCLK_CPUDIV (*(RwReg8 *)0x40000804UL) /**< \brief (MCLK) CPU Clock Division */
#define REG_MCLK_AHBMASK (*(RwReg *)0x40000810UL) /**< \brief (MCLK) AHB Mask */
#define REG_MCLK_APBAMASK (*(RwReg *)0x40000814UL) /**< \brief (MCLK) APBA Mask */
#define REG_MCLK_APBBMASK (*(RwReg *)0x40000818UL) /**< \brief (MCLK) APBB Mask */
#define REG_MCLK_APBCMASK (*(RwReg *)0x4000081CUL) /**< \brief (MCLK) APBC Mask */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for MCLK peripheral ========== */
#define MCLK_CTRLA_MCSEL_GCLK 1
#define MCLK_CTRLA_MCSEL_OSC8M 0
#define MCLK_MCLK_CLK_APB_NUM 3
#define MCLK_SYSTEM_CLOCK 4000000 // System Clock Frequency at Reset
#endif /* _SAMC21_MCLK_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for MTB
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_MTB_INSTANCE_
#define _SAMC21_MTB_INSTANCE_
/* ========== Register definition for MTB peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MTB_POSITION (0x41008000) /**< \brief (MTB) MTB Position */
#define REG_MTB_MASTER (0x41008004) /**< \brief (MTB) MTB Master */
#define REG_MTB_FLOW (0x41008008) /**< \brief (MTB) MTB Flow */
#define REG_MTB_BASE (0x4100800C) /**< \brief (MTB) MTB Base */
#define REG_MTB_ITCTRL (0x41008F00) /**< \brief (MTB) MTB Integration Mode Control */
#define REG_MTB_CLAIMSET (0x41008FA0) /**< \brief (MTB) MTB Claim Set */
#define REG_MTB_CLAIMCLR (0x41008FA4) /**< \brief (MTB) MTB Claim Clear */
#define REG_MTB_LOCKACCESS (0x41008FB0) /**< \brief (MTB) MTB Lock Access */
#define REG_MTB_LOCKSTATUS (0x41008FB4) /**< \brief (MTB) MTB Lock Status */
#define REG_MTB_AUTHSTATUS (0x41008FB8) /**< \brief (MTB) MTB Authentication Status */
#define REG_MTB_DEVARCH (0x41008FBC) /**< \brief (MTB) MTB Device Architecture */
#define REG_MTB_DEVID (0x41008FC8) /**< \brief (MTB) MTB Device Configuration */
#define REG_MTB_DEVTYPE (0x41008FCC) /**< \brief (MTB) MTB Device Type */
#define REG_MTB_PID4 (0x41008FD0) /**< \brief (MTB) Peripheral Identification 4 */
#define REG_MTB_PID5 (0x41008FD4) /**< \brief (MTB) Peripheral Identification 5 */
#define REG_MTB_PID6 (0x41008FD8) /**< \brief (MTB) Peripheral Identification 6 */
#define REG_MTB_PID7 (0x41008FDC) /**< \brief (MTB) Peripheral Identification 7 */
#define REG_MTB_PID0 (0x41008FE0) /**< \brief (MTB) Peripheral Identification 0 */
#define REG_MTB_PID1 (0x41008FE4) /**< \brief (MTB) Peripheral Identification 1 */
#define REG_MTB_PID2 (0x41008FE8) /**< \brief (MTB) Peripheral Identification 2 */
#define REG_MTB_PID3 (0x41008FEC) /**< \brief (MTB) Peripheral Identification 3 */
#define REG_MTB_CID0 (0x41008FF0) /**< \brief (MTB) Component Identification 0 */
#define REG_MTB_CID1 (0x41008FF4) /**< \brief (MTB) Component Identification 1 */
#define REG_MTB_CID2 (0x41008FF8) /**< \brief (MTB) Component Identification 2 */
#define REG_MTB_CID3 (0x41008FFC) /**< \brief (MTB) Component Identification 3 */
#else
#define REG_MTB_POSITION (*(RwReg *)0x41008000UL) /**< \brief (MTB) MTB Position */
#define REG_MTB_MASTER (*(RwReg *)0x41008004UL) /**< \brief (MTB) MTB Master */
#define REG_MTB_FLOW (*(RwReg *)0x41008008UL) /**< \brief (MTB) MTB Flow */
#define REG_MTB_BASE (*(RoReg *)0x4100800CUL) /**< \brief (MTB) MTB Base */
#define REG_MTB_ITCTRL (*(RwReg *)0x41008F00UL) /**< \brief (MTB) MTB Integration Mode Control */
#define REG_MTB_CLAIMSET (*(RwReg *)0x41008FA0UL) /**< \brief (MTB) MTB Claim Set */
#define REG_MTB_CLAIMCLR (*(RwReg *)0x41008FA4UL) /**< \brief (MTB) MTB Claim Clear */
#define REG_MTB_LOCKACCESS (*(RwReg *)0x41008FB0UL) /**< \brief (MTB) MTB Lock Access */
#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41008FB4UL) /**< \brief (MTB) MTB Lock Status */
#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41008FB8UL) /**< \brief (MTB) MTB Authentication Status */
#define REG_MTB_DEVARCH (*(RoReg *)0x41008FBCUL) /**< \brief (MTB) MTB Device Architecture */
#define REG_MTB_DEVID (*(RoReg *)0x41008FC8UL) /**< \brief (MTB) MTB Device Configuration */
#define REG_MTB_DEVTYPE (*(RoReg *)0x41008FCCUL) /**< \brief (MTB) MTB Device Type */
#define REG_MTB_PID4 (*(RoReg *)0x41008FD0UL) /**< \brief (MTB) Peripheral Identification 4 */
#define REG_MTB_PID5 (*(RoReg *)0x41008FD4UL) /**< \brief (MTB) Peripheral Identification 5 */
#define REG_MTB_PID6 (*(RoReg *)0x41008FD8UL) /**< \brief (MTB) Peripheral Identification 6 */
#define REG_MTB_PID7 (*(RoReg *)0x41008FDCUL) /**< \brief (MTB) Peripheral Identification 7 */
#define REG_MTB_PID0 (*(RoReg *)0x41008FE0UL) /**< \brief (MTB) Peripheral Identification 0 */
#define REG_MTB_PID1 (*(RoReg *)0x41008FE4UL) /**< \brief (MTB) Peripheral Identification 1 */
#define REG_MTB_PID2 (*(RoReg *)0x41008FE8UL) /**< \brief (MTB) Peripheral Identification 2 */
#define REG_MTB_PID3 (*(RoReg *)0x41008FECUL) /**< \brief (MTB) Peripheral Identification 3 */
#define REG_MTB_CID0 (*(RoReg *)0x41008FF0UL) /**< \brief (MTB) Component Identification 0 */
#define REG_MTB_CID1 (*(RoReg *)0x41008FF4UL) /**< \brief (MTB) Component Identification 1 */
#define REG_MTB_CID2 (*(RoReg *)0x41008FF8UL) /**< \brief (MTB) Component Identification 2 */
#define REG_MTB_CID3 (*(RoReg *)0x41008FFCUL) /**< \brief (MTB) Component Identification 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMC21_MTB_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for NVMCTRL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_NVMCTRL_INSTANCE_
#define _SAMC21_NVMCTRL_INSTANCE_
/* ========== Register definition for NVMCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */
#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */
#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
#define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */
#define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
#define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */
#define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */
#define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */
#define REG_NVMCTRL_PBLDATA0 (0x41004028) /**< \brief (NVMCTRL) Page Buffer Load Data 0 */
#define REG_NVMCTRL_PBLDATA1 (0x4100402C) /**< \brief (NVMCTRL) Page Buffer Load Data 1 */
#else
#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */
#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */
#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */
#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */
#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */
#define REG_NVMCTRL_PBLDATA0 (*(RoReg *)0x41004028UL) /**< \brief (NVMCTRL) Page Buffer Load Data 0 */
#define REG_NVMCTRL_PBLDATA1 (*(RoReg *)0x4100402CUL) /**< \brief (NVMCTRL) Page Buffer Load Data 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for NVMCTRL peripheral ========== */
#define NVMCTRL_AUX0_ADDRESS 0x00804000
#define NVMCTRL_AUX1_ADDRESS 0x00806000
#define NVMCTRL_AUX2_ADDRESS 0x00808000
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
#define NVMCTRL_CLK_AHB_DOMAIN // Clock domain of AHB clock
#define NVMCTRL_CLK_AHB_ID 5 // Index of AHB Clock in PM.AHBMASK register
#define NVMCTRL_CLK_AHB_ID_PICACHU 11 // Index of PICACHU AHB Clock
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0XC0000007FFFFFFFF
#define NVMCTRL_FLASH_SIZE 262144
#define NVMCTRL_GCLK_ID 39 // Index of Generic Clock for test
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
#define NVMCTRL_PAGE_HW 32
#define NVMCTRL_PAGE_SIZE 64
#define NVMCTRL_PAGE_W 16
#define NVMCTRL_PMSB 3
#define NVMCTRL_PSZ_BITS 6
#define NVMCTRL_ROW_PAGES 4
#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0XC01FFFFFFFFFFFFF
#define NVMCTRL_RWWEE_PAGES 128
#define NVMCTRL_RWW_EEPROM_ADDR 0x00400000 // Start address of the RWW EEPROM area
#endif /* _SAMC21_NVMCTRL_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for OSC32KCTRL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_OSC32KCTRL_INSTANCE_
#define _SAMC21_OSC32KCTRL_INSTANCE_
/* ========== Register definition for OSC32KCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_OSC32KCTRL_INTENCLR (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
#define REG_OSC32KCTRL_INTENSET (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
#define REG_OSC32KCTRL_INTFLAG (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
#define REG_OSC32KCTRL_STATUS (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */
#define REG_OSC32KCTRL_RTCCTRL (0x40001410) /**< \brief (OSC32KCTRL) Clock selection */
#define REG_OSC32KCTRL_XOSC32K (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define REG_OSC32KCTRL_CFDCTRL (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
#define REG_OSC32KCTRL_EVCTRL (0x40001417) /**< \brief (OSC32KCTRL) Event Control */
#define REG_OSC32KCTRL_OSC32K (0x40001418) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */
#define REG_OSC32KCTRL_OSCULP32K (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#else
#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */
#define REG_OSC32KCTRL_RTCCTRL (*(RwReg *)0x40001410UL) /**< \brief (OSC32KCTRL) Clock selection */
#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */
#define REG_OSC32KCTRL_OSC32K (*(RwReg *)0x40001418UL) /**< \brief (OSC32KCTRL) 32kHz Internal Oscillator (OSC32K) Control */
#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 6
#endif /* _SAMC21_OSC32KCTRL_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for OSCCTRL
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_OSCCTRL_INSTANCE_
#define _SAMC21_OSCCTRL_INSTANCE_
/* ========== Register definition for OSCCTRL peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_OSCCTRL_INTENCLR (0x40001000) /**< \brief (OSCCTRL) Interrupt Enable Clear */
#define REG_OSCCTRL_INTENSET (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Set */
#define REG_OSCCTRL_INTFLAG (0x40001008) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
#define REG_OSCCTRL_STATUS (0x4000100C) /**< \brief (OSCCTRL) Power and Clocks Status */
#define REG_OSCCTRL_XOSCCTRL (0x40001010) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
#define REG_OSCCTRL_CFDPRESC (0x40001012) /**< \brief (OSCCTRL) Clock Failure Detector Prescaler */
#define REG_OSCCTRL_EVCTRL (0x40001013) /**< \brief (OSCCTRL) Event Control */
#define REG_OSCCTRL_OSC48MCTRL (0x40001014) /**< \brief (OSCCTRL) 48MHz Internal Oscillator (OSC48M) Control */
#define REG_OSCCTRL_OSC48MDIV (0x40001015) /**< \brief (OSCCTRL) OSC48M Divider */
#define REG_OSCCTRL_OSC48MSTUP (0x40001016) /**< \brief (OSCCTRL) OSC48M Startup Time */
#define REG_OSCCTRL_OSC48MSYNCBUSY (0x40001018) /**< \brief (OSCCTRL) OSC48M Synchronization Busy */
#define REG_OSCCTRL_DPLLCTRLA (0x4000101C) /**< \brief (OSCCTRL) DPLL Control */
#define REG_OSCCTRL_DPLLRATIO (0x40001020) /**< \brief (OSCCTRL) DPLL Ratio Control */
#define REG_OSCCTRL_DPLLCTRLB (0x40001024) /**< \brief (OSCCTRL) Digital Core Configuration */
#define REG_OSCCTRL_DPLLPRESC (0x40001028) /**< \brief (OSCCTRL) DPLL Prescaler */
#define REG_OSCCTRL_DPLLSYNCBUSY (0x4000102C) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
#define REG_OSCCTRL_DPLLSTATUS (0x40001030) /**< \brief (OSCCTRL) DPLL Status */
#define REG_OSCCTRL_CAL48M (0x40001038) /**< \brief (OSCCTRL) 48MHz Oscillator Calibration */
#else
#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001000UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
#define REG_OSCCTRL_STATUS (*(RoReg *)0x4000100CUL) /**< \brief (OSCCTRL) Power and Clocks Status */
#define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40001010UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
#define REG_OSCCTRL_CFDPRESC (*(RwReg8 *)0x40001012UL) /**< \brief (OSCCTRL) Clock Failure Detector Prescaler */
#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001013UL) /**< \brief (OSCCTRL) Event Control */
#define REG_OSCCTRL_OSC48MCTRL (*(RwReg8 *)0x40001014UL) /**< \brief (OSCCTRL) 48MHz Internal Oscillator (OSC48M) Control */
#define REG_OSCCTRL_OSC48MDIV (*(RwReg8 *)0x40001015UL) /**< \brief (OSCCTRL) OSC48M Divider */
#define REG_OSCCTRL_OSC48MSTUP (*(RwReg8 *)0x40001016UL) /**< \brief (OSCCTRL) OSC48M Startup Time */
#define REG_OSCCTRL_OSC48MSYNCBUSY (*(RoReg *)0x40001018UL) /**< \brief (OSCCTRL) OSC48M Synchronization Busy */
#define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x4000101CUL) /**< \brief (OSCCTRL) DPLL Control */
#define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x40001020UL) /**< \brief (OSCCTRL) DPLL Ratio Control */
#define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40001024UL) /**< \brief (OSCCTRL) Digital Core Configuration */
#define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40001028UL) /**< \brief (OSCCTRL) DPLL Prescaler */
#define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x4000102CUL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
#define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x40001030UL) /**< \brief (OSCCTRL) DPLL Status */
#define REG_OSCCTRL_CAL48M (*(RwReg *)0x40001038UL) /**< \brief (OSCCTRL) 48MHz Oscillator Calibration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for OSCCTRL peripheral ========== */
#define OSCCTRL_GCLK_ID_FDPLL 0 // Index of Generic Clock for DPLL
#define OSCCTRL_GCLK_ID_FDPLL32K 1 // Index of Generic Clock for DPLL 32K
#define OSCCTRL_FDPLL_VERSION 0x211
#define OSCCTRL_OSC48M_VERSION 0x101
#define OSCCTRL_XOSC_VERSION 0x201
#endif /* _SAMC21_OSCCTRL_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PAC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PAC_INSTANCE_
#define _SAMC21_PAC_INSTANCE_
/* ========== Register definition for PAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PAC_WRCTRL (0x40000000) /**< \brief (PAC) Write control */
#define REG_PAC_EVCTRL (0x40000004) /**< \brief (PAC) Event control */
#define REG_PAC_INTENCLR (0x40000008) /**< \brief (PAC) Interrupt enable clear */
#define REG_PAC_INTENSET (0x40000009) /**< \brief (PAC) Interrupt enable set */
#define REG_PAC_INTFLAGAHB (0x40000010) /**< \brief (PAC) Bridge interrupt flag status */
#define REG_PAC_INTFLAGA (0x40000014) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
#define REG_PAC_INTFLAGB (0x40000018) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
#define REG_PAC_INTFLAGC (0x4000001C) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
#define REG_PAC_STATUSA (0x40000034) /**< \brief (PAC) Peripheral write protection status - Bridge A */
#define REG_PAC_STATUSB (0x40000038) /**< \brief (PAC) Peripheral write protection status - Bridge B */
#define REG_PAC_STATUSC (0x4000003C) /**< \brief (PAC) Peripheral write protection status - Bridge C */
#else
#define REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) /**< \brief (PAC) Write control */
#define REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) /**< \brief (PAC) Event control */
#define REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) /**< \brief (PAC) Interrupt enable clear */
#define REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) /**< \brief (PAC) Interrupt enable set */
#define REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) /**< \brief (PAC) Bridge interrupt flag status */
#define REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge A */
#define REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge B */
#define REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) /**< \brief (PAC) Peripheral interrupt flag status - Bridge C */
#define REG_PAC_STATUSA (*(RoReg *)0x40000034UL) /**< \brief (PAC) Peripheral write protection status - Bridge A */
#define REG_PAC_STATUSB (*(RoReg *)0x40000038UL) /**< \brief (PAC) Peripheral write protection status - Bridge B */
#define REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) /**< \brief (PAC) Peripheral write protection status - Bridge C */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PAC peripheral ========== */
#define PAC_CLK_AHB_DOMAIN // Clock domain of AHB clock
#define PAC_CLK_AHB_ID 10 // AHB clock index
#define PAC_HPB_NUM 3 // Number of bridges AHB/APB
#define PAC_INTFLAG_NUM 4 // Number of intflag registers
#endif /* _SAMC21_PAC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PM
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PM_INSTANCE_
#define _SAMC21_PM_INSTANCE_
/* ========== Register definition for PM peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PM_SLEEPCFG (0x40000401) /**< \brief (PM) Sleep Configuration */
#define REG_PM_STDBYCFG (0x40000408) /**< \brief (PM) Standby Configuration */
#else
#define REG_PM_SLEEPCFG (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Configuration */
#define REG_PM_STDBYCFG (*(RwReg16*)0x40000408UL) /**< \brief (PM) Standby Configuration */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PM peripheral ========== */
#define PM_BIAS_RAM_HS 1 // one if RAM HS can be back biased
#define PM_PD_NUM 0 // Number of switchable Power Domain
#endif /* _SAMC21_PM_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PORT
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PORT_INSTANCE_
#define _SAMC21_PORT_INSTANCE_
/* ========== Register definition for PORT peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PORT_DIR0 (0x41000000) /**< \brief (PORT) Data Direction 0 */
#define REG_PORT_DIRCLR0 (0x41000004) /**< \brief (PORT) Data Direction Clear 0 */
#define REG_PORT_DIRSET0 (0x41000008) /**< \brief (PORT) Data Direction Set 0 */
#define REG_PORT_DIRTGL0 (0x4100000C) /**< \brief (PORT) Data Direction Toggle 0 */
#define REG_PORT_OUT0 (0x41000010) /**< \brief (PORT) Data Output Value 0 */
#define REG_PORT_OUTCLR0 (0x41000014) /**< \brief (PORT) Data Output Value Clear 0 */
#define REG_PORT_OUTSET0 (0x41000018) /**< \brief (PORT) Data Output Value Set 0 */
#define REG_PORT_OUTTGL0 (0x4100001C) /**< \brief (PORT) Data Output Value Toggle 0 */
#define REG_PORT_IN0 (0x41000020) /**< \brief (PORT) Data Input Value 0 */
#define REG_PORT_CTRL0 (0x41000024) /**< \brief (PORT) Control 0 */
#define REG_PORT_WRCONFIG0 (0x41000028) /**< \brief (PORT) Write Configuration 0 */
#define REG_PORT_EVCTRL0 (0x4100002C) /**< \brief (PORT) Event Input Control 0 */
#define REG_PORT_PMUX0 (0x41000030) /**< \brief (PORT) Peripheral Multiplexing 0 */
#define REG_PORT_PINCFG0 (0x41000040) /**< \brief (PORT) Pin Configuration 0 */
#define REG_PORT_DIR1 (0x41000080) /**< \brief (PORT) Data Direction 1 */
#define REG_PORT_DIRCLR1 (0x41000084) /**< \brief (PORT) Data Direction Clear 1 */
#define REG_PORT_DIRSET1 (0x41000088) /**< \brief (PORT) Data Direction Set 1 */
#define REG_PORT_DIRTGL1 (0x4100008C) /**< \brief (PORT) Data Direction Toggle 1 */
#define REG_PORT_OUT1 (0x41000090) /**< \brief (PORT) Data Output Value 1 */
#define REG_PORT_OUTCLR1 (0x41000094) /**< \brief (PORT) Data Output Value Clear 1 */
#define REG_PORT_OUTSET1 (0x41000098) /**< \brief (PORT) Data Output Value Set 1 */
#define REG_PORT_OUTTGL1 (0x4100009C) /**< \brief (PORT) Data Output Value Toggle 1 */
#define REG_PORT_IN1 (0x410000A0) /**< \brief (PORT) Data Input Value 1 */
#define REG_PORT_CTRL1 (0x410000A4) /**< \brief (PORT) Control 1 */
#define REG_PORT_WRCONFIG1 (0x410000A8) /**< \brief (PORT) Write Configuration 1 */
#define REG_PORT_EVCTRL1 (0x410000AC) /**< \brief (PORT) Event Input Control 1 */
#define REG_PORT_PMUX1 (0x410000B0) /**< \brief (PORT) Peripheral Multiplexing 1 */
#define REG_PORT_PINCFG1 (0x410000C0) /**< \brief (PORT) Pin Configuration 1 */
#else
#define REG_PORT_DIR0 (*(RwReg *)0x41000000UL) /**< \brief (PORT) Data Direction 0 */
#define REG_PORT_DIRCLR0 (*(RwReg *)0x41000004UL) /**< \brief (PORT) Data Direction Clear 0 */
#define REG_PORT_DIRSET0 (*(RwReg *)0x41000008UL) /**< \brief (PORT) Data Direction Set 0 */
#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100000CUL) /**< \brief (PORT) Data Direction Toggle 0 */
#define REG_PORT_OUT0 (*(RwReg *)0x41000010UL) /**< \brief (PORT) Data Output Value 0 */
#define REG_PORT_OUTCLR0 (*(RwReg *)0x41000014UL) /**< \brief (PORT) Data Output Value Clear 0 */
#define REG_PORT_OUTSET0 (*(RwReg *)0x41000018UL) /**< \brief (PORT) Data Output Value Set 0 */
#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100001CUL) /**< \brief (PORT) Data Output Value Toggle 0 */
#define REG_PORT_IN0 (*(RoReg *)0x41000020UL) /**< \brief (PORT) Data Input Value 0 */
#define REG_PORT_CTRL0 (*(RwReg *)0x41000024UL) /**< \brief (PORT) Control 0 */
#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41000028UL) /**< \brief (PORT) Write Configuration 0 */
#define REG_PORT_EVCTRL0 (*(RwReg *)0x4100002CUL) /**< \brief (PORT) Event Input Control 0 */
#define REG_PORT_PMUX0 (*(RwReg8 *)0x41000030UL) /**< \brief (PORT) Peripheral Multiplexing 0 */
#define REG_PORT_PINCFG0 (*(RwReg8 *)0x41000040UL) /**< \brief (PORT) Pin Configuration 0 */
#define REG_PORT_DIR1 (*(RwReg *)0x41000080UL) /**< \brief (PORT) Data Direction 1 */
#define REG_PORT_DIRCLR1 (*(RwReg *)0x41000084UL) /**< \brief (PORT) Data Direction Clear 1 */
#define REG_PORT_DIRSET1 (*(RwReg *)0x41000088UL) /**< \brief (PORT) Data Direction Set 1 */
#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100008CUL) /**< \brief (PORT) Data Direction Toggle 1 */
#define REG_PORT_OUT1 (*(RwReg *)0x41000090UL) /**< \brief (PORT) Data Output Value 1 */
#define REG_PORT_OUTCLR1 (*(RwReg *)0x41000094UL) /**< \brief (PORT) Data Output Value Clear 1 */
#define REG_PORT_OUTSET1 (*(RwReg *)0x41000098UL) /**< \brief (PORT) Data Output Value Set 1 */
#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100009CUL) /**< \brief (PORT) Data Output Value Toggle 1 */
#define REG_PORT_IN1 (*(RoReg *)0x410000A0UL) /**< \brief (PORT) Data Input Value 1 */
#define REG_PORT_CTRL1 (*(RwReg *)0x410000A4UL) /**< \brief (PORT) Control 1 */
#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410000A8UL) /**< \brief (PORT) Write Configuration 1 */
#define REG_PORT_EVCTRL1 (*(RwReg *)0x410000ACUL) /**< \brief (PORT) Event Input Control 1 */
#define REG_PORT_PMUX1 (*(RwReg8 *)0x410000B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */
#define REG_PORT_PINCFG1 (*(RwReg8 *)0x410000C0UL) /**< \brief (PORT) Pin Configuration 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PORT peripheral ========== */
#define PORT_BITS 64
#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_DRVSTR 1 // DRVSTR supported
#define PORT_DRVSTR_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_DRVSTR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_EVENT_IMPLEMENTED { 0xCBFFFFFF, 0xC0C3FFFF }
#define PORT_EV_NUM 4
#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_INEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_ODRAIN 0 // ODRAIN supported
#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000 }
#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000 }
#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F }
#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000 }
#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F }
#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_PMUXBIT3_IMPLEMENTED { 0xC3CF0FF0, 0x00C3CFC7 }
#define PORT_PMUXEN_DEFAULT_VAL { 0x40000000, 0x00000000 }
#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF }
#define PORT_SLEWLIM 0 // SLEWLIM supported
#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000 }
#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000 }
#endif /* _SAMC21_PORT_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for PTC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_PTC_INSTANCE_
#define _SAMC21_PTC_INSTANCE_
/* ========== Instance parameters for PTC peripheral ========== */
#define PTC_DMAC_ID_EOC 46 // Index of DMA EOC trigger
#define PTC_DMAC_ID_SEQ 48 // Index of DMA SEQ trigger
#define PTC_DMAC_ID_WCOMP 47 // Index of DMA WCOMP trigger
#define PTC_GCLK_ID 37 // Index of Generic Clock
#define PTC_X_LINES_NUM 16 // Number of X lines
#define PTC_Y_LINES_NUM 32 // Number of Y lines
#endif /* _SAMC21_PTC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for RSTC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_RSTC_INSTANCE_
#define _SAMC21_RSTC_INSTANCE_
/* ========== Register definition for RSTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RSTC_RCAUSE (0x40000C00) /**< \brief (RSTC) Reset Cause */
#else
#define REG_RSTC_RCAUSE (*(RoReg8 *)0x40000C00UL) /**< \brief (RSTC) Reset Cause */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RSTC peripheral ========== */
#define RSTC_NUMBER_OF_EXTWAKE 0 // number of external wakeup line
#endif /* _SAMC21_RSTC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for RTC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_RTC_INSTANCE_
#define _SAMC21_RTC_INSTANCE_
/* ========== Register definition for RTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RTC_DBGCTRL (0x4000240E) /**< \brief (RTC) Debug Control */
#define REG_RTC_FREQCORR (0x40002414) /**< \brief (RTC) Frequency Correction */
#define REG_RTC_MODE0_CTRLA (0x40002400) /**< \brief (RTC) MODE0 Control A */
#define REG_RTC_MODE0_EVCTRL (0x40002404) /**< \brief (RTC) MODE0 Event Control */
#define REG_RTC_MODE0_INTENCLR (0x40002408) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
#define REG_RTC_MODE0_INTENSET (0x4000240A) /**< \brief (RTC) MODE0 Interrupt Enable Set */
#define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
#define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE0 Synchronization Busy Status */
#define REG_RTC_MODE0_COUNT (0x40002418) /**< \brief (RTC) MODE0 Counter Value */
#define REG_RTC_MODE0_COMP0 (0x40002420) /**< \brief (RTC) MODE0 Compare 0 Value */
#define REG_RTC_MODE1_CTRLA (0x40002400) /**< \brief (RTC) MODE1 Control A */
#define REG_RTC_MODE1_EVCTRL (0x40002404) /**< \brief (RTC) MODE1 Event Control */
#define REG_RTC_MODE1_INTENCLR (0x40002408) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
#define REG_RTC_MODE1_INTENSET (0x4000240A) /**< \brief (RTC) MODE1 Interrupt Enable Set */
#define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
#define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE1 Synchronization Busy Status */
#define REG_RTC_MODE1_COUNT (0x40002418) /**< \brief (RTC) MODE1 Counter Value */
#define REG_RTC_MODE1_PER (0x4000241C) /**< \brief (RTC) MODE1 Counter Period */
#define REG_RTC_MODE1_COMP0 (0x40002420) /**< \brief (RTC) MODE1 Compare 0 Value */
#define REG_RTC_MODE1_COMP1 (0x40002422) /**< \brief (RTC) MODE1 Compare 1 Value */
#define REG_RTC_MODE2_CTRLA (0x40002400) /**< \brief (RTC) MODE2 Control A */
#define REG_RTC_MODE2_EVCTRL (0x40002404) /**< \brief (RTC) MODE2 Event Control */
#define REG_RTC_MODE2_INTENCLR (0x40002408) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
#define REG_RTC_MODE2_INTENSET (0x4000240A) /**< \brief (RTC) MODE2 Interrupt Enable Set */
#define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
#define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< \brief (RTC) MODE2 Synchronization Busy Status */
#define REG_RTC_MODE2_CLOCK (0x40002418) /**< \brief (RTC) MODE2 Clock Value */
#define REG_RTC_MODE2_ALARM_ALARM0 (0x40002420) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
#define REG_RTC_MODE2_ALARM_MASK0 (0x40002424) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
#else
#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) /**< \brief (RTC) Debug Control */
#define REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) /**< \brief (RTC) Frequency Correction */
#define REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE0 Control A */
#define REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE0 Event Control */
#define REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
#define REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
#define REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
#define REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE0 Synchronization Busy Status */
#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE0 Counter Value */
#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE0 Compare 0 Value */
#define REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE1 Control A */
#define REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE1 Event Control */
#define REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
#define REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
#define REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
#define REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE1 Synchronization Busy Status */
#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) /**< \brief (RTC) MODE1 Counter Value */
#define REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) /**< \brief (RTC) MODE1 Counter Period */
#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) /**< \brief (RTC) MODE1 Compare 0 Value */
#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) /**< \brief (RTC) MODE1 Compare 1 Value */
#define REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) /**< \brief (RTC) MODE2 Control A */
#define REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) /**< \brief (RTC) MODE2 Event Control */
#define REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
#define REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
#define REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
#define REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) /**< \brief (RTC) MODE2 Synchronization Busy Status */
#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) /**< \brief (RTC) MODE2 Clock Value */
#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x40002424UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for RTC peripheral ========== */
#define RTC_ALARM_NUM 1 // Number of Alarms
#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators
#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators
#define RTC_GPR_NUM 0 // Number of General-Purpose Registers
#define RTC_PER_NUM 8 // Number of Periodic Intervals
#endif /* _SAMC21_RTC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SDADC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SDADC_INSTANCE_
#define _SAMC21_SDADC_INSTANCE_
/* ========== Register definition for SDADC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SDADC_CTRLA (0x42004C00) /**< \brief (SDADC) Control A */
#define REG_SDADC_REFCTRL (0x42004C01) /**< \brief (SDADC) Reference Control */
#define REG_SDADC_CTRLB (0x42004C02) /**< \brief (SDADC) Control B */
#define REG_SDADC_EVCTRL (0x42004C04) /**< \brief (SDADC) Event Control */
#define REG_SDADC_INTENCLR (0x42004C05) /**< \brief (SDADC) Interrupt Enable Clear */
#define REG_SDADC_INTENSET (0x42004C06) /**< \brief (SDADC) Interrupt Enable Set */
#define REG_SDADC_INTFLAG (0x42004C07) /**< \brief (SDADC) Interrupt Flag Status and Clear */
#define REG_SDADC_SEQSTATUS (0x42004C08) /**< \brief (SDADC) Sequence Status */
#define REG_SDADC_INPUTCTRL (0x42004C09) /**< \brief (SDADC) Input Control */
#define REG_SDADC_CTRLC (0x42004C0A) /**< \brief (SDADC) Control C */
#define REG_SDADC_WINCTRL (0x42004C0B) /**< \brief (SDADC) Window Monitor Control */
#define REG_SDADC_WINLT (0x42004C0C) /**< \brief (SDADC) Window Monitor Lower Threshold */
#define REG_SDADC_WINUT (0x42004C10) /**< \brief (SDADC) Window Monitor Upper Threshold */
#define REG_SDADC_OFFSETCORR (0x42004C14) /**< \brief (SDADC) Offset Correction */
#define REG_SDADC_GAINCORR (0x42004C18) /**< \brief (SDADC) Gain Correction */
#define REG_SDADC_SHIFTCORR (0x42004C1A) /**< \brief (SDADC) Shift Correction */
#define REG_SDADC_SWTRIG (0x42004C1C) /**< \brief (SDADC) Software Trigger */
#define REG_SDADC_SYNCBUSY (0x42004C20) /**< \brief (SDADC) Synchronization Busy */
#define REG_SDADC_RESULT (0x42004C24) /**< \brief (SDADC) Result */
#define REG_SDADC_SEQCTRL (0x42004C28) /**< \brief (SDADC) Sequence Control */
#define REG_SDADC_ANACTRL (0x42004C2C) /**< \brief (SDADC) Analog Control */
#define REG_SDADC_DBGCTRL (0x42004C2E) /**< \brief (SDADC) Debug Control */
#else
#define REG_SDADC_CTRLA (*(RwReg8 *)0x42004C00UL) /**< \brief (SDADC) Control A */
#define REG_SDADC_REFCTRL (*(RwReg8 *)0x42004C01UL) /**< \brief (SDADC) Reference Control */
#define REG_SDADC_CTRLB (*(RwReg16*)0x42004C02UL) /**< \brief (SDADC) Control B */
#define REG_SDADC_EVCTRL (*(RwReg8 *)0x42004C04UL) /**< \brief (SDADC) Event Control */
#define REG_SDADC_INTENCLR (*(RwReg8 *)0x42004C05UL) /**< \brief (SDADC) Interrupt Enable Clear */
#define REG_SDADC_INTENSET (*(RwReg8 *)0x42004C06UL) /**< \brief (SDADC) Interrupt Enable Set */
#define REG_SDADC_INTFLAG (*(RwReg8 *)0x42004C07UL) /**< \brief (SDADC) Interrupt Flag Status and Clear */
#define REG_SDADC_SEQSTATUS (*(RoReg8 *)0x42004C08UL) /**< \brief (SDADC) Sequence Status */
#define REG_SDADC_INPUTCTRL (*(RwReg8 *)0x42004C09UL) /**< \brief (SDADC) Input Control */
#define REG_SDADC_CTRLC (*(RwReg8 *)0x42004C0AUL) /**< \brief (SDADC) Control C */
#define REG_SDADC_WINCTRL (*(RwReg8 *)0x42004C0BUL) /**< \brief (SDADC) Window Monitor Control */
#define REG_SDADC_WINLT (*(RwReg *)0x42004C0CUL) /**< \brief (SDADC) Window Monitor Lower Threshold */
#define REG_SDADC_WINUT (*(RwReg *)0x42004C10UL) /**< \brief (SDADC) Window Monitor Upper Threshold */
#define REG_SDADC_OFFSETCORR (*(RwReg *)0x42004C14UL) /**< \brief (SDADC) Offset Correction */
#define REG_SDADC_GAINCORR (*(RwReg16*)0x42004C18UL) /**< \brief (SDADC) Gain Correction */
#define REG_SDADC_SHIFTCORR (*(RwReg8 *)0x42004C1AUL) /**< \brief (SDADC) Shift Correction */
#define REG_SDADC_SWTRIG (*(RwReg8 *)0x42004C1CUL) /**< \brief (SDADC) Software Trigger */
#define REG_SDADC_SYNCBUSY (*(RoReg *)0x42004C20UL) /**< \brief (SDADC) Synchronization Busy */
#define REG_SDADC_RESULT (*(RoReg *)0x42004C24UL) /**< \brief (SDADC) Result */
#define REG_SDADC_SEQCTRL (*(RwReg8 *)0x42004C28UL) /**< \brief (SDADC) Sequence Control */
#define REG_SDADC_ANACTRL (*(RwReg8 *)0x42004C2CUL) /**< \brief (SDADC) Analog Control */
#define REG_SDADC_DBGCTRL (*(RwReg8 *)0x42004C2EUL) /**< \brief (SDADC) Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SDADC peripheral ========== */
#define SDADC_DMAC_ID_RESRDY 44 // Index of DMA RESRDY trigger
#define SDADC_EXT_CHANNELS 3 // Number of external channels
#define SDADC_GCLK_ID 35 // Index of generic clock
#endif /* _SAMC21_SDADC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SERCOM0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM0_INSTANCE_
#define _SAMC21_SERCOM0_INSTANCE_
/* ========== Register definition for SERCOM0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM0_I2CM_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CM Control A */
#define REG_SERCOM0_I2CM_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CM Control B */
#define REG_SERCOM0_I2CM_BAUD (0x4200040C) /**< \brief (SERCOM0) I2CM Baud Rate */
#define REG_SERCOM0_I2CM_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
#define REG_SERCOM0_I2CM_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
#define REG_SERCOM0_I2CM_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CM_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CM Status */
#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CM Synchronization Busy */
#define REG_SERCOM0_I2CM_ADDR (0x42000424) /**< \brief (SERCOM0) I2CM Address */
#define REG_SERCOM0_I2CM_DATA (0x42000428) /**< \brief (SERCOM0) I2CM Data */
#define REG_SERCOM0_I2CM_DBGCTRL (0x42000430) /**< \brief (SERCOM0) I2CM Debug Control */
#define REG_SERCOM0_I2CS_CTRLA (0x42000400) /**< \brief (SERCOM0) I2CS Control A */
#define REG_SERCOM0_I2CS_CTRLB (0x42000404) /**< \brief (SERCOM0) I2CS Control B */
#define REG_SERCOM0_I2CS_INTENCLR (0x42000414) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
#define REG_SERCOM0_I2CS_INTENSET (0x42000416) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
#define REG_SERCOM0_I2CS_INTFLAG (0x42000418) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CS_STATUS (0x4200041A) /**< \brief (SERCOM0) I2CS Status */
#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) I2CS Synchronization Busy */
#define REG_SERCOM0_I2CS_ADDR (0x42000424) /**< \brief (SERCOM0) I2CS Address */
#define REG_SERCOM0_I2CS_DATA (0x42000428) /**< \brief (SERCOM0) I2CS Data */
#define REG_SERCOM0_SPI_CTRLA (0x42000400) /**< \brief (SERCOM0) SPI Control A */
#define REG_SERCOM0_SPI_CTRLB (0x42000404) /**< \brief (SERCOM0) SPI Control B */
#define REG_SERCOM0_SPI_BAUD (0x4200040C) /**< \brief (SERCOM0) SPI Baud Rate */
#define REG_SERCOM0_SPI_INTENCLR (0x42000414) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
#define REG_SERCOM0_SPI_INTENSET (0x42000416) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
#define REG_SERCOM0_SPI_INTFLAG (0x42000418) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM0_SPI_STATUS (0x4200041A) /**< \brief (SERCOM0) SPI Status */
#define REG_SERCOM0_SPI_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) SPI Synchronization Busy */
#define REG_SERCOM0_SPI_ADDR (0x42000424) /**< \brief (SERCOM0) SPI Address */
#define REG_SERCOM0_SPI_DATA (0x42000428) /**< \brief (SERCOM0) SPI Data */
#define REG_SERCOM0_SPI_DBGCTRL (0x42000430) /**< \brief (SERCOM0) SPI Debug Control */
#define REG_SERCOM0_USART_CTRLA (0x42000400) /**< \brief (SERCOM0) USART Control A */
#define REG_SERCOM0_USART_CTRLB (0x42000404) /**< \brief (SERCOM0) USART Control B */
#define REG_SERCOM0_USART_CTRLC (0x42000408) /**< \brief (SERCOM0) USART Control C */
#define REG_SERCOM0_USART_BAUD (0x4200040C) /**< \brief (SERCOM0) USART Baud Rate */
#define REG_SERCOM0_USART_RXPL (0x4200040E) /**< \brief (SERCOM0) USART Receive Pulse Length */
#define REG_SERCOM0_USART_INTENCLR (0x42000414) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
#define REG_SERCOM0_USART_INTENSET (0x42000416) /**< \brief (SERCOM0) USART Interrupt Enable Set */
#define REG_SERCOM0_USART_INTFLAG (0x42000418) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
#define REG_SERCOM0_USART_STATUS (0x4200041A) /**< \brief (SERCOM0) USART Status */
#define REG_SERCOM0_USART_SYNCBUSY (0x4200041C) /**< \brief (SERCOM0) USART Synchronization Busy */
#define REG_SERCOM0_USART_DATA (0x42000428) /**< \brief (SERCOM0) USART Data */
#define REG_SERCOM0_USART_DBGCTRL (0x42000430) /**< \brief (SERCOM0) USART Debug Control */
#else
#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CM Control A */
#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CM Control B */
#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200040CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CM Status */
#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CM Synchronization Busy */
#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CM Address */
#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CM Data */
#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) I2CM Debug Control */
#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) I2CS Control A */
#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) I2CS Control B */
#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) I2CS Status */
#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) I2CS Synchronization Busy */
#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) I2CS Address */
#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000428UL) /**< \brief (SERCOM0) I2CS Data */
#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) SPI Control A */
#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) SPI Control B */
#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200040CUL) /**< \brief (SERCOM0) SPI Baud Rate */
#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) SPI Status */
#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) SPI Synchronization Busy */
#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000424UL) /**< \brief (SERCOM0) SPI Address */
#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000428UL) /**< \brief (SERCOM0) SPI Data */
#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) SPI Debug Control */
#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000400UL) /**< \brief (SERCOM0) USART Control A */
#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000404UL) /**< \brief (SERCOM0) USART Control B */
#define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x42000408UL) /**< \brief (SERCOM0) USART Control C */
#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200040CUL) /**< \brief (SERCOM0) USART Baud Rate */
#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200040EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000414UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000416UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000418UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200041AUL) /**< \brief (SERCOM0) USART Status */
#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200041CUL) /**< \brief (SERCOM0) USART Synchronization Busy */
#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000428UL) /**< \brief (SERCOM0) USART Data */
#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000430UL) /**< \brief (SERCOM0) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM0 peripheral ========== */
#define SERCOM0_DMAC_ID_RX 2 // Index of DMA RX trigger
#define SERCOM0_DMAC_ID_TX 3 // Index of DMA TX trigger
#define SERCOM0_GCLK_ID_CORE 19
#define SERCOM0_GCLK_ID_SLOW 18
#define SERCOM0_INT_MSB 6
#define SERCOM0_PMSB 3
#endif /* _SAMC21_SERCOM0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SERCOM1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM1_INSTANCE_
#define _SAMC21_SERCOM1_INSTANCE_
/* ========== Register definition for SERCOM1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM1_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CM Control A */
#define REG_SERCOM1_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CM Control B */
#define REG_SERCOM1_I2CM_BAUD (0x4200080C) /**< \brief (SERCOM1) I2CM Baud Rate */
#define REG_SERCOM1_I2CM_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
#define REG_SERCOM1_I2CM_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
#define REG_SERCOM1_I2CM_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CM_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CM Status */
#define REG_SERCOM1_I2CM_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CM Synchronization Busy */
#define REG_SERCOM1_I2CM_ADDR (0x42000824) /**< \brief (SERCOM1) I2CM Address */
#define REG_SERCOM1_I2CM_DATA (0x42000828) /**< \brief (SERCOM1) I2CM Data */
#define REG_SERCOM1_I2CM_DBGCTRL (0x42000830) /**< \brief (SERCOM1) I2CM Debug Control */
#define REG_SERCOM1_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM1) I2CS Control A */
#define REG_SERCOM1_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM1) I2CS Control B */
#define REG_SERCOM1_I2CS_INTENCLR (0x42000814) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
#define REG_SERCOM1_I2CS_INTENSET (0x42000816) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
#define REG_SERCOM1_I2CS_INTFLAG (0x42000818) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CS_STATUS (0x4200081A) /**< \brief (SERCOM1) I2CS Status */
#define REG_SERCOM1_I2CS_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) I2CS Synchronization Busy */
#define REG_SERCOM1_I2CS_ADDR (0x42000824) /**< \brief (SERCOM1) I2CS Address */
#define REG_SERCOM1_I2CS_DATA (0x42000828) /**< \brief (SERCOM1) I2CS Data */
#define REG_SERCOM1_SPI_CTRLA (0x42000800) /**< \brief (SERCOM1) SPI Control A */
#define REG_SERCOM1_SPI_CTRLB (0x42000804) /**< \brief (SERCOM1) SPI Control B */
#define REG_SERCOM1_SPI_BAUD (0x4200080C) /**< \brief (SERCOM1) SPI Baud Rate */
#define REG_SERCOM1_SPI_INTENCLR (0x42000814) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
#define REG_SERCOM1_SPI_INTENSET (0x42000816) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
#define REG_SERCOM1_SPI_INTFLAG (0x42000818) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM1_SPI_STATUS (0x4200081A) /**< \brief (SERCOM1) SPI Status */
#define REG_SERCOM1_SPI_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) SPI Synchronization Busy */
#define REG_SERCOM1_SPI_ADDR (0x42000824) /**< \brief (SERCOM1) SPI Address */
#define REG_SERCOM1_SPI_DATA (0x42000828) /**< \brief (SERCOM1) SPI Data */
#define REG_SERCOM1_SPI_DBGCTRL (0x42000830) /**< \brief (SERCOM1) SPI Debug Control */
#define REG_SERCOM1_USART_CTRLA (0x42000800) /**< \brief (SERCOM1) USART Control A */
#define REG_SERCOM1_USART_CTRLB (0x42000804) /**< \brief (SERCOM1) USART Control B */
#define REG_SERCOM1_USART_CTRLC (0x42000808) /**< \brief (SERCOM1) USART Control C */
#define REG_SERCOM1_USART_BAUD (0x4200080C) /**< \brief (SERCOM1) USART Baud Rate */
#define REG_SERCOM1_USART_RXPL (0x4200080E) /**< \brief (SERCOM1) USART Receive Pulse Length */
#define REG_SERCOM1_USART_INTENCLR (0x42000814) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
#define REG_SERCOM1_USART_INTENSET (0x42000816) /**< \brief (SERCOM1) USART Interrupt Enable Set */
#define REG_SERCOM1_USART_INTFLAG (0x42000818) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
#define REG_SERCOM1_USART_STATUS (0x4200081A) /**< \brief (SERCOM1) USART Status */
#define REG_SERCOM1_USART_SYNCBUSY (0x4200081C) /**< \brief (SERCOM1) USART Synchronization Busy */
#define REG_SERCOM1_USART_DATA (0x42000828) /**< \brief (SERCOM1) USART Data */
#define REG_SERCOM1_USART_DBGCTRL (0x42000830) /**< \brief (SERCOM1) USART Debug Control */
#else
#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CM Control A */
#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CM Control B */
#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4200080CUL) /**< \brief (SERCOM1) I2CM Baud Rate */
#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CM Status */
#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CM Synchronization Busy */
#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CM Address */
#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CM Data */
#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) I2CM Debug Control */
#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) I2CS Control A */
#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) I2CS Control B */
#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) I2CS Status */
#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) I2CS Synchronization Busy */
#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) I2CS Address */
#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM1) I2CS Data */
#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) SPI Control A */
#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) SPI Control B */
#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM1) SPI Baud Rate */
#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) SPI Status */
#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) SPI Synchronization Busy */
#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM1) SPI Address */
#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000828UL) /**< \brief (SERCOM1) SPI Data */
#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) SPI Debug Control */
#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM1) USART Control A */
#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM1) USART Control B */
#define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x42000808UL) /**< \brief (SERCOM1) USART Control C */
#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4200080CUL) /**< \brief (SERCOM1) USART Baud Rate */
#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */
#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */
#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM1) USART Status */
#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM1) USART Synchronization Busy */
#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000828UL) /**< \brief (SERCOM1) USART Data */
#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM1) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM1 peripheral ========== */
#define SERCOM1_DMAC_ID_RX 4 // Index of DMA RX trigger
#define SERCOM1_DMAC_ID_TX 5 // Index of DMA TX trigger
#define SERCOM1_GCLK_ID_CORE 20
#define SERCOM1_GCLK_ID_SLOW 18
#define SERCOM1_INT_MSB 6
#define SERCOM1_PMSB 3
#endif /* _SAMC21_SERCOM1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SERCOM2
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM2_INSTANCE_
#define _SAMC21_SERCOM2_INSTANCE_
/* ========== Register definition for SERCOM2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM2_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CM Control A */
#define REG_SERCOM2_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CM Control B */
#define REG_SERCOM2_I2CM_BAUD (0x42000C0C) /**< \brief (SERCOM2) I2CM Baud Rate */
#define REG_SERCOM2_I2CM_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
#define REG_SERCOM2_I2CM_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
#define REG_SERCOM2_I2CM_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CM_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CM Status */
#define REG_SERCOM2_I2CM_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CM Synchronization Busy */
#define REG_SERCOM2_I2CM_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CM Address */
#define REG_SERCOM2_I2CM_DATA (0x42000C28) /**< \brief (SERCOM2) I2CM Data */
#define REG_SERCOM2_I2CM_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) I2CM Debug Control */
#define REG_SERCOM2_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM2) I2CS Control A */
#define REG_SERCOM2_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM2) I2CS Control B */
#define REG_SERCOM2_I2CS_INTENCLR (0x42000C14) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
#define REG_SERCOM2_I2CS_INTENSET (0x42000C16) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
#define REG_SERCOM2_I2CS_INTFLAG (0x42000C18) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CS_STATUS (0x42000C1A) /**< \brief (SERCOM2) I2CS Status */
#define REG_SERCOM2_I2CS_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) I2CS Synchronization Busy */
#define REG_SERCOM2_I2CS_ADDR (0x42000C24) /**< \brief (SERCOM2) I2CS Address */
#define REG_SERCOM2_I2CS_DATA (0x42000C28) /**< \brief (SERCOM2) I2CS Data */
#define REG_SERCOM2_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM2) SPI Control A */
#define REG_SERCOM2_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM2) SPI Control B */
#define REG_SERCOM2_SPI_BAUD (0x42000C0C) /**< \brief (SERCOM2) SPI Baud Rate */
#define REG_SERCOM2_SPI_INTENCLR (0x42000C14) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
#define REG_SERCOM2_SPI_INTENSET (0x42000C16) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
#define REG_SERCOM2_SPI_INTFLAG (0x42000C18) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM2_SPI_STATUS (0x42000C1A) /**< \brief (SERCOM2) SPI Status */
#define REG_SERCOM2_SPI_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) SPI Synchronization Busy */
#define REG_SERCOM2_SPI_ADDR (0x42000C24) /**< \brief (SERCOM2) SPI Address */
#define REG_SERCOM2_SPI_DATA (0x42000C28) /**< \brief (SERCOM2) SPI Data */
#define REG_SERCOM2_SPI_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) SPI Debug Control */
#define REG_SERCOM2_USART_CTRLA (0x42000C00) /**< \brief (SERCOM2) USART Control A */
#define REG_SERCOM2_USART_CTRLB (0x42000C04) /**< \brief (SERCOM2) USART Control B */
#define REG_SERCOM2_USART_CTRLC (0x42000C08) /**< \brief (SERCOM2) USART Control C */
#define REG_SERCOM2_USART_BAUD (0x42000C0C) /**< \brief (SERCOM2) USART Baud Rate */
#define REG_SERCOM2_USART_RXPL (0x42000C0E) /**< \brief (SERCOM2) USART Receive Pulse Length */
#define REG_SERCOM2_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
#define REG_SERCOM2_USART_INTENSET (0x42000C16) /**< \brief (SERCOM2) USART Interrupt Enable Set */
#define REG_SERCOM2_USART_INTFLAG (0x42000C18) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
#define REG_SERCOM2_USART_STATUS (0x42000C1A) /**< \brief (SERCOM2) USART Status */
#define REG_SERCOM2_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM2) USART Synchronization Busy */
#define REG_SERCOM2_USART_DATA (0x42000C28) /**< \brief (SERCOM2) USART Data */
#define REG_SERCOM2_USART_DBGCTRL (0x42000C30) /**< \brief (SERCOM2) USART Debug Control */
#else
#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CM Control A */
#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CM Control B */
#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM2) I2CM Baud Rate */
#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CM Status */
#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CM Synchronization Busy */
#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CM Address */
#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CM Data */
#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) I2CM Debug Control */
#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) I2CS Control A */
#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) I2CS Control B */
#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) I2CS Status */
#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) I2CS Synchronization Busy */
#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) I2CS Address */
#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM2) I2CS Data */
#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) SPI Control A */
#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) SPI Control B */
#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM2) SPI Baud Rate */
#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) SPI Status */
#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) SPI Synchronization Busy */
#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM2) SPI Address */
#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42000C28UL) /**< \brief (SERCOM2) SPI Data */
#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) SPI Debug Control */
#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM2) USART Control A */
#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM2) USART Control B */
#define REG_SERCOM2_USART_CTRLC (*(RwReg *)0x42000C08UL) /**< \brief (SERCOM2) USART Control C */
#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM2) USART Baud Rate */
#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */
#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */
#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM2) USART Status */
#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM2) USART Synchronization Busy */
#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM2) USART Data */
#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM2) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM2 peripheral ========== */
#define SERCOM2_DMAC_ID_RX 6 // Index of DMA RX trigger
#define SERCOM2_DMAC_ID_TX 7 // Index of DMA TX trigger
#define SERCOM2_GCLK_ID_CORE 21
#define SERCOM2_GCLK_ID_SLOW 18
#define SERCOM2_INT_MSB 6
#define SERCOM2_PMSB 3
#endif /* _SAMC21_SERCOM2_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SERCOM3
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM3_INSTANCE_
#define _SAMC21_SERCOM3_INSTANCE_
/* ========== Register definition for SERCOM3 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM3_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CM Control A */
#define REG_SERCOM3_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CM Control B */
#define REG_SERCOM3_I2CM_BAUD (0x4200100C) /**< \brief (SERCOM3) I2CM Baud Rate */
#define REG_SERCOM3_I2CM_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
#define REG_SERCOM3_I2CM_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
#define REG_SERCOM3_I2CM_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CM_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CM Status */
#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CM Synchronization Busy */
#define REG_SERCOM3_I2CM_ADDR (0x42001024) /**< \brief (SERCOM3) I2CM Address */
#define REG_SERCOM3_I2CM_DATA (0x42001028) /**< \brief (SERCOM3) I2CM Data */
#define REG_SERCOM3_I2CM_DBGCTRL (0x42001030) /**< \brief (SERCOM3) I2CM Debug Control */
#define REG_SERCOM3_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM3) I2CS Control A */
#define REG_SERCOM3_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM3) I2CS Control B */
#define REG_SERCOM3_I2CS_INTENCLR (0x42001014) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
#define REG_SERCOM3_I2CS_INTENSET (0x42001016) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
#define REG_SERCOM3_I2CS_INTFLAG (0x42001018) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CS_STATUS (0x4200101A) /**< \brief (SERCOM3) I2CS Status */
#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) I2CS Synchronization Busy */
#define REG_SERCOM3_I2CS_ADDR (0x42001024) /**< \brief (SERCOM3) I2CS Address */
#define REG_SERCOM3_I2CS_DATA (0x42001028) /**< \brief (SERCOM3) I2CS Data */
#define REG_SERCOM3_SPI_CTRLA (0x42001000) /**< \brief (SERCOM3) SPI Control A */
#define REG_SERCOM3_SPI_CTRLB (0x42001004) /**< \brief (SERCOM3) SPI Control B */
#define REG_SERCOM3_SPI_BAUD (0x4200100C) /**< \brief (SERCOM3) SPI Baud Rate */
#define REG_SERCOM3_SPI_INTENCLR (0x42001014) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
#define REG_SERCOM3_SPI_INTENSET (0x42001016) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
#define REG_SERCOM3_SPI_INTFLAG (0x42001018) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM3_SPI_STATUS (0x4200101A) /**< \brief (SERCOM3) SPI Status */
#define REG_SERCOM3_SPI_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) SPI Synchronization Busy */
#define REG_SERCOM3_SPI_ADDR (0x42001024) /**< \brief (SERCOM3) SPI Address */
#define REG_SERCOM3_SPI_DATA (0x42001028) /**< \brief (SERCOM3) SPI Data */
#define REG_SERCOM3_SPI_DBGCTRL (0x42001030) /**< \brief (SERCOM3) SPI Debug Control */
#define REG_SERCOM3_USART_CTRLA (0x42001000) /**< \brief (SERCOM3) USART Control A */
#define REG_SERCOM3_USART_CTRLB (0x42001004) /**< \brief (SERCOM3) USART Control B */
#define REG_SERCOM3_USART_CTRLC (0x42001008) /**< \brief (SERCOM3) USART Control C */
#define REG_SERCOM3_USART_BAUD (0x4200100C) /**< \brief (SERCOM3) USART Baud Rate */
#define REG_SERCOM3_USART_RXPL (0x4200100E) /**< \brief (SERCOM3) USART Receive Pulse Length */
#define REG_SERCOM3_USART_INTENCLR (0x42001014) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
#define REG_SERCOM3_USART_INTENSET (0x42001016) /**< \brief (SERCOM3) USART Interrupt Enable Set */
#define REG_SERCOM3_USART_INTFLAG (0x42001018) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
#define REG_SERCOM3_USART_STATUS (0x4200101A) /**< \brief (SERCOM3) USART Status */
#define REG_SERCOM3_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM3) USART Synchronization Busy */
#define REG_SERCOM3_USART_DATA (0x42001028) /**< \brief (SERCOM3) USART Data */
#define REG_SERCOM3_USART_DBGCTRL (0x42001030) /**< \brief (SERCOM3) USART Debug Control */
#else
#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CM Control A */
#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CM Control B */
#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM3) I2CM Baud Rate */
#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CM Status */
#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CM Synchronization Busy */
#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CM Address */
#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CM Data */
#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) I2CM Debug Control */
#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) I2CS Control A */
#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) I2CS Control B */
#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) I2CS Status */
#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) I2CS Synchronization Busy */
#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) I2CS Address */
#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM3) I2CS Data */
#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) SPI Control A */
#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) SPI Control B */
#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM3) SPI Baud Rate */
#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) SPI Status */
#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) SPI Synchronization Busy */
#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM3) SPI Address */
#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001028UL) /**< \brief (SERCOM3) SPI Data */
#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) SPI Debug Control */
#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM3) USART Control A */
#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM3) USART Control B */
#define REG_SERCOM3_USART_CTRLC (*(RwReg *)0x42001008UL) /**< \brief (SERCOM3) USART Control C */
#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM3) USART Baud Rate */
#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */
#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */
#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM3) USART Status */
#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM3) USART Synchronization Busy */
#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM3) USART Data */
#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM3) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM3 peripheral ========== */
#define SERCOM3_DMAC_ID_RX 8 // Index of DMA RX trigger
#define SERCOM3_DMAC_ID_TX 9 // Index of DMA TX trigger
#define SERCOM3_GCLK_ID_CORE 22
#define SERCOM3_GCLK_ID_SLOW 18
#define SERCOM3_INT_MSB 6
#define SERCOM3_PMSB 3
#endif /* _SAMC21_SERCOM3_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SERCOM4
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM4_INSTANCE_
#define _SAMC21_SERCOM4_INSTANCE_
/* ========== Register definition for SERCOM4 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM4_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CM Control A */
#define REG_SERCOM4_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CM Control B */
#define REG_SERCOM4_I2CM_BAUD (0x4200140C) /**< \brief (SERCOM4) I2CM Baud Rate */
#define REG_SERCOM4_I2CM_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
#define REG_SERCOM4_I2CM_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
#define REG_SERCOM4_I2CM_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CM_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CM Status */
#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CM Synchronization Busy */
#define REG_SERCOM4_I2CM_ADDR (0x42001424) /**< \brief (SERCOM4) I2CM Address */
#define REG_SERCOM4_I2CM_DATA (0x42001428) /**< \brief (SERCOM4) I2CM Data */
#define REG_SERCOM4_I2CM_DBGCTRL (0x42001430) /**< \brief (SERCOM4) I2CM Debug Control */
#define REG_SERCOM4_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM4) I2CS Control A */
#define REG_SERCOM4_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM4) I2CS Control B */
#define REG_SERCOM4_I2CS_INTENCLR (0x42001414) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
#define REG_SERCOM4_I2CS_INTENSET (0x42001416) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
#define REG_SERCOM4_I2CS_INTFLAG (0x42001418) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CS_STATUS (0x4200141A) /**< \brief (SERCOM4) I2CS Status */
#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) I2CS Synchronization Busy */
#define REG_SERCOM4_I2CS_ADDR (0x42001424) /**< \brief (SERCOM4) I2CS Address */
#define REG_SERCOM4_I2CS_DATA (0x42001428) /**< \brief (SERCOM4) I2CS Data */
#define REG_SERCOM4_SPI_CTRLA (0x42001400) /**< \brief (SERCOM4) SPI Control A */
#define REG_SERCOM4_SPI_CTRLB (0x42001404) /**< \brief (SERCOM4) SPI Control B */
#define REG_SERCOM4_SPI_BAUD (0x4200140C) /**< \brief (SERCOM4) SPI Baud Rate */
#define REG_SERCOM4_SPI_INTENCLR (0x42001414) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
#define REG_SERCOM4_SPI_INTENSET (0x42001416) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
#define REG_SERCOM4_SPI_INTFLAG (0x42001418) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM4_SPI_STATUS (0x4200141A) /**< \brief (SERCOM4) SPI Status */
#define REG_SERCOM4_SPI_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) SPI Synchronization Busy */
#define REG_SERCOM4_SPI_ADDR (0x42001424) /**< \brief (SERCOM4) SPI Address */
#define REG_SERCOM4_SPI_DATA (0x42001428) /**< \brief (SERCOM4) SPI Data */
#define REG_SERCOM4_SPI_DBGCTRL (0x42001430) /**< \brief (SERCOM4) SPI Debug Control */
#define REG_SERCOM4_USART_CTRLA (0x42001400) /**< \brief (SERCOM4) USART Control A */
#define REG_SERCOM4_USART_CTRLB (0x42001404) /**< \brief (SERCOM4) USART Control B */
#define REG_SERCOM4_USART_CTRLC (0x42001408) /**< \brief (SERCOM4) USART Control C */
#define REG_SERCOM4_USART_BAUD (0x4200140C) /**< \brief (SERCOM4) USART Baud Rate */
#define REG_SERCOM4_USART_RXPL (0x4200140E) /**< \brief (SERCOM4) USART Receive Pulse Length */
#define REG_SERCOM4_USART_INTENCLR (0x42001414) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
#define REG_SERCOM4_USART_INTENSET (0x42001416) /**< \brief (SERCOM4) USART Interrupt Enable Set */
#define REG_SERCOM4_USART_INTFLAG (0x42001418) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
#define REG_SERCOM4_USART_STATUS (0x4200141A) /**< \brief (SERCOM4) USART Status */
#define REG_SERCOM4_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM4) USART Synchronization Busy */
#define REG_SERCOM4_USART_DATA (0x42001428) /**< \brief (SERCOM4) USART Data */
#define REG_SERCOM4_USART_DBGCTRL (0x42001430) /**< \brief (SERCOM4) USART Debug Control */
#else
#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CM Control A */
#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CM Control B */
#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200140CUL) /**< \brief (SERCOM4) I2CM Baud Rate */
#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CM Status */
#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CM Synchronization Busy */
#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CM Address */
#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CM Data */
#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) I2CM Debug Control */
#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) I2CS Control A */
#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) I2CS Control B */
#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) I2CS Status */
#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) I2CS Synchronization Busy */
#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) I2CS Address */
#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM4) I2CS Data */
#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) SPI Control A */
#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) SPI Control B */
#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM4) SPI Baud Rate */
#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) SPI Status */
#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) SPI Synchronization Busy */
#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM4) SPI Address */
#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001428UL) /**< \brief (SERCOM4) SPI Data */
#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) SPI Debug Control */
#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM4) USART Control A */
#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM4) USART Control B */
#define REG_SERCOM4_USART_CTRLC (*(RwReg *)0x42001408UL) /**< \brief (SERCOM4) USART Control C */
#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM4) USART Baud Rate */
#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */
#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */
#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM4) USART Status */
#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM4) USART Synchronization Busy */
#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM4) USART Data */
#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM4) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM4 peripheral ========== */
#define SERCOM4_DMAC_ID_RX 10 // Index of DMA RX trigger
#define SERCOM4_DMAC_ID_TX 11 // Index of DMA TX trigger
#define SERCOM4_GCLK_ID_CORE 23
#define SERCOM4_GCLK_ID_SLOW 18
#define SERCOM4_INT_MSB 6
#define SERCOM4_PMSB 3
#endif /* _SAMC21_SERCOM4_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SERCOM5
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SERCOM5_INSTANCE_
#define _SAMC21_SERCOM5_INSTANCE_
/* ========== Register definition for SERCOM5 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SERCOM5_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CM Control A */
#define REG_SERCOM5_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CM Control B */
#define REG_SERCOM5_I2CM_BAUD (0x4200180C) /**< \brief (SERCOM5) I2CM Baud Rate */
#define REG_SERCOM5_I2CM_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
#define REG_SERCOM5_I2CM_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
#define REG_SERCOM5_I2CM_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM5_I2CM_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CM Status */
#define REG_SERCOM5_I2CM_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CM Synchronization Busy */
#define REG_SERCOM5_I2CM_ADDR (0x42001824) /**< \brief (SERCOM5) I2CM Address */
#define REG_SERCOM5_I2CM_DATA (0x42001828) /**< \brief (SERCOM5) I2CM Data */
#define REG_SERCOM5_I2CM_DBGCTRL (0x42001830) /**< \brief (SERCOM5) I2CM Debug Control */
#define REG_SERCOM5_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM5) I2CS Control A */
#define REG_SERCOM5_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM5) I2CS Control B */
#define REG_SERCOM5_I2CS_INTENCLR (0x42001814) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
#define REG_SERCOM5_I2CS_INTENSET (0x42001816) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
#define REG_SERCOM5_I2CS_INTFLAG (0x42001818) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM5_I2CS_STATUS (0x4200181A) /**< \brief (SERCOM5) I2CS Status */
#define REG_SERCOM5_I2CS_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) I2CS Synchronization Busy */
#define REG_SERCOM5_I2CS_ADDR (0x42001824) /**< \brief (SERCOM5) I2CS Address */
#define REG_SERCOM5_I2CS_DATA (0x42001828) /**< \brief (SERCOM5) I2CS Data */
#define REG_SERCOM5_SPI_CTRLA (0x42001800) /**< \brief (SERCOM5) SPI Control A */
#define REG_SERCOM5_SPI_CTRLB (0x42001804) /**< \brief (SERCOM5) SPI Control B */
#define REG_SERCOM5_SPI_BAUD (0x4200180C) /**< \brief (SERCOM5) SPI Baud Rate */
#define REG_SERCOM5_SPI_INTENCLR (0x42001814) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
#define REG_SERCOM5_SPI_INTENSET (0x42001816) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
#define REG_SERCOM5_SPI_INTFLAG (0x42001818) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM5_SPI_STATUS (0x4200181A) /**< \brief (SERCOM5) SPI Status */
#define REG_SERCOM5_SPI_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) SPI Synchronization Busy */
#define REG_SERCOM5_SPI_ADDR (0x42001824) /**< \brief (SERCOM5) SPI Address */
#define REG_SERCOM5_SPI_DATA (0x42001828) /**< \brief (SERCOM5) SPI Data */
#define REG_SERCOM5_SPI_DBGCTRL (0x42001830) /**< \brief (SERCOM5) SPI Debug Control */
#define REG_SERCOM5_USART_CTRLA (0x42001800) /**< \brief (SERCOM5) USART Control A */
#define REG_SERCOM5_USART_CTRLB (0x42001804) /**< \brief (SERCOM5) USART Control B */
#define REG_SERCOM5_USART_CTRLC (0x42001808) /**< \brief (SERCOM5) USART Control C */
#define REG_SERCOM5_USART_BAUD (0x4200180C) /**< \brief (SERCOM5) USART Baud Rate */
#define REG_SERCOM5_USART_RXPL (0x4200180E) /**< \brief (SERCOM5) USART Receive Pulse Length */
#define REG_SERCOM5_USART_INTENCLR (0x42001814) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
#define REG_SERCOM5_USART_INTENSET (0x42001816) /**< \brief (SERCOM5) USART Interrupt Enable Set */
#define REG_SERCOM5_USART_INTFLAG (0x42001818) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
#define REG_SERCOM5_USART_STATUS (0x4200181A) /**< \brief (SERCOM5) USART Status */
#define REG_SERCOM5_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM5) USART Synchronization Busy */
#define REG_SERCOM5_USART_DATA (0x42001828) /**< \brief (SERCOM5) USART Data */
#define REG_SERCOM5_USART_DBGCTRL (0x42001830) /**< \brief (SERCOM5) USART Debug Control */
#else
#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CM Control A */
#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CM Control B */
#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x4200180CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CM Status */
#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CM Synchronization Busy */
#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CM Address */
#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CM Data */
#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) I2CM Debug Control */
#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) I2CS Control A */
#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) I2CS Control B */
#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) I2CS Status */
#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) I2CS Synchronization Busy */
#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) I2CS Address */
#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM5) I2CS Data */
#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) SPI Control A */
#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) SPI Control B */
#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM5) SPI Baud Rate */
#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) SPI Status */
#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) SPI Synchronization Busy */
#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM5) SPI Address */
#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001828UL) /**< \brief (SERCOM5) SPI Data */
#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) SPI Debug Control */
#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM5) USART Control A */
#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM5) USART Control B */
#define REG_SERCOM5_USART_CTRLC (*(RwReg *)0x42001808UL) /**< \brief (SERCOM5) USART Control C */
#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM5) USART Baud Rate */
#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM5) USART Status */
#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM5) USART Synchronization Busy */
#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM5) USART Data */
#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM5) USART Debug Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SERCOM5 peripheral ========== */
#define SERCOM5_DMAC_ID_RX 12 // Index of DMA RX trigger
#define SERCOM5_DMAC_ID_TX 13 // Index of DMA TX trigger
#define SERCOM5_GCLK_ID_CORE 25
#define SERCOM5_GCLK_ID_SLOW 24
#define SERCOM5_INT_MSB 6
#define SERCOM5_PMSB 3
#endif /* _SAMC21_SERCOM5_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for SUPC
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_SUPC_INSTANCE_
#define _SAMC21_SUPC_INSTANCE_
/* ========== Register definition for SUPC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SUPC_INTENCLR (0x40001800) /**< \brief (SUPC) Interrupt Enable Clear */
#define REG_SUPC_INTENSET (0x40001804) /**< \brief (SUPC) Interrupt Enable Set */
#define REG_SUPC_INTFLAG (0x40001808) /**< \brief (SUPC) Interrupt Flag Status and Clear */
#define REG_SUPC_STATUS (0x4000180C) /**< \brief (SUPC) Power and Clocks Status */
#define REG_SUPC_BODVDD (0x40001810) /**< \brief (SUPC) BODVDD Control */
#define REG_SUPC_BODCORE (0x40001814) /**< \brief (SUPC) BODCORE Control */
#define REG_SUPC_VREG (0x40001818) /**< \brief (SUPC) VREG Control */
#define REG_SUPC_VREF (0x4000181C) /**< \brief (SUPC) VREF Control */
#else
#define REG_SUPC_INTENCLR (*(RwReg *)0x40001800UL) /**< \brief (SUPC) Interrupt Enable Clear */
#define REG_SUPC_INTENSET (*(RwReg *)0x40001804UL) /**< \brief (SUPC) Interrupt Enable Set */
#define REG_SUPC_INTFLAG (*(RwReg *)0x40001808UL) /**< \brief (SUPC) Interrupt Flag Status and Clear */
#define REG_SUPC_STATUS (*(RoReg *)0x4000180CUL) /**< \brief (SUPC) Power and Clocks Status */
#define REG_SUPC_BODVDD (*(RwReg *)0x40001810UL) /**< \brief (SUPC) BODVDD Control */
#define REG_SUPC_BODCORE (*(RwReg *)0x40001814UL) /**< \brief (SUPC) BODCORE Control */
#define REG_SUPC_VREG (*(RwReg *)0x40001818UL) /**< \brief (SUPC) VREG Control */
#define REG_SUPC_VREF (*(RwReg *)0x4000181CUL) /**< \brief (SUPC) VREF Control */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SUPC peripheral ========== */
#define SUPC_BODCORE_CALIB_MSB 5
#define SUPC_BODVDD_CALIB_MSB 5
#define SUPC_SUPC_OUT_NUM_MSB 1 // MSB of backup output pad Number
#endif /* _SAMC21_SUPC_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TC0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC0_INSTANCE_
#define _SAMC21_TC0_INSTANCE_
/* ========== Register definition for TC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC0_CTRLA (0x42003000) /**< \brief (TC0) Control A */
#define REG_TC0_CTRLBCLR (0x42003004) /**< \brief (TC0) Control B Clear */
#define REG_TC0_CTRLBSET (0x42003005) /**< \brief (TC0) Control B Set */
#define REG_TC0_EVCTRL (0x42003006) /**< \brief (TC0) Event Control */
#define REG_TC0_INTENCLR (0x42003008) /**< \brief (TC0) Interrupt Enable Clear */
#define REG_TC0_INTENSET (0x42003009) /**< \brief (TC0) Interrupt Enable Set */
#define REG_TC0_INTFLAG (0x4200300A) /**< \brief (TC0) Interrupt Flag Status and Clear */
#define REG_TC0_STATUS (0x4200300B) /**< \brief (TC0) Status */
#define REG_TC0_WAVE (0x4200300C) /**< \brief (TC0) Waveform Generation Control */
#define REG_TC0_DRVCTRL (0x4200300D) /**< \brief (TC0) Control C */
#define REG_TC0_DBGCTRL (0x4200300F) /**< \brief (TC0) Debug Control */
#define REG_TC0_SYNCBUSY (0x42003010) /**< \brief (TC0) Synchronization Status */
#define REG_TC0_COUNT16_COUNT (0x42003014) /**< \brief (TC0) COUNT16 Count */
#define REG_TC0_COUNT16_CC0 (0x4200301C) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
#define REG_TC0_COUNT16_CC1 (0x4200301E) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
#define REG_TC0_COUNT16_CCBUF0 (0x42003030) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT16_CCBUF1 (0x42003032) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC0_COUNT32_COUNT (0x42003014) /**< \brief (TC0) COUNT32 Count */
#define REG_TC0_COUNT32_CC0 (0x4200301C) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
#define REG_TC0_COUNT32_CC1 (0x42003020) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
#define REG_TC0_COUNT32_CCBUF0 (0x42003030) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT32_CCBUF1 (0x42003034) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC0_COUNT8_COUNT (0x42003014) /**< \brief (TC0) COUNT8 Count */
#define REG_TC0_COUNT8_PER (0x4200301B) /**< \brief (TC0) COUNT8 Period */
#define REG_TC0_COUNT8_CC0 (0x4200301C) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
#define REG_TC0_COUNT8_CC1 (0x4200301D) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
#define REG_TC0_COUNT8_PERBUF (0x4200302F) /**< \brief (TC0) COUNT8 Period Buffer */
#define REG_TC0_COUNT8_CCBUF0 (0x42003030) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT8_CCBUF1 (0x42003031) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC0_CTRLA (*(RwReg *)0x42003000UL) /**< \brief (TC0) Control A */
#define REG_TC0_CTRLBCLR (*(RwReg8 *)0x42003004UL) /**< \brief (TC0) Control B Clear */
#define REG_TC0_CTRLBSET (*(RwReg8 *)0x42003005UL) /**< \brief (TC0) Control B Set */
#define REG_TC0_EVCTRL (*(RwReg16*)0x42003006UL) /**< \brief (TC0) Event Control */
#define REG_TC0_INTENCLR (*(RwReg8 *)0x42003008UL) /**< \brief (TC0) Interrupt Enable Clear */
#define REG_TC0_INTENSET (*(RwReg8 *)0x42003009UL) /**< \brief (TC0) Interrupt Enable Set */
#define REG_TC0_INTFLAG (*(RwReg8 *)0x4200300AUL) /**< \brief (TC0) Interrupt Flag Status and Clear */
#define REG_TC0_STATUS (*(RwReg8 *)0x4200300BUL) /**< \brief (TC0) Status */
#define REG_TC0_WAVE (*(RwReg8 *)0x4200300CUL) /**< \brief (TC0) Waveform Generation Control */
#define REG_TC0_DRVCTRL (*(RwReg8 *)0x4200300DUL) /**< \brief (TC0) Control C */
#define REG_TC0_DBGCTRL (*(RwReg8 *)0x4200300FUL) /**< \brief (TC0) Debug Control */
#define REG_TC0_SYNCBUSY (*(RoReg *)0x42003010UL) /**< \brief (TC0) Synchronization Status */
#define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x42003014UL) /**< \brief (TC0) COUNT16 Count */
#define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4200301CUL) /**< \brief (TC0) COUNT16 Compare and Capture 0 */
#define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4200301EUL) /**< \brief (TC0) COUNT16 Compare and Capture 1 */
#define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x42003030UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x42003032UL) /**< \brief (TC0) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC0_COUNT32_COUNT (*(RwReg *)0x42003014UL) /**< \brief (TC0) COUNT32 Count */
#define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4200301CUL) /**< \brief (TC0) COUNT32 Compare and Capture 0 */
#define REG_TC0_COUNT32_CC1 (*(RwReg *)0x42003020UL) /**< \brief (TC0) COUNT32 Compare and Capture 1 */
#define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x42003030UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x42003034UL) /**< \brief (TC0) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x42003014UL) /**< \brief (TC0) COUNT8 Count */
#define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4200301BUL) /**< \brief (TC0) COUNT8 Period */
#define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4200301CUL) /**< \brief (TC0) COUNT8 Compare and Capture 0 */
#define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4200301DUL) /**< \brief (TC0) COUNT8 Compare and Capture 1 */
#define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4200302FUL) /**< \brief (TC0) COUNT8 Period Buffer */
#define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x42003030UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x42003031UL) /**< \brief (TC0) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC0 peripheral ========== */
#define TC0_CC_NUM 2
#define TC0_DMAC_ID_MC_0 28
#define TC0_DMAC_ID_MC_1 29
#define TC0_DMAC_ID_MC_LSB 28
#define TC0_DMAC_ID_MC_MSB 29
#define TC0_DMAC_ID_MC_SIZE 2
#define TC0_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
#define TC0_EXT 0
#define TC0_GCLK_ID 30
#define TC0_MASTER 1
#define TC0_OW_NUM 2
#endif /* _SAMC21_TC0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TC1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC1_INSTANCE_
#define _SAMC21_TC1_INSTANCE_
/* ========== Register definition for TC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC1_CTRLA (0x42003400) /**< \brief (TC1) Control A */
#define REG_TC1_CTRLBCLR (0x42003404) /**< \brief (TC1) Control B Clear */
#define REG_TC1_CTRLBSET (0x42003405) /**< \brief (TC1) Control B Set */
#define REG_TC1_EVCTRL (0x42003406) /**< \brief (TC1) Event Control */
#define REG_TC1_INTENCLR (0x42003408) /**< \brief (TC1) Interrupt Enable Clear */
#define REG_TC1_INTENSET (0x42003409) /**< \brief (TC1) Interrupt Enable Set */
#define REG_TC1_INTFLAG (0x4200340A) /**< \brief (TC1) Interrupt Flag Status and Clear */
#define REG_TC1_STATUS (0x4200340B) /**< \brief (TC1) Status */
#define REG_TC1_WAVE (0x4200340C) /**< \brief (TC1) Waveform Generation Control */
#define REG_TC1_DRVCTRL (0x4200340D) /**< \brief (TC1) Control C */
#define REG_TC1_DBGCTRL (0x4200340F) /**< \brief (TC1) Debug Control */
#define REG_TC1_SYNCBUSY (0x42003410) /**< \brief (TC1) Synchronization Status */
#define REG_TC1_COUNT16_COUNT (0x42003414) /**< \brief (TC1) COUNT16 Count */
#define REG_TC1_COUNT16_CC0 (0x4200341C) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
#define REG_TC1_COUNT16_CC1 (0x4200341E) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
#define REG_TC1_COUNT16_CCBUF0 (0x42003430) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT16_CCBUF1 (0x42003432) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC1_COUNT32_COUNT (0x42003414) /**< \brief (TC1) COUNT32 Count */
#define REG_TC1_COUNT32_CC0 (0x4200341C) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
#define REG_TC1_COUNT32_CC1 (0x42003420) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
#define REG_TC1_COUNT32_CCBUF0 (0x42003430) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT32_CCBUF1 (0x42003434) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC1_COUNT8_COUNT (0x42003414) /**< \brief (TC1) COUNT8 Count */
#define REG_TC1_COUNT8_PER (0x4200341B) /**< \brief (TC1) COUNT8 Period */
#define REG_TC1_COUNT8_CC0 (0x4200341C) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
#define REG_TC1_COUNT8_CC1 (0x4200341D) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
#define REG_TC1_COUNT8_PERBUF (0x4200342F) /**< \brief (TC1) COUNT8 Period Buffer */
#define REG_TC1_COUNT8_CCBUF0 (0x42003430) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT8_CCBUF1 (0x42003431) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC1_CTRLA (*(RwReg *)0x42003400UL) /**< \brief (TC1) Control A */
#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x42003404UL) /**< \brief (TC1) Control B Clear */
#define REG_TC1_CTRLBSET (*(RwReg8 *)0x42003405UL) /**< \brief (TC1) Control B Set */
#define REG_TC1_EVCTRL (*(RwReg16*)0x42003406UL) /**< \brief (TC1) Event Control */
#define REG_TC1_INTENCLR (*(RwReg8 *)0x42003408UL) /**< \brief (TC1) Interrupt Enable Clear */
#define REG_TC1_INTENSET (*(RwReg8 *)0x42003409UL) /**< \brief (TC1) Interrupt Enable Set */
#define REG_TC1_INTFLAG (*(RwReg8 *)0x4200340AUL) /**< \brief (TC1) Interrupt Flag Status and Clear */
#define REG_TC1_STATUS (*(RwReg8 *)0x4200340BUL) /**< \brief (TC1) Status */
#define REG_TC1_WAVE (*(RwReg8 *)0x4200340CUL) /**< \brief (TC1) Waveform Generation Control */
#define REG_TC1_DRVCTRL (*(RwReg8 *)0x4200340DUL) /**< \brief (TC1) Control C */
#define REG_TC1_DBGCTRL (*(RwReg8 *)0x4200340FUL) /**< \brief (TC1) Debug Control */
#define REG_TC1_SYNCBUSY (*(RoReg *)0x42003410UL) /**< \brief (TC1) Synchronization Status */
#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x42003414UL) /**< \brief (TC1) COUNT16 Count */
#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x4200341CUL) /**< \brief (TC1) COUNT16 Compare and Capture 0 */
#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x4200341EUL) /**< \brief (TC1) COUNT16 Compare and Capture 1 */
#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x42003430UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x42003432UL) /**< \brief (TC1) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x42003414UL) /**< \brief (TC1) COUNT32 Count */
#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x4200341CUL) /**< \brief (TC1) COUNT32 Compare and Capture 0 */
#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x42003420UL) /**< \brief (TC1) COUNT32 Compare and Capture 1 */
#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x42003430UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x42003434UL) /**< \brief (TC1) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x42003414UL) /**< \brief (TC1) COUNT8 Count */
#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x4200341BUL) /**< \brief (TC1) COUNT8 Period */
#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x4200341CUL) /**< \brief (TC1) COUNT8 Compare and Capture 0 */
#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x4200341DUL) /**< \brief (TC1) COUNT8 Compare and Capture 1 */
#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x4200342FUL) /**< \brief (TC1) COUNT8 Period Buffer */
#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x42003430UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x42003431UL) /**< \brief (TC1) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC1 peripheral ========== */
#define TC1_CC_NUM 2
#define TC1_DMAC_ID_MC_0 31
#define TC1_DMAC_ID_MC_1 32
#define TC1_DMAC_ID_MC_LSB 31
#define TC1_DMAC_ID_MC_MSB 32
#define TC1_DMAC_ID_MC_SIZE 2
#define TC1_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
#define TC1_EXT 0
#define TC1_GCLK_ID 30
#define TC1_MASTER 0
#define TC1_OW_NUM 2
#endif /* _SAMC21_TC1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TC2
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC2_INSTANCE_
#define _SAMC21_TC2_INSTANCE_
/* ========== Register definition for TC2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC2_CTRLA (0x42003800) /**< \brief (TC2) Control A */
#define REG_TC2_CTRLBCLR (0x42003804) /**< \brief (TC2) Control B Clear */
#define REG_TC2_CTRLBSET (0x42003805) /**< \brief (TC2) Control B Set */
#define REG_TC2_EVCTRL (0x42003806) /**< \brief (TC2) Event Control */
#define REG_TC2_INTENCLR (0x42003808) /**< \brief (TC2) Interrupt Enable Clear */
#define REG_TC2_INTENSET (0x42003809) /**< \brief (TC2) Interrupt Enable Set */
#define REG_TC2_INTFLAG (0x4200380A) /**< \brief (TC2) Interrupt Flag Status and Clear */
#define REG_TC2_STATUS (0x4200380B) /**< \brief (TC2) Status */
#define REG_TC2_WAVE (0x4200380C) /**< \brief (TC2) Waveform Generation Control */
#define REG_TC2_DRVCTRL (0x4200380D) /**< \brief (TC2) Control C */
#define REG_TC2_DBGCTRL (0x4200380F) /**< \brief (TC2) Debug Control */
#define REG_TC2_SYNCBUSY (0x42003810) /**< \brief (TC2) Synchronization Status */
#define REG_TC2_COUNT16_COUNT (0x42003814) /**< \brief (TC2) COUNT16 Count */
#define REG_TC2_COUNT16_CC0 (0x4200381C) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
#define REG_TC2_COUNT16_CC1 (0x4200381E) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
#define REG_TC2_COUNT16_CCBUF0 (0x42003830) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT16_CCBUF1 (0x42003832) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC2_COUNT32_COUNT (0x42003814) /**< \brief (TC2) COUNT32 Count */
#define REG_TC2_COUNT32_CC0 (0x4200381C) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
#define REG_TC2_COUNT32_CC1 (0x42003820) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
#define REG_TC2_COUNT32_CCBUF0 (0x42003830) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT32_CCBUF1 (0x42003834) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC2_COUNT8_COUNT (0x42003814) /**< \brief (TC2) COUNT8 Count */
#define REG_TC2_COUNT8_PER (0x4200381B) /**< \brief (TC2) COUNT8 Period */
#define REG_TC2_COUNT8_CC0 (0x4200381C) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
#define REG_TC2_COUNT8_CC1 (0x4200381D) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
#define REG_TC2_COUNT8_PERBUF (0x4200382F) /**< \brief (TC2) COUNT8 Period Buffer */
#define REG_TC2_COUNT8_CCBUF0 (0x42003830) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT8_CCBUF1 (0x42003831) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC2_CTRLA (*(RwReg *)0x42003800UL) /**< \brief (TC2) Control A */
#define REG_TC2_CTRLBCLR (*(RwReg8 *)0x42003804UL) /**< \brief (TC2) Control B Clear */
#define REG_TC2_CTRLBSET (*(RwReg8 *)0x42003805UL) /**< \brief (TC2) Control B Set */
#define REG_TC2_EVCTRL (*(RwReg16*)0x42003806UL) /**< \brief (TC2) Event Control */
#define REG_TC2_INTENCLR (*(RwReg8 *)0x42003808UL) /**< \brief (TC2) Interrupt Enable Clear */
#define REG_TC2_INTENSET (*(RwReg8 *)0x42003809UL) /**< \brief (TC2) Interrupt Enable Set */
#define REG_TC2_INTFLAG (*(RwReg8 *)0x4200380AUL) /**< \brief (TC2) Interrupt Flag Status and Clear */
#define REG_TC2_STATUS (*(RwReg8 *)0x4200380BUL) /**< \brief (TC2) Status */
#define REG_TC2_WAVE (*(RwReg8 *)0x4200380CUL) /**< \brief (TC2) Waveform Generation Control */
#define REG_TC2_DRVCTRL (*(RwReg8 *)0x4200380DUL) /**< \brief (TC2) Control C */
#define REG_TC2_DBGCTRL (*(RwReg8 *)0x4200380FUL) /**< \brief (TC2) Debug Control */
#define REG_TC2_SYNCBUSY (*(RoReg *)0x42003810UL) /**< \brief (TC2) Synchronization Status */
#define REG_TC2_COUNT16_COUNT (*(RwReg16*)0x42003814UL) /**< \brief (TC2) COUNT16 Count */
#define REG_TC2_COUNT16_CC0 (*(RwReg16*)0x4200381CUL) /**< \brief (TC2) COUNT16 Compare and Capture 0 */
#define REG_TC2_COUNT16_CC1 (*(RwReg16*)0x4200381EUL) /**< \brief (TC2) COUNT16 Compare and Capture 1 */
#define REG_TC2_COUNT16_CCBUF0 (*(RwReg16*)0x42003830UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT16_CCBUF1 (*(RwReg16*)0x42003832UL) /**< \brief (TC2) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC2_COUNT32_COUNT (*(RwReg *)0x42003814UL) /**< \brief (TC2) COUNT32 Count */
#define REG_TC2_COUNT32_CC0 (*(RwReg *)0x4200381CUL) /**< \brief (TC2) COUNT32 Compare and Capture 0 */
#define REG_TC2_COUNT32_CC1 (*(RwReg *)0x42003820UL) /**< \brief (TC2) COUNT32 Compare and Capture 1 */
#define REG_TC2_COUNT32_CCBUF0 (*(RwReg *)0x42003830UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT32_CCBUF1 (*(RwReg *)0x42003834UL) /**< \brief (TC2) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC2_COUNT8_COUNT (*(RwReg8 *)0x42003814UL) /**< \brief (TC2) COUNT8 Count */
#define REG_TC2_COUNT8_PER (*(RwReg8 *)0x4200381BUL) /**< \brief (TC2) COUNT8 Period */
#define REG_TC2_COUNT8_CC0 (*(RwReg8 *)0x4200381CUL) /**< \brief (TC2) COUNT8 Compare and Capture 0 */
#define REG_TC2_COUNT8_CC1 (*(RwReg8 *)0x4200381DUL) /**< \brief (TC2) COUNT8 Compare and Capture 1 */
#define REG_TC2_COUNT8_PERBUF (*(RwReg8 *)0x4200382FUL) /**< \brief (TC2) COUNT8 Period Buffer */
#define REG_TC2_COUNT8_CCBUF0 (*(RwReg8 *)0x42003830UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC2_COUNT8_CCBUF1 (*(RwReg8 *)0x42003831UL) /**< \brief (TC2) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC2 peripheral ========== */
#define TC2_CC_NUM 2
#define TC2_DMAC_ID_MC_0 34
#define TC2_DMAC_ID_MC_1 35
#define TC2_DMAC_ID_MC_LSB 34
#define TC2_DMAC_ID_MC_MSB 35
#define TC2_DMAC_ID_MC_SIZE 2
#define TC2_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
#define TC2_EXT 0
#define TC2_GCLK_ID 31
#define TC2_MASTER 1
#define TC2_OW_NUM 2
#endif /* _SAMC21_TC2_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TC3
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC3_INSTANCE_
#define _SAMC21_TC3_INSTANCE_
/* ========== Register definition for TC3 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC3_CTRLA (0x42003C00) /**< \brief (TC3) Control A */
#define REG_TC3_CTRLBCLR (0x42003C04) /**< \brief (TC3) Control B Clear */
#define REG_TC3_CTRLBSET (0x42003C05) /**< \brief (TC3) Control B Set */
#define REG_TC3_EVCTRL (0x42003C06) /**< \brief (TC3) Event Control */
#define REG_TC3_INTENCLR (0x42003C08) /**< \brief (TC3) Interrupt Enable Clear */
#define REG_TC3_INTENSET (0x42003C09) /**< \brief (TC3) Interrupt Enable Set */
#define REG_TC3_INTFLAG (0x42003C0A) /**< \brief (TC3) Interrupt Flag Status and Clear */
#define REG_TC3_STATUS (0x42003C0B) /**< \brief (TC3) Status */
#define REG_TC3_WAVE (0x42003C0C) /**< \brief (TC3) Waveform Generation Control */
#define REG_TC3_DRVCTRL (0x42003C0D) /**< \brief (TC3) Control C */
#define REG_TC3_DBGCTRL (0x42003C0F) /**< \brief (TC3) Debug Control */
#define REG_TC3_SYNCBUSY (0x42003C10) /**< \brief (TC3) Synchronization Status */
#define REG_TC3_COUNT16_COUNT (0x42003C14) /**< \brief (TC3) COUNT16 Count */
#define REG_TC3_COUNT16_CC0 (0x42003C1C) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
#define REG_TC3_COUNT16_CC1 (0x42003C1E) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
#define REG_TC3_COUNT16_CCBUF0 (0x42003C30) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT16_CCBUF1 (0x42003C32) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC3_COUNT32_COUNT (0x42003C14) /**< \brief (TC3) COUNT32 Count */
#define REG_TC3_COUNT32_CC0 (0x42003C1C) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
#define REG_TC3_COUNT32_CC1 (0x42003C20) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
#define REG_TC3_COUNT32_CCBUF0 (0x42003C30) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT32_CCBUF1 (0x42003C34) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC3_COUNT8_COUNT (0x42003C14) /**< \brief (TC3) COUNT8 Count */
#define REG_TC3_COUNT8_PER (0x42003C1B) /**< \brief (TC3) COUNT8 Period */
#define REG_TC3_COUNT8_CC0 (0x42003C1C) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
#define REG_TC3_COUNT8_CC1 (0x42003C1D) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
#define REG_TC3_COUNT8_PERBUF (0x42003C2F) /**< \brief (TC3) COUNT8 Period Buffer */
#define REG_TC3_COUNT8_CCBUF0 (0x42003C30) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT8_CCBUF1 (0x42003C31) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC3_CTRLA (*(RwReg *)0x42003C00UL) /**< \brief (TC3) Control A */
#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42003C04UL) /**< \brief (TC3) Control B Clear */
#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42003C05UL) /**< \brief (TC3) Control B Set */
#define REG_TC3_EVCTRL (*(RwReg16*)0x42003C06UL) /**< \brief (TC3) Event Control */
#define REG_TC3_INTENCLR (*(RwReg8 *)0x42003C08UL) /**< \brief (TC3) Interrupt Enable Clear */
#define REG_TC3_INTENSET (*(RwReg8 *)0x42003C09UL) /**< \brief (TC3) Interrupt Enable Set */
#define REG_TC3_INTFLAG (*(RwReg8 *)0x42003C0AUL) /**< \brief (TC3) Interrupt Flag Status and Clear */
#define REG_TC3_STATUS (*(RwReg8 *)0x42003C0BUL) /**< \brief (TC3) Status */
#define REG_TC3_WAVE (*(RwReg8 *)0x42003C0CUL) /**< \brief (TC3) Waveform Generation Control */
#define REG_TC3_DRVCTRL (*(RwReg8 *)0x42003C0DUL) /**< \brief (TC3) Control C */
#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42003C0FUL) /**< \brief (TC3) Debug Control */
#define REG_TC3_SYNCBUSY (*(RoReg *)0x42003C10UL) /**< \brief (TC3) Synchronization Status */
#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42003C14UL) /**< \brief (TC3) COUNT16 Count */
#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42003C1CUL) /**< \brief (TC3) COUNT16 Compare and Capture 0 */
#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42003C1EUL) /**< \brief (TC3) COUNT16 Compare and Capture 1 */
#define REG_TC3_COUNT16_CCBUF0 (*(RwReg16*)0x42003C30UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT16_CCBUF1 (*(RwReg16*)0x42003C32UL) /**< \brief (TC3) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42003C14UL) /**< \brief (TC3) COUNT32 Count */
#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42003C1CUL) /**< \brief (TC3) COUNT32 Compare and Capture 0 */
#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42003C20UL) /**< \brief (TC3) COUNT32 Compare and Capture 1 */
#define REG_TC3_COUNT32_CCBUF0 (*(RwReg *)0x42003C30UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT32_CCBUF1 (*(RwReg *)0x42003C34UL) /**< \brief (TC3) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42003C14UL) /**< \brief (TC3) COUNT8 Count */
#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42003C1BUL) /**< \brief (TC3) COUNT8 Period */
#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42003C1CUL) /**< \brief (TC3) COUNT8 Compare and Capture 0 */
#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42003C1DUL) /**< \brief (TC3) COUNT8 Compare and Capture 1 */
#define REG_TC3_COUNT8_PERBUF (*(RwReg8 *)0x42003C2FUL) /**< \brief (TC3) COUNT8 Period Buffer */
#define REG_TC3_COUNT8_CCBUF0 (*(RwReg8 *)0x42003C30UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC3_COUNT8_CCBUF1 (*(RwReg8 *)0x42003C31UL) /**< \brief (TC3) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC3 peripheral ========== */
#define TC3_CC_NUM 2
#define TC3_DMAC_ID_MC_0 37
#define TC3_DMAC_ID_MC_1 38
#define TC3_DMAC_ID_MC_LSB 37
#define TC3_DMAC_ID_MC_MSB 38
#define TC3_DMAC_ID_MC_SIZE 2
#define TC3_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
#define TC3_EXT 0
#define TC3_GCLK_ID 31
#define TC3_MASTER 0
#define TC3_OW_NUM 2
#endif /* _SAMC21_TC3_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TC4
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TC4_INSTANCE_
#define _SAMC21_TC4_INSTANCE_
/* ========== Register definition for TC4 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC4_CTRLA (0x42004000) /**< \brief (TC4) Control A */
#define REG_TC4_CTRLBCLR (0x42004004) /**< \brief (TC4) Control B Clear */
#define REG_TC4_CTRLBSET (0x42004005) /**< \brief (TC4) Control B Set */
#define REG_TC4_EVCTRL (0x42004006) /**< \brief (TC4) Event Control */
#define REG_TC4_INTENCLR (0x42004008) /**< \brief (TC4) Interrupt Enable Clear */
#define REG_TC4_INTENSET (0x42004009) /**< \brief (TC4) Interrupt Enable Set */
#define REG_TC4_INTFLAG (0x4200400A) /**< \brief (TC4) Interrupt Flag Status and Clear */
#define REG_TC4_STATUS (0x4200400B) /**< \brief (TC4) Status */
#define REG_TC4_WAVE (0x4200400C) /**< \brief (TC4) Waveform Generation Control */
#define REG_TC4_DRVCTRL (0x4200400D) /**< \brief (TC4) Control C */
#define REG_TC4_DBGCTRL (0x4200400F) /**< \brief (TC4) Debug Control */
#define REG_TC4_SYNCBUSY (0x42004010) /**< \brief (TC4) Synchronization Status */
#define REG_TC4_COUNT16_COUNT (0x42004014) /**< \brief (TC4) COUNT16 Count */
#define REG_TC4_COUNT16_CC0 (0x4200401C) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
#define REG_TC4_COUNT16_CC1 (0x4200401E) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
#define REG_TC4_COUNT16_CCBUF0 (0x42004030) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT16_CCBUF1 (0x42004032) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC4_COUNT32_COUNT (0x42004014) /**< \brief (TC4) COUNT32 Count */
#define REG_TC4_COUNT32_CC0 (0x4200401C) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
#define REG_TC4_COUNT32_CC1 (0x42004020) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
#define REG_TC4_COUNT32_CCBUF0 (0x42004030) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT32_CCBUF1 (0x42004034) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC4_COUNT8_COUNT (0x42004014) /**< \brief (TC4) COUNT8 Count */
#define REG_TC4_COUNT8_PER (0x4200401B) /**< \brief (TC4) COUNT8 Period */
#define REG_TC4_COUNT8_CC0 (0x4200401C) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
#define REG_TC4_COUNT8_CC1 (0x4200401D) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
#define REG_TC4_COUNT8_PERBUF (0x4200402F) /**< \brief (TC4) COUNT8 Period Buffer */
#define REG_TC4_COUNT8_CCBUF0 (0x42004030) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT8_CCBUF1 (0x42004031) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
#else
#define REG_TC4_CTRLA (*(RwReg *)0x42004000UL) /**< \brief (TC4) Control A */
#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42004004UL) /**< \brief (TC4) Control B Clear */
#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42004005UL) /**< \brief (TC4) Control B Set */
#define REG_TC4_EVCTRL (*(RwReg16*)0x42004006UL) /**< \brief (TC4) Event Control */
#define REG_TC4_INTENCLR (*(RwReg8 *)0x42004008UL) /**< \brief (TC4) Interrupt Enable Clear */
#define REG_TC4_INTENSET (*(RwReg8 *)0x42004009UL) /**< \brief (TC4) Interrupt Enable Set */
#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200400AUL) /**< \brief (TC4) Interrupt Flag Status and Clear */
#define REG_TC4_STATUS (*(RwReg8 *)0x4200400BUL) /**< \brief (TC4) Status */
#define REG_TC4_WAVE (*(RwReg8 *)0x4200400CUL) /**< \brief (TC4) Waveform Generation Control */
#define REG_TC4_DRVCTRL (*(RwReg8 *)0x4200400DUL) /**< \brief (TC4) Control C */
#define REG_TC4_DBGCTRL (*(RwReg8 *)0x4200400FUL) /**< \brief (TC4) Debug Control */
#define REG_TC4_SYNCBUSY (*(RoReg *)0x42004010UL) /**< \brief (TC4) Synchronization Status */
#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42004014UL) /**< \brief (TC4) COUNT16 Count */
#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x4200401CUL) /**< \brief (TC4) COUNT16 Compare and Capture 0 */
#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200401EUL) /**< \brief (TC4) COUNT16 Compare and Capture 1 */
#define REG_TC4_COUNT16_CCBUF0 (*(RwReg16*)0x42004030UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT16_CCBUF1 (*(RwReg16*)0x42004032UL) /**< \brief (TC4) COUNT16 Compare and Capture Buffer 1 */
#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42004014UL) /**< \brief (TC4) COUNT32 Count */
#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x4200401CUL) /**< \brief (TC4) COUNT32 Compare and Capture 0 */
#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x42004020UL) /**< \brief (TC4) COUNT32 Compare and Capture 1 */
#define REG_TC4_COUNT32_CCBUF0 (*(RwReg *)0x42004030UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT32_CCBUF1 (*(RwReg *)0x42004034UL) /**< \brief (TC4) COUNT32 Compare and Capture Buffer 1 */
#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42004014UL) /**< \brief (TC4) COUNT8 Count */
#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x4200401BUL) /**< \brief (TC4) COUNT8 Period */
#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x4200401CUL) /**< \brief (TC4) COUNT8 Compare and Capture 0 */
#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x4200401DUL) /**< \brief (TC4) COUNT8 Compare and Capture 1 */
#define REG_TC4_COUNT8_PERBUF (*(RwReg8 *)0x4200402FUL) /**< \brief (TC4) COUNT8 Period Buffer */
#define REG_TC4_COUNT8_CCBUF0 (*(RwReg8 *)0x42004030UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 0 */
#define REG_TC4_COUNT8_CCBUF1 (*(RwReg8 *)0x42004031UL) /**< \brief (TC4) COUNT8 Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TC4 peripheral ========== */
#define TC4_CC_NUM 2
#define TC4_DMAC_ID_MC_0 40
#define TC4_DMAC_ID_MC_1 41
#define TC4_DMAC_ID_MC_LSB 40
#define TC4_DMAC_ID_MC_MSB 41
#define TC4_DMAC_ID_MC_SIZE 2
#define TC4_DMAC_ID_OVF 39 // Indexes of DMA Overflow trigger
#define TC4_EXT 0
#define TC4_GCLK_ID 32
#define TC4_MASTER 0
#define TC4_OW_NUM 2
#endif /* _SAMC21_TC4_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TCC0
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TCC0_INSTANCE_
#define _SAMC21_TCC0_INSTANCE_
/* ========== Register definition for TCC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TCC0_CTRLA (0x42002400) /**< \brief (TCC0) Control A */
#define REG_TCC0_CTRLBCLR (0x42002404) /**< \brief (TCC0) Control B Clear */
#define REG_TCC0_CTRLBSET (0x42002405) /**< \brief (TCC0) Control B Set */
#define REG_TCC0_SYNCBUSY (0x42002408) /**< \brief (TCC0) Synchronization Busy */
#define REG_TCC0_FCTRLA (0x4200240C) /**< \brief (TCC0) Recoverable Fault A Configuration */
#define REG_TCC0_FCTRLB (0x42002410) /**< \brief (TCC0) Recoverable Fault B Configuration */
#define REG_TCC0_WEXCTRL (0x42002414) /**< \brief (TCC0) Waveform Extension Configuration */
#define REG_TCC0_DRVCTRL (0x42002418) /**< \brief (TCC0) Driver Control */
#define REG_TCC0_DBGCTRL (0x4200241E) /**< \brief (TCC0) Debug Control */
#define REG_TCC0_EVCTRL (0x42002420) /**< \brief (TCC0) Event Control */
#define REG_TCC0_INTENCLR (0x42002424) /**< \brief (TCC0) Interrupt Enable Clear */
#define REG_TCC0_INTENSET (0x42002428) /**< \brief (TCC0) Interrupt Enable Set */
#define REG_TCC0_INTFLAG (0x4200242C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
#define REG_TCC0_STATUS (0x42002430) /**< \brief (TCC0) Status */
#define REG_TCC0_COUNT (0x42002434) /**< \brief (TCC0) Count */
#define REG_TCC0_PATT (0x42002438) /**< \brief (TCC0) Pattern */
#define REG_TCC0_WAVE (0x4200243C) /**< \brief (TCC0) Waveform Control */
#define REG_TCC0_PER (0x42002440) /**< \brief (TCC0) Period */
#define REG_TCC0_CC0 (0x42002444) /**< \brief (TCC0) Compare and Capture 0 */
#define REG_TCC0_CC1 (0x42002448) /**< \brief (TCC0) Compare and Capture 1 */
#define REG_TCC0_CC2 (0x4200244C) /**< \brief (TCC0) Compare and Capture 2 */
#define REG_TCC0_CC3 (0x42002450) /**< \brief (TCC0) Compare and Capture 3 */
#define REG_TCC0_PATTBUF (0x42002464) /**< \brief (TCC0) Pattern Buffer */
#define REG_TCC0_PERBUF (0x4200246C) /**< \brief (TCC0) Period Buffer */
#define REG_TCC0_CCBUF0 (0x42002470) /**< \brief (TCC0) Compare and Capture Buffer 0 */
#define REG_TCC0_CCBUF1 (0x42002474) /**< \brief (TCC0) Compare and Capture Buffer 1 */
#define REG_TCC0_CCBUF2 (0x42002478) /**< \brief (TCC0) Compare and Capture Buffer 2 */
#define REG_TCC0_CCBUF3 (0x4200247C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
#else
#define REG_TCC0_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (TCC0) Control A */
#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TCC0) Control B Clear */
#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TCC0) Control B Set */
#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002408UL) /**< \brief (TCC0) Synchronization Busy */
#define REG_TCC0_FCTRLA (*(RwReg *)0x4200240CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
#define REG_TCC0_FCTRLB (*(RwReg *)0x42002410UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002414UL) /**< \brief (TCC0) Waveform Extension Configuration */
#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002418UL) /**< \brief (TCC0) Driver Control */
#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200241EUL) /**< \brief (TCC0) Debug Control */
#define REG_TCC0_EVCTRL (*(RwReg *)0x42002420UL) /**< \brief (TCC0) Event Control */
#define REG_TCC0_INTENCLR (*(RwReg *)0x42002424UL) /**< \brief (TCC0) Interrupt Enable Clear */
#define REG_TCC0_INTENSET (*(RwReg *)0x42002428UL) /**< \brief (TCC0) Interrupt Enable Set */
#define REG_TCC0_INTFLAG (*(RwReg *)0x4200242CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
#define REG_TCC0_STATUS (*(RwReg *)0x42002430UL) /**< \brief (TCC0) Status */
#define REG_TCC0_COUNT (*(RwReg *)0x42002434UL) /**< \brief (TCC0) Count */
#define REG_TCC0_PATT (*(RwReg16*)0x42002438UL) /**< \brief (TCC0) Pattern */
#define REG_TCC0_WAVE (*(RwReg *)0x4200243CUL) /**< \brief (TCC0) Waveform Control */
#define REG_TCC0_PER (*(RwReg *)0x42002440UL) /**< \brief (TCC0) Period */
#define REG_TCC0_CC0 (*(RwReg *)0x42002444UL) /**< \brief (TCC0) Compare and Capture 0 */
#define REG_TCC0_CC1 (*(RwReg *)0x42002448UL) /**< \brief (TCC0) Compare and Capture 1 */
#define REG_TCC0_CC2 (*(RwReg *)0x4200244CUL) /**< \brief (TCC0) Compare and Capture 2 */
#define REG_TCC0_CC3 (*(RwReg *)0x42002450UL) /**< \brief (TCC0) Compare and Capture 3 */
#define REG_TCC0_PATTBUF (*(RwReg16*)0x42002464UL) /**< \brief (TCC0) Pattern Buffer */
#define REG_TCC0_PERBUF (*(RwReg *)0x4200246CUL) /**< \brief (TCC0) Period Buffer */
#define REG_TCC0_CCBUF0 (*(RwReg *)0x42002470UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
#define REG_TCC0_CCBUF1 (*(RwReg *)0x42002474UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
#define REG_TCC0_CCBUF2 (*(RwReg *)0x42002478UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
#define REG_TCC0_CCBUF3 (*(RwReg *)0x4200247CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TCC0 peripheral ========== */
#define TCC0_CC_NUM 4 // Number of Compare/Capture units
#define TCC0_DITHERING 1 // Dithering feature implemented
#define TCC0_DMAC_ID_MC_0 17
#define TCC0_DMAC_ID_MC_1 18
#define TCC0_DMAC_ID_MC_2 19
#define TCC0_DMAC_ID_MC_3 20
#define TCC0_DMAC_ID_MC_LSB 17
#define TCC0_DMAC_ID_MC_MSB 20
#define TCC0_DMAC_ID_MC_SIZE 4
#define TCC0_DMAC_ID_OVF 16 // DMA overflow/underflow/retrigger trigger
#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
#define TCC0_EXT 31 // Coding of implemented extended features
#define TCC0_GCLK_ID 28 // Index of Generic Clock
#define TCC0_OTMX 1 // Output Matrix feature implemented
#define TCC0_OW_NUM 8 // Number of Output Waveforms
#define TCC0_PG 1 // Pattern Generation feature implemented
#define TCC0_SIZE 24
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave
#endif /* _SAMC21_TCC0_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TCC1
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TCC1_INSTANCE_
#define _SAMC21_TCC1_INSTANCE_
/* ========== Register definition for TCC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TCC1_CTRLA (0x42002800) /**< \brief (TCC1) Control A */
#define REG_TCC1_CTRLBCLR (0x42002804) /**< \brief (TCC1) Control B Clear */
#define REG_TCC1_CTRLBSET (0x42002805) /**< \brief (TCC1) Control B Set */
#define REG_TCC1_SYNCBUSY (0x42002808) /**< \brief (TCC1) Synchronization Busy */
#define REG_TCC1_FCTRLA (0x4200280C) /**< \brief (TCC1) Recoverable Fault A Configuration */
#define REG_TCC1_FCTRLB (0x42002810) /**< \brief (TCC1) Recoverable Fault B Configuration */
#define REG_TCC1_DRVCTRL (0x42002818) /**< \brief (TCC1) Driver Control */
#define REG_TCC1_DBGCTRL (0x4200281E) /**< \brief (TCC1) Debug Control */
#define REG_TCC1_EVCTRL (0x42002820) /**< \brief (TCC1) Event Control */
#define REG_TCC1_INTENCLR (0x42002824) /**< \brief (TCC1) Interrupt Enable Clear */
#define REG_TCC1_INTENSET (0x42002828) /**< \brief (TCC1) Interrupt Enable Set */
#define REG_TCC1_INTFLAG (0x4200282C) /**< \brief (TCC1) Interrupt Flag Status and Clear */
#define REG_TCC1_STATUS (0x42002830) /**< \brief (TCC1) Status */
#define REG_TCC1_COUNT (0x42002834) /**< \brief (TCC1) Count */
#define REG_TCC1_PATT (0x42002838) /**< \brief (TCC1) Pattern */
#define REG_TCC1_WAVE (0x4200283C) /**< \brief (TCC1) Waveform Control */
#define REG_TCC1_PER (0x42002840) /**< \brief (TCC1) Period */
#define REG_TCC1_CC0 (0x42002844) /**< \brief (TCC1) Compare and Capture 0 */
#define REG_TCC1_CC1 (0x42002848) /**< \brief (TCC1) Compare and Capture 1 */
#define REG_TCC1_PATTBUF (0x42002864) /**< \brief (TCC1) Pattern Buffer */
#define REG_TCC1_PERBUF (0x4200286C) /**< \brief (TCC1) Period Buffer */
#define REG_TCC1_CCBUF0 (0x42002870) /**< \brief (TCC1) Compare and Capture Buffer 0 */
#define REG_TCC1_CCBUF1 (0x42002874) /**< \brief (TCC1) Compare and Capture Buffer 1 */
#else
#define REG_TCC1_CTRLA (*(RwReg *)0x42002800UL) /**< \brief (TCC1) Control A */
#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TCC1) Control B Clear */
#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TCC1) Control B Set */
#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002808UL) /**< \brief (TCC1) Synchronization Busy */
#define REG_TCC1_FCTRLA (*(RwReg *)0x4200280CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */
#define REG_TCC1_FCTRLB (*(RwReg *)0x42002810UL) /**< \brief (TCC1) Recoverable Fault B Configuration */
#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002818UL) /**< \brief (TCC1) Driver Control */
#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200281EUL) /**< \brief (TCC1) Debug Control */
#define REG_TCC1_EVCTRL (*(RwReg *)0x42002820UL) /**< \brief (TCC1) Event Control */
#define REG_TCC1_INTENCLR (*(RwReg *)0x42002824UL) /**< \brief (TCC1) Interrupt Enable Clear */
#define REG_TCC1_INTENSET (*(RwReg *)0x42002828UL) /**< \brief (TCC1) Interrupt Enable Set */
#define REG_TCC1_INTFLAG (*(RwReg *)0x4200282CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */
#define REG_TCC1_STATUS (*(RwReg *)0x42002830UL) /**< \brief (TCC1) Status */
#define REG_TCC1_COUNT (*(RwReg *)0x42002834UL) /**< \brief (TCC1) Count */
#define REG_TCC1_PATT (*(RwReg16*)0x42002838UL) /**< \brief (TCC1) Pattern */
#define REG_TCC1_WAVE (*(RwReg *)0x4200283CUL) /**< \brief (TCC1) Waveform Control */
#define REG_TCC1_PER (*(RwReg *)0x42002840UL) /**< \brief (TCC1) Period */
#define REG_TCC1_CC0 (*(RwReg *)0x42002844UL) /**< \brief (TCC1) Compare and Capture 0 */
#define REG_TCC1_CC1 (*(RwReg *)0x42002848UL) /**< \brief (TCC1) Compare and Capture 1 */
#define REG_TCC1_PATTBUF (*(RwReg16*)0x42002864UL) /**< \brief (TCC1) Pattern Buffer */
#define REG_TCC1_PERBUF (*(RwReg *)0x4200286CUL) /**< \brief (TCC1) Period Buffer */
#define REG_TCC1_CCBUF0 (*(RwReg *)0x42002870UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */
#define REG_TCC1_CCBUF1 (*(RwReg *)0x42002874UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TCC1 peripheral ========== */
#define TCC1_CC_NUM 2 // Number of Compare/Capture units
#define TCC1_DITHERING 1 // Dithering feature implemented
#define TCC1_DMAC_ID_MC_0 22
#define TCC1_DMAC_ID_MC_1 23
#define TCC1_DMAC_ID_MC_LSB 22
#define TCC1_DMAC_ID_MC_MSB 23
#define TCC1_DMAC_ID_MC_SIZE 2
#define TCC1_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger
#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
#define TCC1_EXT 24 // Coding of implemented extended features
#define TCC1_GCLK_ID 28 // Index of Generic Clock
#define TCC1_OTMX 0 // Output Matrix feature implemented
#define TCC1_OW_NUM 4 // Number of Output Waveforms
#define TCC1_PG 1 // Pattern Generation feature implemented
#define TCC1_SIZE 24
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
#endif /* _SAMC21_TCC1_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TCC2
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TCC2_INSTANCE_
#define _SAMC21_TCC2_INSTANCE_
/* ========== Register definition for TCC2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TCC2_CTRLA (0x42002C00) /**< \brief (TCC2) Control A */
#define REG_TCC2_CTRLBCLR (0x42002C04) /**< \brief (TCC2) Control B Clear */
#define REG_TCC2_CTRLBSET (0x42002C05) /**< \brief (TCC2) Control B Set */
#define REG_TCC2_SYNCBUSY (0x42002C08) /**< \brief (TCC2) Synchronization Busy */
#define REG_TCC2_FCTRLA (0x42002C0C) /**< \brief (TCC2) Recoverable Fault A Configuration */
#define REG_TCC2_FCTRLB (0x42002C10) /**< \brief (TCC2) Recoverable Fault B Configuration */
#define REG_TCC2_DRVCTRL (0x42002C18) /**< \brief (TCC2) Driver Control */
#define REG_TCC2_DBGCTRL (0x42002C1E) /**< \brief (TCC2) Debug Control */
#define REG_TCC2_EVCTRL (0x42002C20) /**< \brief (TCC2) Event Control */
#define REG_TCC2_INTENCLR (0x42002C24) /**< \brief (TCC2) Interrupt Enable Clear */
#define REG_TCC2_INTENSET (0x42002C28) /**< \brief (TCC2) Interrupt Enable Set */
#define REG_TCC2_INTFLAG (0x42002C2C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
#define REG_TCC2_STATUS (0x42002C30) /**< \brief (TCC2) Status */
#define REG_TCC2_COUNT (0x42002C34) /**< \brief (TCC2) Count */
#define REG_TCC2_WAVE (0x42002C3C) /**< \brief (TCC2) Waveform Control */
#define REG_TCC2_PER (0x42002C40) /**< \brief (TCC2) Period */
#define REG_TCC2_CC0 (0x42002C44) /**< \brief (TCC2) Compare and Capture 0 */
#define REG_TCC2_CC1 (0x42002C48) /**< \brief (TCC2) Compare and Capture 1 */
#define REG_TCC2_PERBUF (0x42002C6C) /**< \brief (TCC2) Period Buffer */
#define REG_TCC2_CCBUF0 (0x42002C70) /**< \brief (TCC2) Compare and Capture Buffer 0 */
#define REG_TCC2_CCBUF1 (0x42002C74) /**< \brief (TCC2) Compare and Capture Buffer 1 */
#else
#define REG_TCC2_CTRLA (*(RwReg *)0x42002C00UL) /**< \brief (TCC2) Control A */
#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TCC2) Control B Clear */
#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TCC2) Control B Set */
#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002C08UL) /**< \brief (TCC2) Synchronization Busy */
#define REG_TCC2_FCTRLA (*(RwReg *)0x42002C0CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
#define REG_TCC2_FCTRLB (*(RwReg *)0x42002C10UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002C18UL) /**< \brief (TCC2) Driver Control */
#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x42002C1EUL) /**< \brief (TCC2) Debug Control */
#define REG_TCC2_EVCTRL (*(RwReg *)0x42002C20UL) /**< \brief (TCC2) Event Control */
#define REG_TCC2_INTENCLR (*(RwReg *)0x42002C24UL) /**< \brief (TCC2) Interrupt Enable Clear */
#define REG_TCC2_INTENSET (*(RwReg *)0x42002C28UL) /**< \brief (TCC2) Interrupt Enable Set */
#define REG_TCC2_INTFLAG (*(RwReg *)0x42002C2CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
#define REG_TCC2_STATUS (*(RwReg *)0x42002C30UL) /**< \brief (TCC2) Status */
#define REG_TCC2_COUNT (*(RwReg *)0x42002C34UL) /**< \brief (TCC2) Count */
#define REG_TCC2_WAVE (*(RwReg *)0x42002C3CUL) /**< \brief (TCC2) Waveform Control */
#define REG_TCC2_PER (*(RwReg *)0x42002C40UL) /**< \brief (TCC2) Period */
#define REG_TCC2_CC0 (*(RwReg *)0x42002C44UL) /**< \brief (TCC2) Compare and Capture 0 */
#define REG_TCC2_CC1 (*(RwReg *)0x42002C48UL) /**< \brief (TCC2) Compare and Capture 1 */
#define REG_TCC2_PERBUF (*(RwReg *)0x42002C6CUL) /**< \brief (TCC2) Period Buffer */
#define REG_TCC2_CCBUF0 (*(RwReg *)0x42002C70UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
#define REG_TCC2_CCBUF1 (*(RwReg *)0x42002C74UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TCC2 peripheral ========== */
#define TCC2_CC_NUM 2 // Number of Compare/Capture units
#define TCC2_DITHERING 0 // Dithering feature implemented
#define TCC2_DMAC_ID_MC_0 25
#define TCC2_DMAC_ID_MC_1 26
#define TCC2_DMAC_ID_MC_LSB 25
#define TCC2_DMAC_ID_MC_MSB 26
#define TCC2_DMAC_ID_MC_SIZE 2
#define TCC2_DMAC_ID_OVF 24 // DMA overflow/underflow/retrigger trigger
#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
#define TCC2_EXT 0 // Coding of implemented extended features
#define TCC2_GCLK_ID 29 // Index of Generic Clock
#define TCC2_OTMX 0 // Output Matrix feature implemented
#define TCC2_OW_NUM 2 // Number of Output Waveforms
#define TCC2_PG 0 // Pattern Generation feature implemented
#define TCC2_SIZE 16
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
#endif /* _SAMC21_TCC2_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for TSENS
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_TSENS_INSTANCE_
#define _SAMC21_TSENS_INSTANCE_
/* ========== Register definition for TSENS peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TSENS_CTRLA (0x40003000) /**< \brief (TSENS) Control A Register */
#define REG_TSENS_CTRLB (0x40003001) /**< \brief (TSENS) Control B Register */
#define REG_TSENS_CTRLC (0x40003002) /**< \brief (TSENS) Control C Register */
#define REG_TSENS_EVCTRL (0x40003003) /**< \brief (TSENS) Event Control Register */
#define REG_TSENS_INTENCLR (0x40003004) /**< \brief (TSENS) Interrupt Enable Clear Register */
#define REG_TSENS_INTENSET (0x40003005) /**< \brief (TSENS) Interrupt Enable Set Register */
#define REG_TSENS_INTFLAG (0x40003006) /**< \brief (TSENS) Interrupt Flag Status and Clear Register */
#define REG_TSENS_STATUS (0x40003007) /**< \brief (TSENS) Status Register */
#define REG_TSENS_SYNCBUSY (0x40003008) /**< \brief (TSENS) Synchronization Busy Register */
#define REG_TSENS_VALUE (0x4000300C) /**< \brief (TSENS) Value Register */
#define REG_TSENS_WINLT (0x40003010) /**< \brief (TSENS) Window Monitor Lower Threshold Register */
#define REG_TSENS_WINUT (0x40003014) /**< \brief (TSENS) Window Monitor Upper Threshold Register */
#define REG_TSENS_GAIN (0x40003018) /**< \brief (TSENS) Gain Register */
#define REG_TSENS_OFFSET (0x4000301C) /**< \brief (TSENS) Offset Register */
#define REG_TSENS_CAL (0x40003020) /**< \brief (TSENS) Calibration Register */
#define REG_TSENS_DBGCTRL (0x40003024) /**< \brief (TSENS) Debug Control Register */
#else
#define REG_TSENS_CTRLA (*(RwReg8 *)0x40003000UL) /**< \brief (TSENS) Control A Register */
#define REG_TSENS_CTRLB (*(WoReg8 *)0x40003001UL) /**< \brief (TSENS) Control B Register */
#define REG_TSENS_CTRLC (*(RwReg8 *)0x40003002UL) /**< \brief (TSENS) Control C Register */
#define REG_TSENS_EVCTRL (*(RwReg8 *)0x40003003UL) /**< \brief (TSENS) Event Control Register */
#define REG_TSENS_INTENCLR (*(RwReg8 *)0x40003004UL) /**< \brief (TSENS) Interrupt Enable Clear Register */
#define REG_TSENS_INTENSET (*(RwReg8 *)0x40003005UL) /**< \brief (TSENS) Interrupt Enable Set Register */
#define REG_TSENS_INTFLAG (*(RwReg8 *)0x40003006UL) /**< \brief (TSENS) Interrupt Flag Status and Clear Register */
#define REG_TSENS_STATUS (*(RoReg8 *)0x40003007UL) /**< \brief (TSENS) Status Register */
#define REG_TSENS_SYNCBUSY (*(RoReg *)0x40003008UL) /**< \brief (TSENS) Synchronization Busy Register */
#define REG_TSENS_VALUE (*(RoReg *)0x4000300CUL) /**< \brief (TSENS) Value Register */
#define REG_TSENS_WINLT (*(RwReg *)0x40003010UL) /**< \brief (TSENS) Window Monitor Lower Threshold Register */
#define REG_TSENS_WINUT (*(RwReg *)0x40003014UL) /**< \brief (TSENS) Window Monitor Upper Threshold Register */
#define REG_TSENS_GAIN (*(RwReg *)0x40003018UL) /**< \brief (TSENS) Gain Register */
#define REG_TSENS_OFFSET (*(RwReg *)0x4000301CUL) /**< \brief (TSENS) Offset Register */
#define REG_TSENS_CAL (*(RwReg *)0x40003020UL) /**< \brief (TSENS) Calibration Register */
#define REG_TSENS_DBGCTRL (*(RwReg8 *)0x40003024UL) /**< \brief (TSENS) Debug Control Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for TSENS peripheral ========== */
#define TSENS_DMAC_ID_RESRDY 1 // Index of DMA RESRDY trigger
#define TSENS_GCLK_ID 5 // Index of Generic Clock
#endif /* _SAMC21_TSENS_INSTANCE_ */

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/**
* \file
*
* \brief Instance description for WDT
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_WDT_INSTANCE_
#define _SAMC21_WDT_INSTANCE_
/* ========== Register definition for WDT peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */
#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */
#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */
#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */
#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */
#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */
#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */
#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */
#else
#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */
#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */
#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */
#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */
#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */
#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */
#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */
#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAMC21_WDT_INSTANCE_ */

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/**
* \file
*
* \brief Peripheral I/O description for SAMC21E15A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21E15A_PIO_
#define _SAMC21E15A_PIO_
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
#define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
/* ========== PORT definition for RSTC peripheral ========== */
#define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */
#define MUX_PA00A_RSTC_EXTWAKE0 _L_(0)
#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0)
#define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0)
#define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */
#define MUX_PA01A_RSTC_EXTWAKE1 _L_(0)
#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1)
#define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1)
#define PIN_PA02A_RSTC_EXTWAKE2 _L_(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */
#define MUX_PA02A_RSTC_EXTWAKE2 _L_(0)
#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2)
#define PORT_PA02A_RSTC_EXTWAKE2 (_UL_(1) << 2)
#define PIN_PA03A_RSTC_EXTWAKE3 _L_(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */
#define MUX_PA03A_RSTC_EXTWAKE3 _L_(0)
#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3)
#define PORT_PA03A_RSTC_EXTWAKE3 (_UL_(1) << 3)
#define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */
#define MUX_PA04A_RSTC_EXTWAKE4 _L_(0)
#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4)
#define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4)
#define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */
#define MUX_PA05A_RSTC_EXTWAKE5 _L_(0)
#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5)
#define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5)
#define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */
#define MUX_PA06A_RSTC_EXTWAKE6 _L_(0)
#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6)
#define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6)
#define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */
#define MUX_PA07A_RSTC_EXTWAKE7 _L_(0)
#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7)
#define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7)
#define PIN_PA08A_RSTC_EXTWAKE8 _L_(8) /**< \brief RSTC signal: EXTWAKE8 on PA08 mux A */
#define MUX_PA08A_RSTC_EXTWAKE8 _L_(0)
#define PINMUX_PA08A_RSTC_EXTWAKE8 ((PIN_PA08A_RSTC_EXTWAKE8 << 16) | MUX_PA08A_RSTC_EXTWAKE8)
#define PORT_PA08A_RSTC_EXTWAKE8 (_UL_(1) << 8)
#define PIN_PA09A_RSTC_EXTWAKE9 _L_(9) /**< \brief RSTC signal: EXTWAKE9 on PA09 mux A */
#define MUX_PA09A_RSTC_EXTWAKE9 _L_(0)
#define PINMUX_PA09A_RSTC_EXTWAKE9 ((PIN_PA09A_RSTC_EXTWAKE9 << 16) | MUX_PA09A_RSTC_EXTWAKE9)
#define PORT_PA09A_RSTC_EXTWAKE9 (_UL_(1) << 9)
#define PIN_PA10A_RSTC_EXTWAKE10 _L_(10) /**< \brief RSTC signal: EXTWAKE10 on PA10 mux A */
#define MUX_PA10A_RSTC_EXTWAKE10 _L_(0)
#define PINMUX_PA10A_RSTC_EXTWAKE10 ((PIN_PA10A_RSTC_EXTWAKE10 << 16) | MUX_PA10A_RSTC_EXTWAKE10)
#define PORT_PA10A_RSTC_EXTWAKE10 (_UL_(1) << 10)
#define PIN_PA11A_RSTC_EXTWAKE11 _L_(11) /**< \brief RSTC signal: EXTWAKE11 on PA11 mux A */
#define MUX_PA11A_RSTC_EXTWAKE11 _L_(0)
#define PINMUX_PA11A_RSTC_EXTWAKE11 ((PIN_PA11A_RSTC_EXTWAKE11 << 16) | MUX_PA11A_RSTC_EXTWAKE11)
#define PORT_PA11A_RSTC_EXTWAKE11 (_UL_(1) << 11)
#define PIN_PA14A_RSTC_EXTWAKE14 _L_(14) /**< \brief RSTC signal: EXTWAKE14 on PA14 mux A */
#define MUX_PA14A_RSTC_EXTWAKE14 _L_(0)
#define PINMUX_PA14A_RSTC_EXTWAKE14 ((PIN_PA14A_RSTC_EXTWAKE14 << 16) | MUX_PA14A_RSTC_EXTWAKE14)
#define PORT_PA14A_RSTC_EXTWAKE14 (_UL_(1) << 14)
#define PIN_PA15A_RSTC_EXTWAKE15 _L_(15) /**< \brief RSTC signal: EXTWAKE15 on PA15 mux A */
#define MUX_PA15A_RSTC_EXTWAKE15 _L_(0)
#define PINMUX_PA15A_RSTC_EXTWAKE15 ((PIN_PA15A_RSTC_EXTWAKE15 << 16) | MUX_PA15A_RSTC_EXTWAKE15)
#define PORT_PA15A_RSTC_EXTWAKE15 (_UL_(1) << 15)
/* ========== PORT definition for GCLK peripheral ========== */
#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
#define MUX_PA14H_GCLK_IO0 _L_(7)
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14)
#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
#define MUX_PA27H_GCLK_IO0 _L_(7)
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27)
#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
#define MUX_PA30H_GCLK_IO0 _L_(7)
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30)
#define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
#define MUX_PA28H_GCLK_IO0 _L_(7)
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
#define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28)
#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
#define MUX_PA15H_GCLK_IO1 _L_(7)
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15)
#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
#define MUX_PA16H_GCLK_IO2 _L_(7)
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16)
#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
#define MUX_PA17H_GCLK_IO3 _L_(7)
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17)
#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
#define MUX_PA10H_GCLK_IO4 _L_(7)
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10)
#define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
#define MUX_PA11H_GCLK_IO5 _L_(7)
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
#define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11)
#define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
#define MUX_PA22H_GCLK_IO6 _L_(7)
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
#define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22)
#define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
#define MUX_PA23H_GCLK_IO7 _L_(7)
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
#define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23)
/* ========== PORT definition for EIC peripheral ========== */
#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
#define MUX_PA16A_EIC_EXTINT0 _L_(0)
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
#define MUX_PA00A_EIC_EXTINT0 _L_(0)
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
#define MUX_PA17A_EIC_EXTINT1 _L_(0)
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
#define MUX_PA01A_EIC_EXTINT1 _L_(0)
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
#define MUX_PA02A_EIC_EXTINT2 _L_(0)
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
#define MUX_PA18A_EIC_EXTINT2 _L_(0)
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
#define MUX_PA03A_EIC_EXTINT3 _L_(0)
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
#define MUX_PA19A_EIC_EXTINT3 _L_(0)
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
#define MUX_PA04A_EIC_EXTINT4 _L_(0)
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
#define MUX_PA05A_EIC_EXTINT5 _L_(0)
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
#define MUX_PA06A_EIC_EXTINT6 _L_(0)
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
#define MUX_PA22A_EIC_EXTINT6 _L_(0)
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
#define MUX_PA07A_EIC_EXTINT7 _L_(0)
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
#define MUX_PA23A_EIC_EXTINT7 _L_(0)
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
#define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
#define MUX_PA28A_EIC_EXTINT8 _L_(0)
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
#define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28)
#define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
#define MUX_PA09A_EIC_EXTINT9 _L_(0)
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
#define MUX_PA10A_EIC_EXTINT10 _L_(0)
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
#define MUX_PA30A_EIC_EXTINT10 _L_(0)
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30)
#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
#define MUX_PA11A_EIC_EXTINT11 _L_(0)
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
#define MUX_PA31A_EIC_EXTINT11 _L_(0)
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31)
#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
#define MUX_PA24A_EIC_EXTINT12 _L_(0)
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24)
#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
#define MUX_PA25A_EIC_EXTINT13 _L_(0)
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25)
#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
#define MUX_PA14A_EIC_EXTINT14 _L_(0)
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
#define MUX_PA27A_EIC_EXTINT15 _L_(0)
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27)
#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
#define MUX_PA15A_EIC_EXTINT15 _L_(0)
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
#define MUX_PA08A_EIC_NMI _L_(0)
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
#define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
/* ========== PORT definition for SERCOM0 peripheral ========== */
#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
#define MUX_PA04D_SERCOM0_PAD0 _L_(3)
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
#define MUX_PA08C_SERCOM0_PAD0 _L_(2)
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
#define MUX_PA05D_SERCOM0_PAD1 _L_(3)
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
#define MUX_PA09C_SERCOM0_PAD1 _L_(2)
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
#define MUX_PA06D_SERCOM0_PAD2 _L_(3)
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
#define MUX_PA10C_SERCOM0_PAD2 _L_(2)
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
#define MUX_PA07D_SERCOM0_PAD3 _L_(3)
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
#define MUX_PA11C_SERCOM0_PAD3 _L_(2)
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
/* ========== PORT definition for SERCOM1 peripheral ========== */
#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
#define MUX_PA16C_SERCOM1_PAD0 _L_(2)
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
#define MUX_PA00D_SERCOM1_PAD0 _L_(3)
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
#define MUX_PA17C_SERCOM1_PAD1 _L_(2)
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
#define MUX_PA01D_SERCOM1_PAD1 _L_(3)
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
#define MUX_PA30D_SERCOM1_PAD2 _L_(3)
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
#define MUX_PA18C_SERCOM1_PAD2 _L_(2)
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
#define MUX_PA31D_SERCOM1_PAD3 _L_(3)
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
#define MUX_PA19C_SERCOM1_PAD3 _L_(2)
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
/* ========== PORT definition for SERCOM2 peripheral ========== */
#define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
#define MUX_PA08D_SERCOM2_PAD0 _L_(3)
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
#define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8)
#define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
#define MUX_PA09D_SERCOM2_PAD1 _L_(3)
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
#define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9)
#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
#define MUX_PA10D_SERCOM2_PAD2 _L_(3)
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
#define MUX_PA14C_SERCOM2_PAD2 _L_(2)
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
#define MUX_PA11D_SERCOM2_PAD3 _L_(3)
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
#define MUX_PA15C_SERCOM2_PAD3 _L_(2)
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
/* ========== PORT definition for SERCOM3 peripheral ========== */
#define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
#define MUX_PA16D_SERCOM3_PAD0 _L_(3)
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
#define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16)
#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
#define MUX_PA22C_SERCOM3_PAD0 _L_(2)
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
#define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
#define MUX_PA17D_SERCOM3_PAD1 _L_(3)
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
#define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17)
#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
#define MUX_PA23C_SERCOM3_PAD1 _L_(2)
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
#define MUX_PA18D_SERCOM3_PAD2 _L_(3)
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
#define MUX_PA24C_SERCOM3_PAD2 _L_(2)
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
#define MUX_PA19D_SERCOM3_PAD3 _L_(3)
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
#define MUX_PA25C_SERCOM3_PAD3 _L_(2)
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
/* ========== PORT definition for CAN0 peripheral ========== */
#define PIN_PA25G_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux G */
#define MUX_PA25G_CAN0_RX _L_(6)
#define PINMUX_PA25G_CAN0_RX ((PIN_PA25G_CAN0_RX << 16) | MUX_PA25G_CAN0_RX)
#define PORT_PA25G_CAN0_RX (_UL_(1) << 25)
#define PIN_PA24G_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux G */
#define MUX_PA24G_CAN0_TX _L_(6)
#define PINMUX_PA24G_CAN0_TX ((PIN_PA24G_CAN0_TX << 16) | MUX_PA24G_CAN0_TX)
#define PORT_PA24G_CAN0_TX (_UL_(1) << 24)
/* ========== PORT definition for TCC0 peripheral ========== */
#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
#define MUX_PA04E_TCC0_WO0 _L_(4)
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4)
#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
#define MUX_PA08E_TCC0_WO0 _L_(4)
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8)
#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
#define MUX_PA05E_TCC0_WO1 _L_(4)
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5)
#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
#define MUX_PA09E_TCC0_WO1 _L_(4)
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9)
#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
#define MUX_PA10F_TCC0_WO2 _L_(5)
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
#define MUX_PA18F_TCC0_WO2 _L_(5)
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18)
#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
#define MUX_PA11F_TCC0_WO3 _L_(5)
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
#define MUX_PA19F_TCC0_WO3 _L_(5)
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19)
#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
#define MUX_PA22F_TCC0_WO4 _L_(5)
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22)
#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
#define MUX_PA14F_TCC0_WO4 _L_(5)
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14)
#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
#define MUX_PA15F_TCC0_WO5 _L_(5)
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15)
#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
#define MUX_PA23F_TCC0_WO5 _L_(5)
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23)
#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
#define MUX_PA16F_TCC0_WO6 _L_(5)
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16)
#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
#define MUX_PA17F_TCC0_WO7 _L_(5)
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17)
/* ========== PORT definition for TCC1 peripheral ========== */
#define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
#define MUX_PA06E_TCC1_WO0 _L_(4)
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
#define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6)
#define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
#define MUX_PA10E_TCC1_WO0 _L_(4)
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
#define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10)
#define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
#define MUX_PA30E_TCC1_WO0 _L_(4)
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
#define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30)
#define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
#define MUX_PA07E_TCC1_WO1 _L_(4)
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
#define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7)
#define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
#define MUX_PA11E_TCC1_WO1 _L_(4)
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
#define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11)
#define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
#define MUX_PA31E_TCC1_WO1 _L_(4)
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
#define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31)
#define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
#define MUX_PA08F_TCC1_WO2 _L_(5)
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
#define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8)
#define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
#define MUX_PA24F_TCC1_WO2 _L_(5)
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
#define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24)
#define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
#define MUX_PA09F_TCC1_WO3 _L_(5)
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
#define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9)
#define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
#define MUX_PA25F_TCC1_WO3 _L_(5)
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
#define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25)
/* ========== PORT definition for TCC2 peripheral ========== */
#define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
#define MUX_PA16E_TCC2_WO0 _L_(4)
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
#define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16)
#define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
#define MUX_PA00E_TCC2_WO0 _L_(4)
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
#define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0)
#define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
#define MUX_PA17E_TCC2_WO1 _L_(4)
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
#define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17)
#define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
#define MUX_PA01E_TCC2_WO1 _L_(4)
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
#define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1)
/* ========== PORT definition for TC0 peripheral ========== */
#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */
#define MUX_PA22E_TC0_WO0 _L_(4)
#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0)
#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22)
#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */
#define MUX_PA23E_TC0_WO1 _L_(4)
#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1)
#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23)
/* ========== PORT definition for TC1 peripheral ========== */
#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */
#define MUX_PA24E_TC1_WO0 _L_(4)
#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0)
#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24)
#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */
#define MUX_PA25E_TC1_WO1 _L_(4)
#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1)
#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25)
/* ========== PORT definition for TC4 peripheral ========== */
#define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */
#define MUX_PA18E_TC4_WO0 _L_(4)
#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0)
#define PORT_PA18E_TC4_WO0 (_UL_(1) << 18)
#define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */
#define MUX_PA14E_TC4_WO0 _L_(4)
#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0)
#define PORT_PA14E_TC4_WO0 (_UL_(1) << 14)
#define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */
#define MUX_PA19E_TC4_WO1 _L_(4)
#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1)
#define PORT_PA19E_TC4_WO1 (_UL_(1) << 19)
#define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */
#define MUX_PA15E_TC4_WO1 _L_(4)
#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1)
#define PORT_PA15E_TC4_WO1 (_UL_(1) << 15)
/* ========== PORT definition for ADC0 peripheral ========== */
#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
#define MUX_PA02B_ADC0_AIN0 _L_(1)
#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
#define MUX_PA03B_ADC0_AIN1 _L_(1)
#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
#define MUX_PA04B_ADC0_AIN4 _L_(1)
#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
#define MUX_PA05B_ADC0_AIN5 _L_(1)
#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
#define MUX_PA06B_ADC0_AIN6 _L_(1)
#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
#define MUX_PA07B_ADC0_AIN7 _L_(1)
#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
#define MUX_PA08B_ADC0_AIN8 _L_(1)
#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
#define MUX_PA09B_ADC0_AIN9 _L_(1)
#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
#define MUX_PA10B_ADC0_AIN10 _L_(1)
#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
#define MUX_PA11B_ADC0_AIN11 _L_(1)
#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
#define PIN_PA03B_ADC0_VREFP _L_(3) /**< \brief ADC0 signal: VREFP on PA03 mux B */
#define MUX_PA03B_ADC0_VREFP _L_(1)
#define PINMUX_PA03B_ADC0_VREFP ((PIN_PA03B_ADC0_VREFP << 16) | MUX_PA03B_ADC0_VREFP)
#define PORT_PA03B_ADC0_VREFP (_UL_(1) << 3)
/* ========== PORT definition for ADC1 peripheral ========== */
#define PIN_PA08B_ADC1_AIN10 _L_(8) /**< \brief ADC1 signal: AIN10 on PA08 mux B */
#define MUX_PA08B_ADC1_AIN10 _L_(1)
#define PINMUX_PA08B_ADC1_AIN10 ((PIN_PA08B_ADC1_AIN10 << 16) | MUX_PA08B_ADC1_AIN10)
#define PORT_PA08B_ADC1_AIN10 (_UL_(1) << 8)
#define PIN_PA09B_ADC1_AIN11 _L_(9) /**< \brief ADC1 signal: AIN11 on PA09 mux B */
#define MUX_PA09B_ADC1_AIN11 _L_(1)
#define PINMUX_PA09B_ADC1_AIN11 ((PIN_PA09B_ADC1_AIN11 << 16) | MUX_PA09B_ADC1_AIN11)
#define PORT_PA09B_ADC1_AIN11 (_UL_(1) << 9)
/* ========== PORT definition for SDADC peripheral ========== */
#define PIN_PA06B_SDADC_INN0 _L_(6) /**< \brief SDADC signal: INN0 on PA06 mux B */
#define MUX_PA06B_SDADC_INN0 _L_(1)
#define PINMUX_PA06B_SDADC_INN0 ((PIN_PA06B_SDADC_INN0 << 16) | MUX_PA06B_SDADC_INN0)
#define PORT_PA06B_SDADC_INN0 (_UL_(1) << 6)
#define PIN_PA07B_SDADC_INP0 _L_(7) /**< \brief SDADC signal: INP0 on PA07 mux B */
#define MUX_PA07B_SDADC_INP0 _L_(1)
#define PINMUX_PA07B_SDADC_INP0 ((PIN_PA07B_SDADC_INP0 << 16) | MUX_PA07B_SDADC_INP0)
#define PORT_PA07B_SDADC_INP0 (_UL_(1) << 7)
#define PIN_PA04B_SDADC_VREFP _L_(4) /**< \brief SDADC signal: VREFP on PA04 mux B */
#define MUX_PA04B_SDADC_VREFP _L_(1)
#define PINMUX_PA04B_SDADC_VREFP ((PIN_PA04B_SDADC_VREFP << 16) | MUX_PA04B_SDADC_VREFP)
#define PORT_PA04B_SDADC_VREFP (_UL_(1) << 4)
/* ========== PORT definition for AC peripheral ========== */
#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
#define MUX_PA04B_AC_AIN0 _L_(1)
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
#define MUX_PA05B_AC_AIN1 _L_(1)
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
#define MUX_PA06B_AC_AIN2 _L_(1)
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
#define MUX_PA07B_AC_AIN3 _L_(1)
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
#define PIN_PA02B_AC_AIN4 _L_(2) /**< \brief AC signal: AIN4 on PA02 mux B */
#define MUX_PA02B_AC_AIN4 _L_(1)
#define PINMUX_PA02B_AC_AIN4 ((PIN_PA02B_AC_AIN4 << 16) | MUX_PA02B_AC_AIN4)
#define PORT_PA02B_AC_AIN4 (_UL_(1) << 2)
#define PIN_PA03B_AC_AIN5 _L_(3) /**< \brief AC signal: AIN5 on PA03 mux B */
#define MUX_PA03B_AC_AIN5 _L_(1)
#define PINMUX_PA03B_AC_AIN5 ((PIN_PA03B_AC_AIN5 << 16) | MUX_PA03B_AC_AIN5)
#define PORT_PA03B_AC_AIN5 (_UL_(1) << 3)
#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */
#define MUX_PA18H_AC_CMP0 _L_(7)
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18)
#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */
#define MUX_PA19H_AC_CMP1 _L_(7)
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19)
#define PIN_PA00H_AC_CMP2 _L_(0) /**< \brief AC signal: CMP2 on PA00 mux H */
#define MUX_PA00H_AC_CMP2 _L_(7)
#define PINMUX_PA00H_AC_CMP2 ((PIN_PA00H_AC_CMP2 << 16) | MUX_PA00H_AC_CMP2)
#define PORT_PA00H_AC_CMP2 (_UL_(1) << 0)
#define PIN_PA24H_AC_CMP2 _L_(24) /**< \brief AC signal: CMP2 on PA24 mux H */
#define MUX_PA24H_AC_CMP2 _L_(7)
#define PINMUX_PA24H_AC_CMP2 ((PIN_PA24H_AC_CMP2 << 16) | MUX_PA24H_AC_CMP2)
#define PORT_PA24H_AC_CMP2 (_UL_(1) << 24)
#define PIN_PA01H_AC_CMP3 _L_(1) /**< \brief AC signal: CMP3 on PA01 mux H */
#define MUX_PA01H_AC_CMP3 _L_(7)
#define PINMUX_PA01H_AC_CMP3 ((PIN_PA01H_AC_CMP3 << 16) | MUX_PA01H_AC_CMP3)
#define PORT_PA01H_AC_CMP3 (_UL_(1) << 1)
#define PIN_PA25H_AC_CMP3 _L_(25) /**< \brief AC signal: CMP3 on PA25 mux H */
#define MUX_PA25H_AC_CMP3 _L_(7)
#define PINMUX_PA25H_AC_CMP3 ((PIN_PA25H_AC_CMP3 << 16) | MUX_PA25H_AC_CMP3)
#define PORT_PA25H_AC_CMP3 (_UL_(1) << 25)
/* ========== PORT definition for DAC peripheral ========== */
#define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */
#define MUX_PA02B_DAC_VOUT _L_(1)
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
#define PORT_PA02B_DAC_VOUT (_UL_(1) << 2)
#define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */
#define MUX_PA03B_DAC_VREFP _L_(1)
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
#define PORT_PA03B_DAC_VREFP (_UL_(1) << 3)
/* ========== PORT definition for CCL peripheral ========== */
#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */
#define MUX_PA04I_CCL_IN0 _L_(8)
#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0)
#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4)
#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */
#define MUX_PA16I_CCL_IN0 _L_(8)
#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0)
#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16)
#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */
#define MUX_PA05I_CCL_IN1 _L_(8)
#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1)
#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5)
#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */
#define MUX_PA17I_CCL_IN1 _L_(8)
#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1)
#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17)
#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */
#define MUX_PA06I_CCL_IN2 _L_(8)
#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2)
#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6)
#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */
#define MUX_PA18I_CCL_IN2 _L_(8)
#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2)
#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18)
#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */
#define MUX_PA08I_CCL_IN3 _L_(8)
#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3)
#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8)
#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */
#define MUX_PA30I_CCL_IN3 _L_(8)
#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3)
#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30)
#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */
#define MUX_PA09I_CCL_IN4 _L_(8)
#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4)
#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9)
#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */
#define MUX_PA10I_CCL_IN5 _L_(8)
#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5)
#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10)
#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */
#define MUX_PA22I_CCL_IN6 _L_(8)
#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6)
#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22)
#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */
#define MUX_PA23I_CCL_IN7 _L_(8)
#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7)
#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23)
#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */
#define MUX_PA24I_CCL_IN8 _L_(8)
#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8)
#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24)
#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */
#define MUX_PA07I_CCL_OUT0 _L_(8)
#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0)
#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7)
#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */
#define MUX_PA19I_CCL_OUT0 _L_(8)
#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0)
#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19)
#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */
#define MUX_PA11I_CCL_OUT1 _L_(8)
#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1)
#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11)
#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */
#define MUX_PA31I_CCL_OUT1 _L_(8)
#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1)
#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31)
#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */
#define MUX_PA25I_CCL_OUT2 _L_(8)
#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2)
#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25)
#endif /* _SAMC21E15A_PIO_ */

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/**
* \file
*
* \brief Peripheral I/O description for SAMC21E16A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21E16A_PIO_
#define _SAMC21E16A_PIO_
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
#define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
/* ========== PORT definition for RSTC peripheral ========== */
#define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */
#define MUX_PA00A_RSTC_EXTWAKE0 _L_(0)
#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0)
#define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0)
#define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */
#define MUX_PA01A_RSTC_EXTWAKE1 _L_(0)
#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1)
#define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1)
#define PIN_PA02A_RSTC_EXTWAKE2 _L_(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */
#define MUX_PA02A_RSTC_EXTWAKE2 _L_(0)
#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2)
#define PORT_PA02A_RSTC_EXTWAKE2 (_UL_(1) << 2)
#define PIN_PA03A_RSTC_EXTWAKE3 _L_(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */
#define MUX_PA03A_RSTC_EXTWAKE3 _L_(0)
#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3)
#define PORT_PA03A_RSTC_EXTWAKE3 (_UL_(1) << 3)
#define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */
#define MUX_PA04A_RSTC_EXTWAKE4 _L_(0)
#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4)
#define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4)
#define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */
#define MUX_PA05A_RSTC_EXTWAKE5 _L_(0)
#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5)
#define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5)
#define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */
#define MUX_PA06A_RSTC_EXTWAKE6 _L_(0)
#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6)
#define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6)
#define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */
#define MUX_PA07A_RSTC_EXTWAKE7 _L_(0)
#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7)
#define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7)
#define PIN_PA08A_RSTC_EXTWAKE8 _L_(8) /**< \brief RSTC signal: EXTWAKE8 on PA08 mux A */
#define MUX_PA08A_RSTC_EXTWAKE8 _L_(0)
#define PINMUX_PA08A_RSTC_EXTWAKE8 ((PIN_PA08A_RSTC_EXTWAKE8 << 16) | MUX_PA08A_RSTC_EXTWAKE8)
#define PORT_PA08A_RSTC_EXTWAKE8 (_UL_(1) << 8)
#define PIN_PA09A_RSTC_EXTWAKE9 _L_(9) /**< \brief RSTC signal: EXTWAKE9 on PA09 mux A */
#define MUX_PA09A_RSTC_EXTWAKE9 _L_(0)
#define PINMUX_PA09A_RSTC_EXTWAKE9 ((PIN_PA09A_RSTC_EXTWAKE9 << 16) | MUX_PA09A_RSTC_EXTWAKE9)
#define PORT_PA09A_RSTC_EXTWAKE9 (_UL_(1) << 9)
#define PIN_PA10A_RSTC_EXTWAKE10 _L_(10) /**< \brief RSTC signal: EXTWAKE10 on PA10 mux A */
#define MUX_PA10A_RSTC_EXTWAKE10 _L_(0)
#define PINMUX_PA10A_RSTC_EXTWAKE10 ((PIN_PA10A_RSTC_EXTWAKE10 << 16) | MUX_PA10A_RSTC_EXTWAKE10)
#define PORT_PA10A_RSTC_EXTWAKE10 (_UL_(1) << 10)
#define PIN_PA11A_RSTC_EXTWAKE11 _L_(11) /**< \brief RSTC signal: EXTWAKE11 on PA11 mux A */
#define MUX_PA11A_RSTC_EXTWAKE11 _L_(0)
#define PINMUX_PA11A_RSTC_EXTWAKE11 ((PIN_PA11A_RSTC_EXTWAKE11 << 16) | MUX_PA11A_RSTC_EXTWAKE11)
#define PORT_PA11A_RSTC_EXTWAKE11 (_UL_(1) << 11)
#define PIN_PA14A_RSTC_EXTWAKE14 _L_(14) /**< \brief RSTC signal: EXTWAKE14 on PA14 mux A */
#define MUX_PA14A_RSTC_EXTWAKE14 _L_(0)
#define PINMUX_PA14A_RSTC_EXTWAKE14 ((PIN_PA14A_RSTC_EXTWAKE14 << 16) | MUX_PA14A_RSTC_EXTWAKE14)
#define PORT_PA14A_RSTC_EXTWAKE14 (_UL_(1) << 14)
#define PIN_PA15A_RSTC_EXTWAKE15 _L_(15) /**< \brief RSTC signal: EXTWAKE15 on PA15 mux A */
#define MUX_PA15A_RSTC_EXTWAKE15 _L_(0)
#define PINMUX_PA15A_RSTC_EXTWAKE15 ((PIN_PA15A_RSTC_EXTWAKE15 << 16) | MUX_PA15A_RSTC_EXTWAKE15)
#define PORT_PA15A_RSTC_EXTWAKE15 (_UL_(1) << 15)
/* ========== PORT definition for GCLK peripheral ========== */
#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
#define MUX_PA14H_GCLK_IO0 _L_(7)
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14)
#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
#define MUX_PA27H_GCLK_IO0 _L_(7)
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27)
#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
#define MUX_PA30H_GCLK_IO0 _L_(7)
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30)
#define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
#define MUX_PA28H_GCLK_IO0 _L_(7)
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
#define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28)
#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
#define MUX_PA15H_GCLK_IO1 _L_(7)
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15)
#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
#define MUX_PA16H_GCLK_IO2 _L_(7)
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16)
#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
#define MUX_PA17H_GCLK_IO3 _L_(7)
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17)
#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
#define MUX_PA10H_GCLK_IO4 _L_(7)
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10)
#define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
#define MUX_PA11H_GCLK_IO5 _L_(7)
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
#define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11)
#define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
#define MUX_PA22H_GCLK_IO6 _L_(7)
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
#define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22)
#define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
#define MUX_PA23H_GCLK_IO7 _L_(7)
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
#define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23)
/* ========== PORT definition for EIC peripheral ========== */
#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
#define MUX_PA16A_EIC_EXTINT0 _L_(0)
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
#define MUX_PA00A_EIC_EXTINT0 _L_(0)
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
#define MUX_PA17A_EIC_EXTINT1 _L_(0)
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
#define MUX_PA01A_EIC_EXTINT1 _L_(0)
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
#define MUX_PA02A_EIC_EXTINT2 _L_(0)
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
#define MUX_PA18A_EIC_EXTINT2 _L_(0)
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
#define MUX_PA03A_EIC_EXTINT3 _L_(0)
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
#define MUX_PA19A_EIC_EXTINT3 _L_(0)
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
#define MUX_PA04A_EIC_EXTINT4 _L_(0)
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
#define MUX_PA05A_EIC_EXTINT5 _L_(0)
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
#define MUX_PA06A_EIC_EXTINT6 _L_(0)
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
#define MUX_PA22A_EIC_EXTINT6 _L_(0)
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
#define MUX_PA07A_EIC_EXTINT7 _L_(0)
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
#define MUX_PA23A_EIC_EXTINT7 _L_(0)
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
#define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
#define MUX_PA28A_EIC_EXTINT8 _L_(0)
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
#define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28)
#define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
#define MUX_PA09A_EIC_EXTINT9 _L_(0)
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
#define MUX_PA10A_EIC_EXTINT10 _L_(0)
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
#define MUX_PA30A_EIC_EXTINT10 _L_(0)
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30)
#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
#define MUX_PA11A_EIC_EXTINT11 _L_(0)
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
#define MUX_PA31A_EIC_EXTINT11 _L_(0)
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31)
#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
#define MUX_PA24A_EIC_EXTINT12 _L_(0)
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24)
#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
#define MUX_PA25A_EIC_EXTINT13 _L_(0)
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25)
#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
#define MUX_PA14A_EIC_EXTINT14 _L_(0)
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
#define MUX_PA27A_EIC_EXTINT15 _L_(0)
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27)
#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
#define MUX_PA15A_EIC_EXTINT15 _L_(0)
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
#define MUX_PA08A_EIC_NMI _L_(0)
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
#define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
/* ========== PORT definition for SERCOM0 peripheral ========== */
#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
#define MUX_PA04D_SERCOM0_PAD0 _L_(3)
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
#define MUX_PA08C_SERCOM0_PAD0 _L_(2)
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
#define MUX_PA05D_SERCOM0_PAD1 _L_(3)
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
#define MUX_PA09C_SERCOM0_PAD1 _L_(2)
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
#define MUX_PA06D_SERCOM0_PAD2 _L_(3)
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
#define MUX_PA10C_SERCOM0_PAD2 _L_(2)
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
#define MUX_PA07D_SERCOM0_PAD3 _L_(3)
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
#define MUX_PA11C_SERCOM0_PAD3 _L_(2)
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
/* ========== PORT definition for SERCOM1 peripheral ========== */
#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
#define MUX_PA16C_SERCOM1_PAD0 _L_(2)
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
#define MUX_PA00D_SERCOM1_PAD0 _L_(3)
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
#define MUX_PA17C_SERCOM1_PAD1 _L_(2)
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
#define MUX_PA01D_SERCOM1_PAD1 _L_(3)
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
#define MUX_PA30D_SERCOM1_PAD2 _L_(3)
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
#define MUX_PA18C_SERCOM1_PAD2 _L_(2)
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
#define MUX_PA31D_SERCOM1_PAD3 _L_(3)
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
#define MUX_PA19C_SERCOM1_PAD3 _L_(2)
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
/* ========== PORT definition for SERCOM2 peripheral ========== */
#define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
#define MUX_PA08D_SERCOM2_PAD0 _L_(3)
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
#define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8)
#define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
#define MUX_PA09D_SERCOM2_PAD1 _L_(3)
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
#define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9)
#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
#define MUX_PA10D_SERCOM2_PAD2 _L_(3)
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
#define MUX_PA14C_SERCOM2_PAD2 _L_(2)
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
#define MUX_PA11D_SERCOM2_PAD3 _L_(3)
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
#define MUX_PA15C_SERCOM2_PAD3 _L_(2)
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
/* ========== PORT definition for SERCOM3 peripheral ========== */
#define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
#define MUX_PA16D_SERCOM3_PAD0 _L_(3)
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
#define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16)
#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
#define MUX_PA22C_SERCOM3_PAD0 _L_(2)
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
#define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
#define MUX_PA17D_SERCOM3_PAD1 _L_(3)
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
#define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17)
#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
#define MUX_PA23C_SERCOM3_PAD1 _L_(2)
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
#define MUX_PA18D_SERCOM3_PAD2 _L_(3)
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
#define MUX_PA24C_SERCOM3_PAD2 _L_(2)
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
#define MUX_PA19D_SERCOM3_PAD3 _L_(3)
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
#define MUX_PA25C_SERCOM3_PAD3 _L_(2)
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
/* ========== PORT definition for CAN0 peripheral ========== */
#define PIN_PA25G_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux G */
#define MUX_PA25G_CAN0_RX _L_(6)
#define PINMUX_PA25G_CAN0_RX ((PIN_PA25G_CAN0_RX << 16) | MUX_PA25G_CAN0_RX)
#define PORT_PA25G_CAN0_RX (_UL_(1) << 25)
#define PIN_PA24G_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux G */
#define MUX_PA24G_CAN0_TX _L_(6)
#define PINMUX_PA24G_CAN0_TX ((PIN_PA24G_CAN0_TX << 16) | MUX_PA24G_CAN0_TX)
#define PORT_PA24G_CAN0_TX (_UL_(1) << 24)
/* ========== PORT definition for TCC0 peripheral ========== */
#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
#define MUX_PA04E_TCC0_WO0 _L_(4)
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4)
#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
#define MUX_PA08E_TCC0_WO0 _L_(4)
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8)
#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
#define MUX_PA05E_TCC0_WO1 _L_(4)
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5)
#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
#define MUX_PA09E_TCC0_WO1 _L_(4)
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9)
#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
#define MUX_PA10F_TCC0_WO2 _L_(5)
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
#define MUX_PA18F_TCC0_WO2 _L_(5)
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18)
#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
#define MUX_PA11F_TCC0_WO3 _L_(5)
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
#define MUX_PA19F_TCC0_WO3 _L_(5)
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19)
#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
#define MUX_PA22F_TCC0_WO4 _L_(5)
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22)
#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
#define MUX_PA14F_TCC0_WO4 _L_(5)
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14)
#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
#define MUX_PA15F_TCC0_WO5 _L_(5)
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15)
#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
#define MUX_PA23F_TCC0_WO5 _L_(5)
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23)
#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
#define MUX_PA16F_TCC0_WO6 _L_(5)
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16)
#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
#define MUX_PA17F_TCC0_WO7 _L_(5)
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17)
/* ========== PORT definition for TCC1 peripheral ========== */
#define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
#define MUX_PA06E_TCC1_WO0 _L_(4)
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
#define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6)
#define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
#define MUX_PA10E_TCC1_WO0 _L_(4)
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
#define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10)
#define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
#define MUX_PA30E_TCC1_WO0 _L_(4)
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
#define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30)
#define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
#define MUX_PA07E_TCC1_WO1 _L_(4)
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
#define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7)
#define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
#define MUX_PA11E_TCC1_WO1 _L_(4)
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
#define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11)
#define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
#define MUX_PA31E_TCC1_WO1 _L_(4)
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
#define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31)
#define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
#define MUX_PA08F_TCC1_WO2 _L_(5)
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
#define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8)
#define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
#define MUX_PA24F_TCC1_WO2 _L_(5)
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
#define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24)
#define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
#define MUX_PA09F_TCC1_WO3 _L_(5)
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
#define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9)
#define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
#define MUX_PA25F_TCC1_WO3 _L_(5)
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
#define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25)
/* ========== PORT definition for TCC2 peripheral ========== */
#define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
#define MUX_PA16E_TCC2_WO0 _L_(4)
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
#define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16)
#define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
#define MUX_PA00E_TCC2_WO0 _L_(4)
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
#define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0)
#define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
#define MUX_PA17E_TCC2_WO1 _L_(4)
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
#define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17)
#define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
#define MUX_PA01E_TCC2_WO1 _L_(4)
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
#define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1)
/* ========== PORT definition for TC0 peripheral ========== */
#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */
#define MUX_PA22E_TC0_WO0 _L_(4)
#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0)
#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22)
#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */
#define MUX_PA23E_TC0_WO1 _L_(4)
#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1)
#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23)
/* ========== PORT definition for TC1 peripheral ========== */
#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */
#define MUX_PA24E_TC1_WO0 _L_(4)
#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0)
#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24)
#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */
#define MUX_PA25E_TC1_WO1 _L_(4)
#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1)
#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25)
/* ========== PORT definition for TC4 peripheral ========== */
#define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */
#define MUX_PA18E_TC4_WO0 _L_(4)
#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0)
#define PORT_PA18E_TC4_WO0 (_UL_(1) << 18)
#define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */
#define MUX_PA14E_TC4_WO0 _L_(4)
#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0)
#define PORT_PA14E_TC4_WO0 (_UL_(1) << 14)
#define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */
#define MUX_PA19E_TC4_WO1 _L_(4)
#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1)
#define PORT_PA19E_TC4_WO1 (_UL_(1) << 19)
#define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */
#define MUX_PA15E_TC4_WO1 _L_(4)
#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1)
#define PORT_PA15E_TC4_WO1 (_UL_(1) << 15)
/* ========== PORT definition for ADC0 peripheral ========== */
#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
#define MUX_PA02B_ADC0_AIN0 _L_(1)
#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
#define MUX_PA03B_ADC0_AIN1 _L_(1)
#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
#define MUX_PA04B_ADC0_AIN4 _L_(1)
#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
#define MUX_PA05B_ADC0_AIN5 _L_(1)
#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
#define MUX_PA06B_ADC0_AIN6 _L_(1)
#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
#define MUX_PA07B_ADC0_AIN7 _L_(1)
#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
#define MUX_PA08B_ADC0_AIN8 _L_(1)
#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
#define MUX_PA09B_ADC0_AIN9 _L_(1)
#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
#define MUX_PA10B_ADC0_AIN10 _L_(1)
#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
#define MUX_PA11B_ADC0_AIN11 _L_(1)
#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
#define PIN_PA03B_ADC0_VREFP _L_(3) /**< \brief ADC0 signal: VREFP on PA03 mux B */
#define MUX_PA03B_ADC0_VREFP _L_(1)
#define PINMUX_PA03B_ADC0_VREFP ((PIN_PA03B_ADC0_VREFP << 16) | MUX_PA03B_ADC0_VREFP)
#define PORT_PA03B_ADC0_VREFP (_UL_(1) << 3)
/* ========== PORT definition for ADC1 peripheral ========== */
#define PIN_PA08B_ADC1_AIN10 _L_(8) /**< \brief ADC1 signal: AIN10 on PA08 mux B */
#define MUX_PA08B_ADC1_AIN10 _L_(1)
#define PINMUX_PA08B_ADC1_AIN10 ((PIN_PA08B_ADC1_AIN10 << 16) | MUX_PA08B_ADC1_AIN10)
#define PORT_PA08B_ADC1_AIN10 (_UL_(1) << 8)
#define PIN_PA09B_ADC1_AIN11 _L_(9) /**< \brief ADC1 signal: AIN11 on PA09 mux B */
#define MUX_PA09B_ADC1_AIN11 _L_(1)
#define PINMUX_PA09B_ADC1_AIN11 ((PIN_PA09B_ADC1_AIN11 << 16) | MUX_PA09B_ADC1_AIN11)
#define PORT_PA09B_ADC1_AIN11 (_UL_(1) << 9)
/* ========== PORT definition for SDADC peripheral ========== */
#define PIN_PA06B_SDADC_INN0 _L_(6) /**< \brief SDADC signal: INN0 on PA06 mux B */
#define MUX_PA06B_SDADC_INN0 _L_(1)
#define PINMUX_PA06B_SDADC_INN0 ((PIN_PA06B_SDADC_INN0 << 16) | MUX_PA06B_SDADC_INN0)
#define PORT_PA06B_SDADC_INN0 (_UL_(1) << 6)
#define PIN_PA07B_SDADC_INP0 _L_(7) /**< \brief SDADC signal: INP0 on PA07 mux B */
#define MUX_PA07B_SDADC_INP0 _L_(1)
#define PINMUX_PA07B_SDADC_INP0 ((PIN_PA07B_SDADC_INP0 << 16) | MUX_PA07B_SDADC_INP0)
#define PORT_PA07B_SDADC_INP0 (_UL_(1) << 7)
#define PIN_PA04B_SDADC_VREFP _L_(4) /**< \brief SDADC signal: VREFP on PA04 mux B */
#define MUX_PA04B_SDADC_VREFP _L_(1)
#define PINMUX_PA04B_SDADC_VREFP ((PIN_PA04B_SDADC_VREFP << 16) | MUX_PA04B_SDADC_VREFP)
#define PORT_PA04B_SDADC_VREFP (_UL_(1) << 4)
/* ========== PORT definition for AC peripheral ========== */
#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
#define MUX_PA04B_AC_AIN0 _L_(1)
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
#define MUX_PA05B_AC_AIN1 _L_(1)
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
#define MUX_PA06B_AC_AIN2 _L_(1)
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
#define MUX_PA07B_AC_AIN3 _L_(1)
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
#define PIN_PA02B_AC_AIN4 _L_(2) /**< \brief AC signal: AIN4 on PA02 mux B */
#define MUX_PA02B_AC_AIN4 _L_(1)
#define PINMUX_PA02B_AC_AIN4 ((PIN_PA02B_AC_AIN4 << 16) | MUX_PA02B_AC_AIN4)
#define PORT_PA02B_AC_AIN4 (_UL_(1) << 2)
#define PIN_PA03B_AC_AIN5 _L_(3) /**< \brief AC signal: AIN5 on PA03 mux B */
#define MUX_PA03B_AC_AIN5 _L_(1)
#define PINMUX_PA03B_AC_AIN5 ((PIN_PA03B_AC_AIN5 << 16) | MUX_PA03B_AC_AIN5)
#define PORT_PA03B_AC_AIN5 (_UL_(1) << 3)
#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */
#define MUX_PA18H_AC_CMP0 _L_(7)
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18)
#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */
#define MUX_PA19H_AC_CMP1 _L_(7)
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19)
#define PIN_PA00H_AC_CMP2 _L_(0) /**< \brief AC signal: CMP2 on PA00 mux H */
#define MUX_PA00H_AC_CMP2 _L_(7)
#define PINMUX_PA00H_AC_CMP2 ((PIN_PA00H_AC_CMP2 << 16) | MUX_PA00H_AC_CMP2)
#define PORT_PA00H_AC_CMP2 (_UL_(1) << 0)
#define PIN_PA24H_AC_CMP2 _L_(24) /**< \brief AC signal: CMP2 on PA24 mux H */
#define MUX_PA24H_AC_CMP2 _L_(7)
#define PINMUX_PA24H_AC_CMP2 ((PIN_PA24H_AC_CMP2 << 16) | MUX_PA24H_AC_CMP2)
#define PORT_PA24H_AC_CMP2 (_UL_(1) << 24)
#define PIN_PA01H_AC_CMP3 _L_(1) /**< \brief AC signal: CMP3 on PA01 mux H */
#define MUX_PA01H_AC_CMP3 _L_(7)
#define PINMUX_PA01H_AC_CMP3 ((PIN_PA01H_AC_CMP3 << 16) | MUX_PA01H_AC_CMP3)
#define PORT_PA01H_AC_CMP3 (_UL_(1) << 1)
#define PIN_PA25H_AC_CMP3 _L_(25) /**< \brief AC signal: CMP3 on PA25 mux H */
#define MUX_PA25H_AC_CMP3 _L_(7)
#define PINMUX_PA25H_AC_CMP3 ((PIN_PA25H_AC_CMP3 << 16) | MUX_PA25H_AC_CMP3)
#define PORT_PA25H_AC_CMP3 (_UL_(1) << 25)
/* ========== PORT definition for DAC peripheral ========== */
#define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */
#define MUX_PA02B_DAC_VOUT _L_(1)
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
#define PORT_PA02B_DAC_VOUT (_UL_(1) << 2)
#define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */
#define MUX_PA03B_DAC_VREFP _L_(1)
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
#define PORT_PA03B_DAC_VREFP (_UL_(1) << 3)
/* ========== PORT definition for CCL peripheral ========== */
#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */
#define MUX_PA04I_CCL_IN0 _L_(8)
#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0)
#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4)
#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */
#define MUX_PA16I_CCL_IN0 _L_(8)
#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0)
#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16)
#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */
#define MUX_PA05I_CCL_IN1 _L_(8)
#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1)
#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5)
#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */
#define MUX_PA17I_CCL_IN1 _L_(8)
#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1)
#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17)
#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */
#define MUX_PA06I_CCL_IN2 _L_(8)
#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2)
#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6)
#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */
#define MUX_PA18I_CCL_IN2 _L_(8)
#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2)
#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18)
#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */
#define MUX_PA08I_CCL_IN3 _L_(8)
#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3)
#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8)
#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */
#define MUX_PA30I_CCL_IN3 _L_(8)
#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3)
#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30)
#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */
#define MUX_PA09I_CCL_IN4 _L_(8)
#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4)
#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9)
#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */
#define MUX_PA10I_CCL_IN5 _L_(8)
#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5)
#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10)
#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */
#define MUX_PA22I_CCL_IN6 _L_(8)
#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6)
#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22)
#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */
#define MUX_PA23I_CCL_IN7 _L_(8)
#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7)
#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23)
#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */
#define MUX_PA24I_CCL_IN8 _L_(8)
#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8)
#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24)
#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */
#define MUX_PA07I_CCL_OUT0 _L_(8)
#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0)
#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7)
#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */
#define MUX_PA19I_CCL_OUT0 _L_(8)
#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0)
#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19)
#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */
#define MUX_PA11I_CCL_OUT1 _L_(8)
#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1)
#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11)
#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */
#define MUX_PA31I_CCL_OUT1 _L_(8)
#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1)
#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31)
#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */
#define MUX_PA25I_CCL_OUT2 _L_(8)
#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2)
#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25)
#endif /* _SAMC21E16A_PIO_ */

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/**
* \file
*
* \brief Peripheral I/O description for SAMC21E17A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21E17A_PIO_
#define _SAMC21E17A_PIO_
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
#define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
/* ========== PORT definition for RSTC peripheral ========== */
#define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */
#define MUX_PA00A_RSTC_EXTWAKE0 _L_(0)
#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0)
#define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0)
#define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */
#define MUX_PA01A_RSTC_EXTWAKE1 _L_(0)
#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1)
#define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1)
#define PIN_PA02A_RSTC_EXTWAKE2 _L_(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */
#define MUX_PA02A_RSTC_EXTWAKE2 _L_(0)
#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2)
#define PORT_PA02A_RSTC_EXTWAKE2 (_UL_(1) << 2)
#define PIN_PA03A_RSTC_EXTWAKE3 _L_(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */
#define MUX_PA03A_RSTC_EXTWAKE3 _L_(0)
#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3)
#define PORT_PA03A_RSTC_EXTWAKE3 (_UL_(1) << 3)
#define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */
#define MUX_PA04A_RSTC_EXTWAKE4 _L_(0)
#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4)
#define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4)
#define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */
#define MUX_PA05A_RSTC_EXTWAKE5 _L_(0)
#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5)
#define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5)
#define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */
#define MUX_PA06A_RSTC_EXTWAKE6 _L_(0)
#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6)
#define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6)
#define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */
#define MUX_PA07A_RSTC_EXTWAKE7 _L_(0)
#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7)
#define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7)
#define PIN_PA08A_RSTC_EXTWAKE8 _L_(8) /**< \brief RSTC signal: EXTWAKE8 on PA08 mux A */
#define MUX_PA08A_RSTC_EXTWAKE8 _L_(0)
#define PINMUX_PA08A_RSTC_EXTWAKE8 ((PIN_PA08A_RSTC_EXTWAKE8 << 16) | MUX_PA08A_RSTC_EXTWAKE8)
#define PORT_PA08A_RSTC_EXTWAKE8 (_UL_(1) << 8)
#define PIN_PA09A_RSTC_EXTWAKE9 _L_(9) /**< \brief RSTC signal: EXTWAKE9 on PA09 mux A */
#define MUX_PA09A_RSTC_EXTWAKE9 _L_(0)
#define PINMUX_PA09A_RSTC_EXTWAKE9 ((PIN_PA09A_RSTC_EXTWAKE9 << 16) | MUX_PA09A_RSTC_EXTWAKE9)
#define PORT_PA09A_RSTC_EXTWAKE9 (_UL_(1) << 9)
#define PIN_PA10A_RSTC_EXTWAKE10 _L_(10) /**< \brief RSTC signal: EXTWAKE10 on PA10 mux A */
#define MUX_PA10A_RSTC_EXTWAKE10 _L_(0)
#define PINMUX_PA10A_RSTC_EXTWAKE10 ((PIN_PA10A_RSTC_EXTWAKE10 << 16) | MUX_PA10A_RSTC_EXTWAKE10)
#define PORT_PA10A_RSTC_EXTWAKE10 (_UL_(1) << 10)
#define PIN_PA11A_RSTC_EXTWAKE11 _L_(11) /**< \brief RSTC signal: EXTWAKE11 on PA11 mux A */
#define MUX_PA11A_RSTC_EXTWAKE11 _L_(0)
#define PINMUX_PA11A_RSTC_EXTWAKE11 ((PIN_PA11A_RSTC_EXTWAKE11 << 16) | MUX_PA11A_RSTC_EXTWAKE11)
#define PORT_PA11A_RSTC_EXTWAKE11 (_UL_(1) << 11)
#define PIN_PA14A_RSTC_EXTWAKE14 _L_(14) /**< \brief RSTC signal: EXTWAKE14 on PA14 mux A */
#define MUX_PA14A_RSTC_EXTWAKE14 _L_(0)
#define PINMUX_PA14A_RSTC_EXTWAKE14 ((PIN_PA14A_RSTC_EXTWAKE14 << 16) | MUX_PA14A_RSTC_EXTWAKE14)
#define PORT_PA14A_RSTC_EXTWAKE14 (_UL_(1) << 14)
#define PIN_PA15A_RSTC_EXTWAKE15 _L_(15) /**< \brief RSTC signal: EXTWAKE15 on PA15 mux A */
#define MUX_PA15A_RSTC_EXTWAKE15 _L_(0)
#define PINMUX_PA15A_RSTC_EXTWAKE15 ((PIN_PA15A_RSTC_EXTWAKE15 << 16) | MUX_PA15A_RSTC_EXTWAKE15)
#define PORT_PA15A_RSTC_EXTWAKE15 (_UL_(1) << 15)
/* ========== PORT definition for GCLK peripheral ========== */
#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
#define MUX_PA14H_GCLK_IO0 _L_(7)
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14)
#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
#define MUX_PA27H_GCLK_IO0 _L_(7)
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27)
#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
#define MUX_PA30H_GCLK_IO0 _L_(7)
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30)
#define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
#define MUX_PA28H_GCLK_IO0 _L_(7)
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
#define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28)
#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
#define MUX_PA15H_GCLK_IO1 _L_(7)
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15)
#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
#define MUX_PA16H_GCLK_IO2 _L_(7)
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16)
#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
#define MUX_PA17H_GCLK_IO3 _L_(7)
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17)
#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
#define MUX_PA10H_GCLK_IO4 _L_(7)
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10)
#define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
#define MUX_PA11H_GCLK_IO5 _L_(7)
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
#define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11)
#define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
#define MUX_PA22H_GCLK_IO6 _L_(7)
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
#define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22)
#define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
#define MUX_PA23H_GCLK_IO7 _L_(7)
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
#define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23)
/* ========== PORT definition for EIC peripheral ========== */
#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
#define MUX_PA16A_EIC_EXTINT0 _L_(0)
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
#define MUX_PA00A_EIC_EXTINT0 _L_(0)
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
#define MUX_PA17A_EIC_EXTINT1 _L_(0)
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
#define MUX_PA01A_EIC_EXTINT1 _L_(0)
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
#define MUX_PA02A_EIC_EXTINT2 _L_(0)
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
#define MUX_PA18A_EIC_EXTINT2 _L_(0)
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
#define MUX_PA03A_EIC_EXTINT3 _L_(0)
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
#define MUX_PA19A_EIC_EXTINT3 _L_(0)
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
#define MUX_PA04A_EIC_EXTINT4 _L_(0)
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
#define MUX_PA05A_EIC_EXTINT5 _L_(0)
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
#define MUX_PA06A_EIC_EXTINT6 _L_(0)
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
#define MUX_PA22A_EIC_EXTINT6 _L_(0)
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
#define MUX_PA07A_EIC_EXTINT7 _L_(0)
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
#define MUX_PA23A_EIC_EXTINT7 _L_(0)
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
#define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
#define MUX_PA28A_EIC_EXTINT8 _L_(0)
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
#define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28)
#define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
#define MUX_PA09A_EIC_EXTINT9 _L_(0)
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
#define MUX_PA10A_EIC_EXTINT10 _L_(0)
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
#define MUX_PA30A_EIC_EXTINT10 _L_(0)
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30)
#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
#define MUX_PA11A_EIC_EXTINT11 _L_(0)
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
#define MUX_PA31A_EIC_EXTINT11 _L_(0)
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31)
#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
#define MUX_PA24A_EIC_EXTINT12 _L_(0)
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24)
#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
#define MUX_PA25A_EIC_EXTINT13 _L_(0)
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25)
#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
#define MUX_PA14A_EIC_EXTINT14 _L_(0)
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
#define MUX_PA27A_EIC_EXTINT15 _L_(0)
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27)
#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
#define MUX_PA15A_EIC_EXTINT15 _L_(0)
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
#define MUX_PA08A_EIC_NMI _L_(0)
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
#define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
/* ========== PORT definition for SERCOM0 peripheral ========== */
#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
#define MUX_PA04D_SERCOM0_PAD0 _L_(3)
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
#define MUX_PA08C_SERCOM0_PAD0 _L_(2)
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
#define MUX_PA05D_SERCOM0_PAD1 _L_(3)
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
#define MUX_PA09C_SERCOM0_PAD1 _L_(2)
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
#define MUX_PA06D_SERCOM0_PAD2 _L_(3)
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
#define MUX_PA10C_SERCOM0_PAD2 _L_(2)
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
#define MUX_PA07D_SERCOM0_PAD3 _L_(3)
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
#define MUX_PA11C_SERCOM0_PAD3 _L_(2)
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
/* ========== PORT definition for SERCOM1 peripheral ========== */
#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
#define MUX_PA16C_SERCOM1_PAD0 _L_(2)
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
#define MUX_PA00D_SERCOM1_PAD0 _L_(3)
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
#define MUX_PA17C_SERCOM1_PAD1 _L_(2)
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
#define MUX_PA01D_SERCOM1_PAD1 _L_(3)
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
#define MUX_PA30D_SERCOM1_PAD2 _L_(3)
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
#define MUX_PA18C_SERCOM1_PAD2 _L_(2)
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
#define MUX_PA31D_SERCOM1_PAD3 _L_(3)
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
#define MUX_PA19C_SERCOM1_PAD3 _L_(2)
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
/* ========== PORT definition for SERCOM2 peripheral ========== */
#define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
#define MUX_PA08D_SERCOM2_PAD0 _L_(3)
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
#define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8)
#define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
#define MUX_PA09D_SERCOM2_PAD1 _L_(3)
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
#define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9)
#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
#define MUX_PA10D_SERCOM2_PAD2 _L_(3)
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
#define MUX_PA14C_SERCOM2_PAD2 _L_(2)
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
#define MUX_PA11D_SERCOM2_PAD3 _L_(3)
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
#define MUX_PA15C_SERCOM2_PAD3 _L_(2)
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
/* ========== PORT definition for SERCOM3 peripheral ========== */
#define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
#define MUX_PA16D_SERCOM3_PAD0 _L_(3)
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
#define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16)
#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
#define MUX_PA22C_SERCOM3_PAD0 _L_(2)
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
#define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
#define MUX_PA17D_SERCOM3_PAD1 _L_(3)
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
#define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17)
#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
#define MUX_PA23C_SERCOM3_PAD1 _L_(2)
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
#define MUX_PA18D_SERCOM3_PAD2 _L_(3)
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
#define MUX_PA24C_SERCOM3_PAD2 _L_(2)
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
#define MUX_PA19D_SERCOM3_PAD3 _L_(3)
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
#define MUX_PA25C_SERCOM3_PAD3 _L_(2)
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
/* ========== PORT definition for CAN0 peripheral ========== */
#define PIN_PA25G_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux G */
#define MUX_PA25G_CAN0_RX _L_(6)
#define PINMUX_PA25G_CAN0_RX ((PIN_PA25G_CAN0_RX << 16) | MUX_PA25G_CAN0_RX)
#define PORT_PA25G_CAN0_RX (_UL_(1) << 25)
#define PIN_PA24G_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux G */
#define MUX_PA24G_CAN0_TX _L_(6)
#define PINMUX_PA24G_CAN0_TX ((PIN_PA24G_CAN0_TX << 16) | MUX_PA24G_CAN0_TX)
#define PORT_PA24G_CAN0_TX (_UL_(1) << 24)
/* ========== PORT definition for TCC0 peripheral ========== */
#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
#define MUX_PA04E_TCC0_WO0 _L_(4)
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4)
#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
#define MUX_PA08E_TCC0_WO0 _L_(4)
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8)
#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
#define MUX_PA05E_TCC0_WO1 _L_(4)
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5)
#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
#define MUX_PA09E_TCC0_WO1 _L_(4)
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9)
#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
#define MUX_PA10F_TCC0_WO2 _L_(5)
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
#define MUX_PA18F_TCC0_WO2 _L_(5)
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18)
#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
#define MUX_PA11F_TCC0_WO3 _L_(5)
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
#define MUX_PA19F_TCC0_WO3 _L_(5)
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19)
#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
#define MUX_PA22F_TCC0_WO4 _L_(5)
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22)
#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
#define MUX_PA14F_TCC0_WO4 _L_(5)
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14)
#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
#define MUX_PA15F_TCC0_WO5 _L_(5)
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15)
#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
#define MUX_PA23F_TCC0_WO5 _L_(5)
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23)
#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
#define MUX_PA16F_TCC0_WO6 _L_(5)
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16)
#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
#define MUX_PA17F_TCC0_WO7 _L_(5)
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17)
/* ========== PORT definition for TCC1 peripheral ========== */
#define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
#define MUX_PA06E_TCC1_WO0 _L_(4)
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
#define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6)
#define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
#define MUX_PA10E_TCC1_WO0 _L_(4)
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
#define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10)
#define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
#define MUX_PA30E_TCC1_WO0 _L_(4)
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
#define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30)
#define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
#define MUX_PA07E_TCC1_WO1 _L_(4)
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
#define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7)
#define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
#define MUX_PA11E_TCC1_WO1 _L_(4)
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
#define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11)
#define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
#define MUX_PA31E_TCC1_WO1 _L_(4)
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
#define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31)
#define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
#define MUX_PA08F_TCC1_WO2 _L_(5)
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
#define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8)
#define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
#define MUX_PA24F_TCC1_WO2 _L_(5)
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
#define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24)
#define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
#define MUX_PA09F_TCC1_WO3 _L_(5)
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
#define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9)
#define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
#define MUX_PA25F_TCC1_WO3 _L_(5)
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
#define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25)
/* ========== PORT definition for TCC2 peripheral ========== */
#define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
#define MUX_PA16E_TCC2_WO0 _L_(4)
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
#define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16)
#define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
#define MUX_PA00E_TCC2_WO0 _L_(4)
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
#define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0)
#define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
#define MUX_PA17E_TCC2_WO1 _L_(4)
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
#define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17)
#define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
#define MUX_PA01E_TCC2_WO1 _L_(4)
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
#define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1)
/* ========== PORT definition for TC0 peripheral ========== */
#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */
#define MUX_PA22E_TC0_WO0 _L_(4)
#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0)
#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22)
#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */
#define MUX_PA23E_TC0_WO1 _L_(4)
#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1)
#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23)
/* ========== PORT definition for TC1 peripheral ========== */
#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */
#define MUX_PA24E_TC1_WO0 _L_(4)
#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0)
#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24)
#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */
#define MUX_PA25E_TC1_WO1 _L_(4)
#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1)
#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25)
/* ========== PORT definition for TC4 peripheral ========== */
#define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */
#define MUX_PA18E_TC4_WO0 _L_(4)
#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0)
#define PORT_PA18E_TC4_WO0 (_UL_(1) << 18)
#define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */
#define MUX_PA14E_TC4_WO0 _L_(4)
#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0)
#define PORT_PA14E_TC4_WO0 (_UL_(1) << 14)
#define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */
#define MUX_PA19E_TC4_WO1 _L_(4)
#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1)
#define PORT_PA19E_TC4_WO1 (_UL_(1) << 19)
#define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */
#define MUX_PA15E_TC4_WO1 _L_(4)
#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1)
#define PORT_PA15E_TC4_WO1 (_UL_(1) << 15)
/* ========== PORT definition for ADC0 peripheral ========== */
#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
#define MUX_PA02B_ADC0_AIN0 _L_(1)
#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
#define MUX_PA03B_ADC0_AIN1 _L_(1)
#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
#define MUX_PA04B_ADC0_AIN4 _L_(1)
#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
#define MUX_PA05B_ADC0_AIN5 _L_(1)
#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
#define MUX_PA06B_ADC0_AIN6 _L_(1)
#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
#define MUX_PA07B_ADC0_AIN7 _L_(1)
#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
#define MUX_PA08B_ADC0_AIN8 _L_(1)
#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
#define MUX_PA09B_ADC0_AIN9 _L_(1)
#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
#define MUX_PA10B_ADC0_AIN10 _L_(1)
#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
#define MUX_PA11B_ADC0_AIN11 _L_(1)
#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
#define PIN_PA03B_ADC0_VREFP _L_(3) /**< \brief ADC0 signal: VREFP on PA03 mux B */
#define MUX_PA03B_ADC0_VREFP _L_(1)
#define PINMUX_PA03B_ADC0_VREFP ((PIN_PA03B_ADC0_VREFP << 16) | MUX_PA03B_ADC0_VREFP)
#define PORT_PA03B_ADC0_VREFP (_UL_(1) << 3)
/* ========== PORT definition for ADC1 peripheral ========== */
#define PIN_PA08B_ADC1_AIN10 _L_(8) /**< \brief ADC1 signal: AIN10 on PA08 mux B */
#define MUX_PA08B_ADC1_AIN10 _L_(1)
#define PINMUX_PA08B_ADC1_AIN10 ((PIN_PA08B_ADC1_AIN10 << 16) | MUX_PA08B_ADC1_AIN10)
#define PORT_PA08B_ADC1_AIN10 (_UL_(1) << 8)
#define PIN_PA09B_ADC1_AIN11 _L_(9) /**< \brief ADC1 signal: AIN11 on PA09 mux B */
#define MUX_PA09B_ADC1_AIN11 _L_(1)
#define PINMUX_PA09B_ADC1_AIN11 ((PIN_PA09B_ADC1_AIN11 << 16) | MUX_PA09B_ADC1_AIN11)
#define PORT_PA09B_ADC1_AIN11 (_UL_(1) << 9)
/* ========== PORT definition for SDADC peripheral ========== */
#define PIN_PA06B_SDADC_INN0 _L_(6) /**< \brief SDADC signal: INN0 on PA06 mux B */
#define MUX_PA06B_SDADC_INN0 _L_(1)
#define PINMUX_PA06B_SDADC_INN0 ((PIN_PA06B_SDADC_INN0 << 16) | MUX_PA06B_SDADC_INN0)
#define PORT_PA06B_SDADC_INN0 (_UL_(1) << 6)
#define PIN_PA07B_SDADC_INP0 _L_(7) /**< \brief SDADC signal: INP0 on PA07 mux B */
#define MUX_PA07B_SDADC_INP0 _L_(1)
#define PINMUX_PA07B_SDADC_INP0 ((PIN_PA07B_SDADC_INP0 << 16) | MUX_PA07B_SDADC_INP0)
#define PORT_PA07B_SDADC_INP0 (_UL_(1) << 7)
#define PIN_PA04B_SDADC_VREFP _L_(4) /**< \brief SDADC signal: VREFP on PA04 mux B */
#define MUX_PA04B_SDADC_VREFP _L_(1)
#define PINMUX_PA04B_SDADC_VREFP ((PIN_PA04B_SDADC_VREFP << 16) | MUX_PA04B_SDADC_VREFP)
#define PORT_PA04B_SDADC_VREFP (_UL_(1) << 4)
/* ========== PORT definition for AC peripheral ========== */
#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
#define MUX_PA04B_AC_AIN0 _L_(1)
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
#define MUX_PA05B_AC_AIN1 _L_(1)
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
#define MUX_PA06B_AC_AIN2 _L_(1)
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
#define MUX_PA07B_AC_AIN3 _L_(1)
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
#define PIN_PA02B_AC_AIN4 _L_(2) /**< \brief AC signal: AIN4 on PA02 mux B */
#define MUX_PA02B_AC_AIN4 _L_(1)
#define PINMUX_PA02B_AC_AIN4 ((PIN_PA02B_AC_AIN4 << 16) | MUX_PA02B_AC_AIN4)
#define PORT_PA02B_AC_AIN4 (_UL_(1) << 2)
#define PIN_PA03B_AC_AIN5 _L_(3) /**< \brief AC signal: AIN5 on PA03 mux B */
#define MUX_PA03B_AC_AIN5 _L_(1)
#define PINMUX_PA03B_AC_AIN5 ((PIN_PA03B_AC_AIN5 << 16) | MUX_PA03B_AC_AIN5)
#define PORT_PA03B_AC_AIN5 (_UL_(1) << 3)
#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */
#define MUX_PA18H_AC_CMP0 _L_(7)
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18)
#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */
#define MUX_PA19H_AC_CMP1 _L_(7)
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19)
#define PIN_PA00H_AC_CMP2 _L_(0) /**< \brief AC signal: CMP2 on PA00 mux H */
#define MUX_PA00H_AC_CMP2 _L_(7)
#define PINMUX_PA00H_AC_CMP2 ((PIN_PA00H_AC_CMP2 << 16) | MUX_PA00H_AC_CMP2)
#define PORT_PA00H_AC_CMP2 (_UL_(1) << 0)
#define PIN_PA24H_AC_CMP2 _L_(24) /**< \brief AC signal: CMP2 on PA24 mux H */
#define MUX_PA24H_AC_CMP2 _L_(7)
#define PINMUX_PA24H_AC_CMP2 ((PIN_PA24H_AC_CMP2 << 16) | MUX_PA24H_AC_CMP2)
#define PORT_PA24H_AC_CMP2 (_UL_(1) << 24)
#define PIN_PA01H_AC_CMP3 _L_(1) /**< \brief AC signal: CMP3 on PA01 mux H */
#define MUX_PA01H_AC_CMP3 _L_(7)
#define PINMUX_PA01H_AC_CMP3 ((PIN_PA01H_AC_CMP3 << 16) | MUX_PA01H_AC_CMP3)
#define PORT_PA01H_AC_CMP3 (_UL_(1) << 1)
#define PIN_PA25H_AC_CMP3 _L_(25) /**< \brief AC signal: CMP3 on PA25 mux H */
#define MUX_PA25H_AC_CMP3 _L_(7)
#define PINMUX_PA25H_AC_CMP3 ((PIN_PA25H_AC_CMP3 << 16) | MUX_PA25H_AC_CMP3)
#define PORT_PA25H_AC_CMP3 (_UL_(1) << 25)
/* ========== PORT definition for DAC peripheral ========== */
#define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */
#define MUX_PA02B_DAC_VOUT _L_(1)
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
#define PORT_PA02B_DAC_VOUT (_UL_(1) << 2)
#define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */
#define MUX_PA03B_DAC_VREFP _L_(1)
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
#define PORT_PA03B_DAC_VREFP (_UL_(1) << 3)
/* ========== PORT definition for CCL peripheral ========== */
#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */
#define MUX_PA04I_CCL_IN0 _L_(8)
#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0)
#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4)
#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */
#define MUX_PA16I_CCL_IN0 _L_(8)
#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0)
#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16)
#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */
#define MUX_PA05I_CCL_IN1 _L_(8)
#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1)
#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5)
#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */
#define MUX_PA17I_CCL_IN1 _L_(8)
#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1)
#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17)
#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */
#define MUX_PA06I_CCL_IN2 _L_(8)
#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2)
#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6)
#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */
#define MUX_PA18I_CCL_IN2 _L_(8)
#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2)
#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18)
#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */
#define MUX_PA08I_CCL_IN3 _L_(8)
#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3)
#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8)
#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */
#define MUX_PA30I_CCL_IN3 _L_(8)
#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3)
#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30)
#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */
#define MUX_PA09I_CCL_IN4 _L_(8)
#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4)
#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9)
#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */
#define MUX_PA10I_CCL_IN5 _L_(8)
#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5)
#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10)
#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */
#define MUX_PA22I_CCL_IN6 _L_(8)
#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6)
#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22)
#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */
#define MUX_PA23I_CCL_IN7 _L_(8)
#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7)
#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23)
#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */
#define MUX_PA24I_CCL_IN8 _L_(8)
#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8)
#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24)
#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */
#define MUX_PA07I_CCL_OUT0 _L_(8)
#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0)
#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7)
#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */
#define MUX_PA19I_CCL_OUT0 _L_(8)
#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0)
#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19)
#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */
#define MUX_PA11I_CCL_OUT1 _L_(8)
#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1)
#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11)
#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */
#define MUX_PA31I_CCL_OUT1 _L_(8)
#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1)
#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31)
#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */
#define MUX_PA25I_CCL_OUT2 _L_(8)
#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2)
#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25)
#endif /* _SAMC21E17A_PIO_ */

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/**
* \file
*
* \brief Peripheral I/O description for SAMC21E18A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21E18A_PIO_
#define _SAMC21E18A_PIO_
#define PIN_PA00 0 /**< \brief Pin Number for PA00 */
#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */
#define PIN_PA01 1 /**< \brief Pin Number for PA01 */
#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */
#define PIN_PA02 2 /**< \brief Pin Number for PA02 */
#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */
#define PIN_PA03 3 /**< \brief Pin Number for PA03 */
#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */
#define PIN_PA04 4 /**< \brief Pin Number for PA04 */
#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */
#define PIN_PA05 5 /**< \brief Pin Number for PA05 */
#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */
#define PIN_PA06 6 /**< \brief Pin Number for PA06 */
#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */
#define PIN_PA07 7 /**< \brief Pin Number for PA07 */
#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */
#define PIN_PA08 8 /**< \brief Pin Number for PA08 */
#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */
#define PIN_PA09 9 /**< \brief Pin Number for PA09 */
#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */
#define PIN_PA10 10 /**< \brief Pin Number for PA10 */
#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */
#define PIN_PA11 11 /**< \brief Pin Number for PA11 */
#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */
#define PIN_PA14 14 /**< \brief Pin Number for PA14 */
#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */
#define PIN_PA15 15 /**< \brief Pin Number for PA15 */
#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */
#define PIN_PA16 16 /**< \brief Pin Number for PA16 */
#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */
#define PIN_PA17 17 /**< \brief Pin Number for PA17 */
#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */
#define PIN_PA18 18 /**< \brief Pin Number for PA18 */
#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */
#define PIN_PA19 19 /**< \brief Pin Number for PA19 */
#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */
#define PIN_PA22 22 /**< \brief Pin Number for PA22 */
#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */
#define PIN_PA23 23 /**< \brief Pin Number for PA23 */
#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */
#define PIN_PA24 24 /**< \brief Pin Number for PA24 */
#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */
#define PIN_PA25 25 /**< \brief Pin Number for PA25 */
#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */
#define PIN_PA27 27 /**< \brief Pin Number for PA27 */
#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */
#define PIN_PA28 28 /**< \brief Pin Number for PA28 */
#define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */
#define PIN_PA30 30 /**< \brief Pin Number for PA30 */
#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */
#define PIN_PA31 31 /**< \brief Pin Number for PA31 */
#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */
/* ========== PORT definition for RSTC peripheral ========== */
#define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */
#define MUX_PA00A_RSTC_EXTWAKE0 _L_(0)
#define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0)
#define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0)
#define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */
#define MUX_PA01A_RSTC_EXTWAKE1 _L_(0)
#define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1)
#define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1)
#define PIN_PA02A_RSTC_EXTWAKE2 _L_(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */
#define MUX_PA02A_RSTC_EXTWAKE2 _L_(0)
#define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2)
#define PORT_PA02A_RSTC_EXTWAKE2 (_UL_(1) << 2)
#define PIN_PA03A_RSTC_EXTWAKE3 _L_(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */
#define MUX_PA03A_RSTC_EXTWAKE3 _L_(0)
#define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3)
#define PORT_PA03A_RSTC_EXTWAKE3 (_UL_(1) << 3)
#define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */
#define MUX_PA04A_RSTC_EXTWAKE4 _L_(0)
#define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4)
#define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4)
#define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */
#define MUX_PA05A_RSTC_EXTWAKE5 _L_(0)
#define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5)
#define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5)
#define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */
#define MUX_PA06A_RSTC_EXTWAKE6 _L_(0)
#define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6)
#define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6)
#define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */
#define MUX_PA07A_RSTC_EXTWAKE7 _L_(0)
#define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7)
#define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7)
#define PIN_PA08A_RSTC_EXTWAKE8 _L_(8) /**< \brief RSTC signal: EXTWAKE8 on PA08 mux A */
#define MUX_PA08A_RSTC_EXTWAKE8 _L_(0)
#define PINMUX_PA08A_RSTC_EXTWAKE8 ((PIN_PA08A_RSTC_EXTWAKE8 << 16) | MUX_PA08A_RSTC_EXTWAKE8)
#define PORT_PA08A_RSTC_EXTWAKE8 (_UL_(1) << 8)
#define PIN_PA09A_RSTC_EXTWAKE9 _L_(9) /**< \brief RSTC signal: EXTWAKE9 on PA09 mux A */
#define MUX_PA09A_RSTC_EXTWAKE9 _L_(0)
#define PINMUX_PA09A_RSTC_EXTWAKE9 ((PIN_PA09A_RSTC_EXTWAKE9 << 16) | MUX_PA09A_RSTC_EXTWAKE9)
#define PORT_PA09A_RSTC_EXTWAKE9 (_UL_(1) << 9)
#define PIN_PA10A_RSTC_EXTWAKE10 _L_(10) /**< \brief RSTC signal: EXTWAKE10 on PA10 mux A */
#define MUX_PA10A_RSTC_EXTWAKE10 _L_(0)
#define PINMUX_PA10A_RSTC_EXTWAKE10 ((PIN_PA10A_RSTC_EXTWAKE10 << 16) | MUX_PA10A_RSTC_EXTWAKE10)
#define PORT_PA10A_RSTC_EXTWAKE10 (_UL_(1) << 10)
#define PIN_PA11A_RSTC_EXTWAKE11 _L_(11) /**< \brief RSTC signal: EXTWAKE11 on PA11 mux A */
#define MUX_PA11A_RSTC_EXTWAKE11 _L_(0)
#define PINMUX_PA11A_RSTC_EXTWAKE11 ((PIN_PA11A_RSTC_EXTWAKE11 << 16) | MUX_PA11A_RSTC_EXTWAKE11)
#define PORT_PA11A_RSTC_EXTWAKE11 (_UL_(1) << 11)
#define PIN_PA14A_RSTC_EXTWAKE14 _L_(14) /**< \brief RSTC signal: EXTWAKE14 on PA14 mux A */
#define MUX_PA14A_RSTC_EXTWAKE14 _L_(0)
#define PINMUX_PA14A_RSTC_EXTWAKE14 ((PIN_PA14A_RSTC_EXTWAKE14 << 16) | MUX_PA14A_RSTC_EXTWAKE14)
#define PORT_PA14A_RSTC_EXTWAKE14 (_UL_(1) << 14)
#define PIN_PA15A_RSTC_EXTWAKE15 _L_(15) /**< \brief RSTC signal: EXTWAKE15 on PA15 mux A */
#define MUX_PA15A_RSTC_EXTWAKE15 _L_(0)
#define PINMUX_PA15A_RSTC_EXTWAKE15 ((PIN_PA15A_RSTC_EXTWAKE15 << 16) | MUX_PA15A_RSTC_EXTWAKE15)
#define PORT_PA15A_RSTC_EXTWAKE15 (_UL_(1) << 15)
/* ========== PORT definition for GCLK peripheral ========== */
#define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */
#define MUX_PA14H_GCLK_IO0 _L_(7)
#define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0)
#define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14)
#define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */
#define MUX_PA27H_GCLK_IO0 _L_(7)
#define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0)
#define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27)
#define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */
#define MUX_PA30H_GCLK_IO0 _L_(7)
#define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0)
#define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30)
#define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */
#define MUX_PA28H_GCLK_IO0 _L_(7)
#define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0)
#define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28)
#define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */
#define MUX_PA15H_GCLK_IO1 _L_(7)
#define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1)
#define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15)
#define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */
#define MUX_PA16H_GCLK_IO2 _L_(7)
#define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2)
#define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16)
#define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */
#define MUX_PA17H_GCLK_IO3 _L_(7)
#define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3)
#define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17)
#define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */
#define MUX_PA10H_GCLK_IO4 _L_(7)
#define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4)
#define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10)
#define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */
#define MUX_PA11H_GCLK_IO5 _L_(7)
#define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5)
#define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11)
#define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */
#define MUX_PA22H_GCLK_IO6 _L_(7)
#define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6)
#define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22)
#define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */
#define MUX_PA23H_GCLK_IO7 _L_(7)
#define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7)
#define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23)
/* ========== PORT definition for EIC peripheral ========== */
#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */
#define MUX_PA16A_EIC_EXTINT0 _L_(0)
#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0)
#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16)
#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */
#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */
#define MUX_PA00A_EIC_EXTINT0 _L_(0)
#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0)
#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0)
#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */
#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */
#define MUX_PA17A_EIC_EXTINT1 _L_(0)
#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1)
#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17)
#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */
#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */
#define MUX_PA01A_EIC_EXTINT1 _L_(0)
#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1)
#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1)
#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */
#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */
#define MUX_PA02A_EIC_EXTINT2 _L_(0)
#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2)
#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2)
#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */
#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */
#define MUX_PA18A_EIC_EXTINT2 _L_(0)
#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2)
#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18)
#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */
#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */
#define MUX_PA03A_EIC_EXTINT3 _L_(0)
#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3)
#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3)
#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */
#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */
#define MUX_PA19A_EIC_EXTINT3 _L_(0)
#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3)
#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19)
#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */
#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */
#define MUX_PA04A_EIC_EXTINT4 _L_(0)
#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4)
#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4)
#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */
#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */
#define MUX_PA05A_EIC_EXTINT5 _L_(0)
#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5)
#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5)
#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */
#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */
#define MUX_PA06A_EIC_EXTINT6 _L_(0)
#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6)
#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6)
#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */
#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */
#define MUX_PA22A_EIC_EXTINT6 _L_(0)
#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6)
#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22)
#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */
#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */
#define MUX_PA07A_EIC_EXTINT7 _L_(0)
#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7)
#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7)
#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */
#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */
#define MUX_PA23A_EIC_EXTINT7 _L_(0)
#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7)
#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23)
#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */
#define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */
#define MUX_PA28A_EIC_EXTINT8 _L_(0)
#define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8)
#define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28)
#define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */
#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */
#define MUX_PA09A_EIC_EXTINT9 _L_(0)
#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9)
#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9)
#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */
#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */
#define MUX_PA10A_EIC_EXTINT10 _L_(0)
#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10)
#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10)
#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */
#define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */
#define MUX_PA30A_EIC_EXTINT10 _L_(0)
#define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10)
#define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30)
#define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */
#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */
#define MUX_PA11A_EIC_EXTINT11 _L_(0)
#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11)
#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11)
#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */
#define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */
#define MUX_PA31A_EIC_EXTINT11 _L_(0)
#define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11)
#define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31)
#define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */
#define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */
#define MUX_PA24A_EIC_EXTINT12 _L_(0)
#define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12)
#define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24)
#define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */
#define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */
#define MUX_PA25A_EIC_EXTINT13 _L_(0)
#define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13)
#define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25)
#define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */
#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */
#define MUX_PA14A_EIC_EXTINT14 _L_(0)
#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14)
#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14)
#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */
#define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */
#define MUX_PA27A_EIC_EXTINT15 _L_(0)
#define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15)
#define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27)
#define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */
#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */
#define MUX_PA15A_EIC_EXTINT15 _L_(0)
#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15)
#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15)
#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */
#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */
#define MUX_PA08A_EIC_NMI _L_(0)
#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI)
#define PORT_PA08A_EIC_NMI (_UL_(1) << 8)
/* ========== PORT definition for SERCOM0 peripheral ========== */
#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */
#define MUX_PA04D_SERCOM0_PAD0 _L_(3)
#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0)
#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4)
#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */
#define MUX_PA08C_SERCOM0_PAD0 _L_(2)
#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0)
#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8)
#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */
#define MUX_PA05D_SERCOM0_PAD1 _L_(3)
#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1)
#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5)
#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */
#define MUX_PA09C_SERCOM0_PAD1 _L_(2)
#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1)
#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9)
#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */
#define MUX_PA06D_SERCOM0_PAD2 _L_(3)
#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2)
#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6)
#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */
#define MUX_PA10C_SERCOM0_PAD2 _L_(2)
#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2)
#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10)
#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */
#define MUX_PA07D_SERCOM0_PAD3 _L_(3)
#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3)
#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7)
#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */
#define MUX_PA11C_SERCOM0_PAD3 _L_(2)
#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3)
#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11)
/* ========== PORT definition for SERCOM1 peripheral ========== */
#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */
#define MUX_PA16C_SERCOM1_PAD0 _L_(2)
#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0)
#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16)
#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */
#define MUX_PA00D_SERCOM1_PAD0 _L_(3)
#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0)
#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0)
#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */
#define MUX_PA17C_SERCOM1_PAD1 _L_(2)
#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1)
#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17)
#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */
#define MUX_PA01D_SERCOM1_PAD1 _L_(3)
#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1)
#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1)
#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */
#define MUX_PA30D_SERCOM1_PAD2 _L_(3)
#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2)
#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30)
#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */
#define MUX_PA18C_SERCOM1_PAD2 _L_(2)
#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2)
#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18)
#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */
#define MUX_PA31D_SERCOM1_PAD3 _L_(3)
#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3)
#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31)
#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */
#define MUX_PA19C_SERCOM1_PAD3 _L_(2)
#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3)
#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19)
/* ========== PORT definition for SERCOM2 peripheral ========== */
#define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */
#define MUX_PA08D_SERCOM2_PAD0 _L_(3)
#define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0)
#define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8)
#define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */
#define MUX_PA09D_SERCOM2_PAD1 _L_(3)
#define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1)
#define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9)
#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */
#define MUX_PA10D_SERCOM2_PAD2 _L_(3)
#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2)
#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10)
#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */
#define MUX_PA14C_SERCOM2_PAD2 _L_(2)
#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2)
#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14)
#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */
#define MUX_PA11D_SERCOM2_PAD3 _L_(3)
#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3)
#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11)
#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */
#define MUX_PA15C_SERCOM2_PAD3 _L_(2)
#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3)
#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15)
/* ========== PORT definition for SERCOM3 peripheral ========== */
#define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */
#define MUX_PA16D_SERCOM3_PAD0 _L_(3)
#define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0)
#define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16)
#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */
#define MUX_PA22C_SERCOM3_PAD0 _L_(2)
#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0)
#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22)
#define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */
#define MUX_PA17D_SERCOM3_PAD1 _L_(3)
#define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1)
#define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17)
#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */
#define MUX_PA23C_SERCOM3_PAD1 _L_(2)
#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1)
#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23)
#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */
#define MUX_PA18D_SERCOM3_PAD2 _L_(3)
#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2)
#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18)
#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */
#define MUX_PA24C_SERCOM3_PAD2 _L_(2)
#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2)
#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24)
#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */
#define MUX_PA19D_SERCOM3_PAD3 _L_(3)
#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3)
#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19)
#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */
#define MUX_PA25C_SERCOM3_PAD3 _L_(2)
#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3)
#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25)
/* ========== PORT definition for CAN0 peripheral ========== */
#define PIN_PA25G_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux G */
#define MUX_PA25G_CAN0_RX _L_(6)
#define PINMUX_PA25G_CAN0_RX ((PIN_PA25G_CAN0_RX << 16) | MUX_PA25G_CAN0_RX)
#define PORT_PA25G_CAN0_RX (_UL_(1) << 25)
#define PIN_PA24G_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux G */
#define MUX_PA24G_CAN0_TX _L_(6)
#define PINMUX_PA24G_CAN0_TX ((PIN_PA24G_CAN0_TX << 16) | MUX_PA24G_CAN0_TX)
#define PORT_PA24G_CAN0_TX (_UL_(1) << 24)
/* ========== PORT definition for TCC0 peripheral ========== */
#define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */
#define MUX_PA04E_TCC0_WO0 _L_(4)
#define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0)
#define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4)
#define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */
#define MUX_PA08E_TCC0_WO0 _L_(4)
#define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0)
#define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8)
#define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */
#define MUX_PA05E_TCC0_WO1 _L_(4)
#define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1)
#define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5)
#define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */
#define MUX_PA09E_TCC0_WO1 _L_(4)
#define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1)
#define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9)
#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */
#define MUX_PA10F_TCC0_WO2 _L_(5)
#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2)
#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10)
#define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */
#define MUX_PA18F_TCC0_WO2 _L_(5)
#define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2)
#define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18)
#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */
#define MUX_PA11F_TCC0_WO3 _L_(5)
#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3)
#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11)
#define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */
#define MUX_PA19F_TCC0_WO3 _L_(5)
#define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3)
#define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19)
#define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */
#define MUX_PA22F_TCC0_WO4 _L_(5)
#define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4)
#define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22)
#define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */
#define MUX_PA14F_TCC0_WO4 _L_(5)
#define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4)
#define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14)
#define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */
#define MUX_PA15F_TCC0_WO5 _L_(5)
#define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5)
#define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15)
#define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */
#define MUX_PA23F_TCC0_WO5 _L_(5)
#define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5)
#define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23)
#define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */
#define MUX_PA16F_TCC0_WO6 _L_(5)
#define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6)
#define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16)
#define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */
#define MUX_PA17F_TCC0_WO7 _L_(5)
#define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7)
#define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17)
/* ========== PORT definition for TCC1 peripheral ========== */
#define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */
#define MUX_PA06E_TCC1_WO0 _L_(4)
#define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0)
#define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6)
#define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */
#define MUX_PA10E_TCC1_WO0 _L_(4)
#define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0)
#define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10)
#define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */
#define MUX_PA30E_TCC1_WO0 _L_(4)
#define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0)
#define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30)
#define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */
#define MUX_PA07E_TCC1_WO1 _L_(4)
#define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1)
#define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7)
#define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */
#define MUX_PA11E_TCC1_WO1 _L_(4)
#define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1)
#define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11)
#define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */
#define MUX_PA31E_TCC1_WO1 _L_(4)
#define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1)
#define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31)
#define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */
#define MUX_PA08F_TCC1_WO2 _L_(5)
#define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2)
#define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8)
#define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */
#define MUX_PA24F_TCC1_WO2 _L_(5)
#define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2)
#define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24)
#define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */
#define MUX_PA09F_TCC1_WO3 _L_(5)
#define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3)
#define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9)
#define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */
#define MUX_PA25F_TCC1_WO3 _L_(5)
#define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3)
#define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25)
/* ========== PORT definition for TCC2 peripheral ========== */
#define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */
#define MUX_PA16E_TCC2_WO0 _L_(4)
#define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0)
#define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16)
#define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */
#define MUX_PA00E_TCC2_WO0 _L_(4)
#define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0)
#define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0)
#define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */
#define MUX_PA17E_TCC2_WO1 _L_(4)
#define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1)
#define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17)
#define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */
#define MUX_PA01E_TCC2_WO1 _L_(4)
#define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1)
#define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1)
/* ========== PORT definition for TC0 peripheral ========== */
#define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */
#define MUX_PA22E_TC0_WO0 _L_(4)
#define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0)
#define PORT_PA22E_TC0_WO0 (_UL_(1) << 22)
#define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */
#define MUX_PA23E_TC0_WO1 _L_(4)
#define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1)
#define PORT_PA23E_TC0_WO1 (_UL_(1) << 23)
/* ========== PORT definition for TC1 peripheral ========== */
#define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */
#define MUX_PA24E_TC1_WO0 _L_(4)
#define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0)
#define PORT_PA24E_TC1_WO0 (_UL_(1) << 24)
#define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */
#define MUX_PA25E_TC1_WO1 _L_(4)
#define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1)
#define PORT_PA25E_TC1_WO1 (_UL_(1) << 25)
/* ========== PORT definition for TC4 peripheral ========== */
#define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */
#define MUX_PA18E_TC4_WO0 _L_(4)
#define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0)
#define PORT_PA18E_TC4_WO0 (_UL_(1) << 18)
#define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */
#define MUX_PA14E_TC4_WO0 _L_(4)
#define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0)
#define PORT_PA14E_TC4_WO0 (_UL_(1) << 14)
#define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */
#define MUX_PA19E_TC4_WO1 _L_(4)
#define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1)
#define PORT_PA19E_TC4_WO1 (_UL_(1) << 19)
#define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */
#define MUX_PA15E_TC4_WO1 _L_(4)
#define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1)
#define PORT_PA15E_TC4_WO1 (_UL_(1) << 15)
/* ========== PORT definition for ADC0 peripheral ========== */
#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */
#define MUX_PA02B_ADC0_AIN0 _L_(1)
#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0)
#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2)
#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */
#define MUX_PA03B_ADC0_AIN1 _L_(1)
#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1)
#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3)
#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */
#define MUX_PA04B_ADC0_AIN4 _L_(1)
#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4)
#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4)
#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */
#define MUX_PA05B_ADC0_AIN5 _L_(1)
#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5)
#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5)
#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */
#define MUX_PA06B_ADC0_AIN6 _L_(1)
#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6)
#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6)
#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */
#define MUX_PA07B_ADC0_AIN7 _L_(1)
#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7)
#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7)
#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */
#define MUX_PA08B_ADC0_AIN8 _L_(1)
#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8)
#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8)
#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */
#define MUX_PA09B_ADC0_AIN9 _L_(1)
#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9)
#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9)
#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */
#define MUX_PA10B_ADC0_AIN10 _L_(1)
#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10)
#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10)
#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */
#define MUX_PA11B_ADC0_AIN11 _L_(1)
#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11)
#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11)
#define PIN_PA03B_ADC0_VREFP _L_(3) /**< \brief ADC0 signal: VREFP on PA03 mux B */
#define MUX_PA03B_ADC0_VREFP _L_(1)
#define PINMUX_PA03B_ADC0_VREFP ((PIN_PA03B_ADC0_VREFP << 16) | MUX_PA03B_ADC0_VREFP)
#define PORT_PA03B_ADC0_VREFP (_UL_(1) << 3)
/* ========== PORT definition for ADC1 peripheral ========== */
#define PIN_PA08B_ADC1_AIN10 _L_(8) /**< \brief ADC1 signal: AIN10 on PA08 mux B */
#define MUX_PA08B_ADC1_AIN10 _L_(1)
#define PINMUX_PA08B_ADC1_AIN10 ((PIN_PA08B_ADC1_AIN10 << 16) | MUX_PA08B_ADC1_AIN10)
#define PORT_PA08B_ADC1_AIN10 (_UL_(1) << 8)
#define PIN_PA09B_ADC1_AIN11 _L_(9) /**< \brief ADC1 signal: AIN11 on PA09 mux B */
#define MUX_PA09B_ADC1_AIN11 _L_(1)
#define PINMUX_PA09B_ADC1_AIN11 ((PIN_PA09B_ADC1_AIN11 << 16) | MUX_PA09B_ADC1_AIN11)
#define PORT_PA09B_ADC1_AIN11 (_UL_(1) << 9)
/* ========== PORT definition for SDADC peripheral ========== */
#define PIN_PA06B_SDADC_INN0 _L_(6) /**< \brief SDADC signal: INN0 on PA06 mux B */
#define MUX_PA06B_SDADC_INN0 _L_(1)
#define PINMUX_PA06B_SDADC_INN0 ((PIN_PA06B_SDADC_INN0 << 16) | MUX_PA06B_SDADC_INN0)
#define PORT_PA06B_SDADC_INN0 (_UL_(1) << 6)
#define PIN_PA07B_SDADC_INP0 _L_(7) /**< \brief SDADC signal: INP0 on PA07 mux B */
#define MUX_PA07B_SDADC_INP0 _L_(1)
#define PINMUX_PA07B_SDADC_INP0 ((PIN_PA07B_SDADC_INP0 << 16) | MUX_PA07B_SDADC_INP0)
#define PORT_PA07B_SDADC_INP0 (_UL_(1) << 7)
#define PIN_PA04B_SDADC_VREFP _L_(4) /**< \brief SDADC signal: VREFP on PA04 mux B */
#define MUX_PA04B_SDADC_VREFP _L_(1)
#define PINMUX_PA04B_SDADC_VREFP ((PIN_PA04B_SDADC_VREFP << 16) | MUX_PA04B_SDADC_VREFP)
#define PORT_PA04B_SDADC_VREFP (_UL_(1) << 4)
/* ========== PORT definition for AC peripheral ========== */
#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */
#define MUX_PA04B_AC_AIN0 _L_(1)
#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0)
#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4)
#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */
#define MUX_PA05B_AC_AIN1 _L_(1)
#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1)
#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5)
#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */
#define MUX_PA06B_AC_AIN2 _L_(1)
#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2)
#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6)
#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */
#define MUX_PA07B_AC_AIN3 _L_(1)
#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3)
#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7)
#define PIN_PA02B_AC_AIN4 _L_(2) /**< \brief AC signal: AIN4 on PA02 mux B */
#define MUX_PA02B_AC_AIN4 _L_(1)
#define PINMUX_PA02B_AC_AIN4 ((PIN_PA02B_AC_AIN4 << 16) | MUX_PA02B_AC_AIN4)
#define PORT_PA02B_AC_AIN4 (_UL_(1) << 2)
#define PIN_PA03B_AC_AIN5 _L_(3) /**< \brief AC signal: AIN5 on PA03 mux B */
#define MUX_PA03B_AC_AIN5 _L_(1)
#define PINMUX_PA03B_AC_AIN5 ((PIN_PA03B_AC_AIN5 << 16) | MUX_PA03B_AC_AIN5)
#define PORT_PA03B_AC_AIN5 (_UL_(1) << 3)
#define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */
#define MUX_PA18H_AC_CMP0 _L_(7)
#define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0)
#define PORT_PA18H_AC_CMP0 (_UL_(1) << 18)
#define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */
#define MUX_PA19H_AC_CMP1 _L_(7)
#define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1)
#define PORT_PA19H_AC_CMP1 (_UL_(1) << 19)
#define PIN_PA00H_AC_CMP2 _L_(0) /**< \brief AC signal: CMP2 on PA00 mux H */
#define MUX_PA00H_AC_CMP2 _L_(7)
#define PINMUX_PA00H_AC_CMP2 ((PIN_PA00H_AC_CMP2 << 16) | MUX_PA00H_AC_CMP2)
#define PORT_PA00H_AC_CMP2 (_UL_(1) << 0)
#define PIN_PA24H_AC_CMP2 _L_(24) /**< \brief AC signal: CMP2 on PA24 mux H */
#define MUX_PA24H_AC_CMP2 _L_(7)
#define PINMUX_PA24H_AC_CMP2 ((PIN_PA24H_AC_CMP2 << 16) | MUX_PA24H_AC_CMP2)
#define PORT_PA24H_AC_CMP2 (_UL_(1) << 24)
#define PIN_PA01H_AC_CMP3 _L_(1) /**< \brief AC signal: CMP3 on PA01 mux H */
#define MUX_PA01H_AC_CMP3 _L_(7)
#define PINMUX_PA01H_AC_CMP3 ((PIN_PA01H_AC_CMP3 << 16) | MUX_PA01H_AC_CMP3)
#define PORT_PA01H_AC_CMP3 (_UL_(1) << 1)
#define PIN_PA25H_AC_CMP3 _L_(25) /**< \brief AC signal: CMP3 on PA25 mux H */
#define MUX_PA25H_AC_CMP3 _L_(7)
#define PINMUX_PA25H_AC_CMP3 ((PIN_PA25H_AC_CMP3 << 16) | MUX_PA25H_AC_CMP3)
#define PORT_PA25H_AC_CMP3 (_UL_(1) << 25)
/* ========== PORT definition for DAC peripheral ========== */
#define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */
#define MUX_PA02B_DAC_VOUT _L_(1)
#define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT)
#define PORT_PA02B_DAC_VOUT (_UL_(1) << 2)
#define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */
#define MUX_PA03B_DAC_VREFP _L_(1)
#define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP)
#define PORT_PA03B_DAC_VREFP (_UL_(1) << 3)
/* ========== PORT definition for CCL peripheral ========== */
#define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */
#define MUX_PA04I_CCL_IN0 _L_(8)
#define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0)
#define PORT_PA04I_CCL_IN0 (_UL_(1) << 4)
#define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */
#define MUX_PA16I_CCL_IN0 _L_(8)
#define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0)
#define PORT_PA16I_CCL_IN0 (_UL_(1) << 16)
#define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */
#define MUX_PA05I_CCL_IN1 _L_(8)
#define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1)
#define PORT_PA05I_CCL_IN1 (_UL_(1) << 5)
#define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */
#define MUX_PA17I_CCL_IN1 _L_(8)
#define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1)
#define PORT_PA17I_CCL_IN1 (_UL_(1) << 17)
#define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */
#define MUX_PA06I_CCL_IN2 _L_(8)
#define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2)
#define PORT_PA06I_CCL_IN2 (_UL_(1) << 6)
#define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */
#define MUX_PA18I_CCL_IN2 _L_(8)
#define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2)
#define PORT_PA18I_CCL_IN2 (_UL_(1) << 18)
#define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */
#define MUX_PA08I_CCL_IN3 _L_(8)
#define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3)
#define PORT_PA08I_CCL_IN3 (_UL_(1) << 8)
#define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */
#define MUX_PA30I_CCL_IN3 _L_(8)
#define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3)
#define PORT_PA30I_CCL_IN3 (_UL_(1) << 30)
#define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */
#define MUX_PA09I_CCL_IN4 _L_(8)
#define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4)
#define PORT_PA09I_CCL_IN4 (_UL_(1) << 9)
#define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */
#define MUX_PA10I_CCL_IN5 _L_(8)
#define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5)
#define PORT_PA10I_CCL_IN5 (_UL_(1) << 10)
#define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */
#define MUX_PA22I_CCL_IN6 _L_(8)
#define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6)
#define PORT_PA22I_CCL_IN6 (_UL_(1) << 22)
#define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */
#define MUX_PA23I_CCL_IN7 _L_(8)
#define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7)
#define PORT_PA23I_CCL_IN7 (_UL_(1) << 23)
#define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */
#define MUX_PA24I_CCL_IN8 _L_(8)
#define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8)
#define PORT_PA24I_CCL_IN8 (_UL_(1) << 24)
#define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */
#define MUX_PA07I_CCL_OUT0 _L_(8)
#define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0)
#define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7)
#define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */
#define MUX_PA19I_CCL_OUT0 _L_(8)
#define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0)
#define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19)
#define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */
#define MUX_PA11I_CCL_OUT1 _L_(8)
#define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1)
#define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11)
#define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */
#define MUX_PA31I_CCL_OUT1 _L_(8)
#define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1)
#define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31)
#define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */
#define MUX_PA25I_CCL_OUT2 _L_(8)
#define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2)
#define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25)
#endif /* _SAMC21E18A_PIO_ */

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/**
* \file
*
* \brief Top level header file
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \license_stop
*
*/
#ifndef _SAM_
#define _SAM_
#if defined(__SAMC21E15A__) || defined(__ATSAMC21E15A__)
#include "samc21e15a.h"
#elif defined(__SAMC21E16A__) || defined(__ATSAMC21E16A__)
#include "samc21e16a.h"
#elif defined(__SAMC21E17A__) || defined(__ATSAMC21E17A__)
#include "samc21e17a.h"
#elif defined(__SAMC21E18A__) || defined(__ATSAMC21E18A__)
#include "samc21e18a.h"
#elif defined(__SAMC21G15A__) || defined(__ATSAMC21G15A__)
#include "samc21g15a.h"
#elif defined(__SAMC21G16A__) || defined(__ATSAMC21G16A__)
#include "samc21g16a.h"
#elif defined(__SAMC21G17A__) || defined(__ATSAMC21G17A__)
#include "samc21g17a.h"
#elif defined(__SAMC21G18A__) || defined(__ATSAMC21G18A__)
#include "samc21g18a.h"
#elif defined(__SAMC21J15A__) || defined(__ATSAMC21J15A__)
#include "samc21j15a.h"
#elif defined(__SAMC21J16A__) || defined(__ATSAMC21J16A__)
#include "samc21j16a.h"
#elif defined(__SAMC21J17A__) || defined(__ATSAMC21J17A__)
#include "samc21j17a.h"
#elif defined(__SAMC21J17AU__) || defined(__ATSAMC21J17AU__)
#include "samc21j17au.h"
#elif defined(__SAMC21J18A__) || defined(__ATSAMC21J18A__)
#include "samc21j18a.h"
#elif defined(__SAMC21J18AU__) || defined(__ATSAMC21J18AU__)
#include "samc21j18au.h"
#else
#error Library does not support the specified device
#endif
#endif /* _SAM_ */

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/**
* \file
*
* \brief Top header file for SAMC21
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21_
#define _SAMC21_
/**
* \defgroup SAMC21_definitions SAMC21 Device Definitions
* \brief SAMC21 CMSIS Definitions.
*/
#if defined(__SAMC21E15A__) || defined(__ATSAMC21E15A__)
#include "samc21e15a.h"
#elif defined(__SAMC21E16A__) || defined(__ATSAMC21E16A__)
#include "samc21e16a.h"
#elif defined(__SAMC21E17A__) || defined(__ATSAMC21E17A__)
#include "samc21e17a.h"
#elif defined(__SAMC21E18A__) || defined(__ATSAMC21E18A__)
#include "samc21e18a.h"
#elif defined(__SAMC21G15A__) || defined(__ATSAMC21G15A__)
#include "samc21g15a.h"
#elif defined(__SAMC21G16A__) || defined(__ATSAMC21G16A__)
#include "samc21g16a.h"
#elif defined(__SAMC21G17A__) || defined(__ATSAMC21G17A__)
#include "samc21g17a.h"
#elif defined(__SAMC21G18A__) || defined(__ATSAMC21G18A__)
#include "samc21g18a.h"
#elif defined(__SAMC21J15A__) || defined(__ATSAMC21J15A__)
#include "samc21j15a.h"
#elif defined(__SAMC21J16A__) || defined(__ATSAMC21J16A__)
#include "samc21j16a.h"
#elif defined(__SAMC21J17A__) || defined(__ATSAMC21J17A__)
#include "samc21j17a.h"
#elif defined(__SAMC21J17AU__) || defined(__ATSAMC21J17AU__)
#include "samc21j17au.h"
#elif defined(__SAMC21J18A__) || defined(__ATSAMC21J18A__)
#include "samc21j18a.h"
#elif defined(__SAMC21J18AU__) || defined(__ATSAMC21J18AU__)
#include "samc21j18au.h"
#else
#error Library does not support the specified device.
#endif
#endif /* _SAMC21_ */

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lib/samc21/samc21/include/samc21e15a.h Normal file
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/**
* \file
*
* \brief Header file for SAMC21E15A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21E15A_
#define _SAMC21E15A_
/**
* \ingroup SAMC21_definitions
* \addtogroup SAMC21E15A_definitions SAMC21E15A definitions
* This file defines all structures and symbols for SAMC21E15A:
* - registers and bitfields
* - peripheral base address
* - peripheral ID
* - PIO definitions
*/
/*@{*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#else
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
#endif
#if !defined(SKIP_INTEGER_LITERALS)
#if defined(_U_) || defined(_L_) || defined(_UL_)
#error "Integer Literals macros already defined elsewhere"
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
#define _L_(x) x ## L /**< C code: Long integer literal constant value */
#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
#define _L_(x) x /**< Assembler: Long integer literal constant value */
#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/* ************************************************************************** */
/** CMSIS DEFINITIONS FOR SAMC21E15A */
/* ************************************************************************** */
/** \defgroup SAMC21E15A_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
/****** SAMC21E15A-specific Interrupt Numbers *********************/
SYSTEM_IRQn = 0, /**< 0 SAMC21E15A System Interrupts */
WDT_IRQn = 1, /**< 1 SAMC21E15A Watchdog Timer (WDT) */
RTC_IRQn = 2, /**< 2 SAMC21E15A Real-Time Counter (RTC) */
EIC_IRQn = 3, /**< 3 SAMC21E15A External Interrupt Controller (EIC) */
FREQM_IRQn = 4, /**< 4 SAMC21E15A Frequency Meter (FREQM) */
TSENS_IRQn = 5, /**< 5 SAMC21E15A Temperature Sensor (TSENS) */
NVMCTRL_IRQn = 6, /**< 6 SAMC21E15A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 7, /**< 7 SAMC21E15A Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMC21E15A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMC21E15A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMC21E15A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMC21E15A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMC21E15A Serial Communication Interface 3 (SERCOM3) */
CAN0_IRQn = 15, /**< 15 SAMC21E15A Control Area Network 0 (CAN0) */
TCC0_IRQn = 17, /**< 17 SAMC21E15A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 18, /**< 18 SAMC21E15A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 19, /**< 19 SAMC21E15A Timer Counter Control 2 (TCC2) */
TC0_IRQn = 20, /**< 20 SAMC21E15A Basic Timer Counter 0 (TC0) */
TC1_IRQn = 21, /**< 21 SAMC21E15A Basic Timer Counter 1 (TC1) */
TC2_IRQn = 22, /**< 22 SAMC21E15A Basic Timer Counter 2 (TC2) */
TC3_IRQn = 23, /**< 23 SAMC21E15A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 24, /**< 24 SAMC21E15A Basic Timer Counter 4 (TC4) */
ADC0_IRQn = 25, /**< 25 SAMC21E15A Analog Digital Converter 0 (ADC0) */
ADC1_IRQn = 26, /**< 26 SAMC21E15A Analog Digital Converter 1 (ADC1) */
AC_IRQn = 27, /**< 27 SAMC21E15A Analog Comparators (AC) */
DAC_IRQn = 28, /**< 28 SAMC21E15A Digital Analog Converter (DAC) */
SDADC_IRQn = 29, /**< 29 SAMC21E15A Sigma-Delta Analog Digital Converter (SDADC) */
PTC_IRQn = 30, /**< 30 SAMC21E15A Peripheral Touch Controller (PTC) */
PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNonMaskableInt_Handler;
void* pfnHardFault_Handler;
void* pvReservedM12;
void* pvReservedM11;
void* pvReservedM10;
void* pvReservedM9;
void* pvReservedM8;
void* pvReservedM7;
void* pvReservedM6;
void* pfnSVCall_Handler;
void* pvReservedM4;
void* pvReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
void* pfnWDT_Handler; /* 1 Watchdog Timer */
void* pfnRTC_Handler; /* 2 Real-Time Counter */
void* pfnEIC_Handler; /* 3 External Interrupt Controller */
void* pfnFREQM_Handler; /* 4 Frequency Meter */
void* pfnTSENS_Handler; /* 5 Temperature Sensor */
void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pvReserved13;
void* pvReserved14;
void* pfnCAN0_Handler; /* 15 Control Area Network 0 */
void* pvReserved16;
void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */
void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */
void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */
void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */
void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */
void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */
void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */
void* pfnAC_Handler; /* 27 Analog Comparators */
void* pfnDAC_Handler; /* 28 Digital Analog Converter */
void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */
void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void SVCall_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void SYSTEM_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void FREQM_Handler ( void );
void TSENS_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void CAN0_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void ADC0_Handler ( void );
void ADC1_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void SDADC_Handler ( void );
void PTC_Handler ( void );
/*
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* \brief CMSIS includes
*/
#include <core_cm0plus.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samc21.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21E15A */
/* ************************************************************************** */
/** \defgroup SAMC21E15A_api Peripheral Software API */
/*@{*/
#include "component/ac.h"
#include "component/adc.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/dac.h"
#include "component/divas.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/mclk.h"
#include "component/mtb.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdadc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/tsens.h"
#include "component/wdt.h"
/*@}*/
/* ************************************************************************** */
/** REGISTERS ACCESS DEFINITIONS FOR SAMC21E15A */
/* ************************************************************************** */
/** \defgroup SAMC21E15A_reg Registers Access Definitions */
/*@{*/
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/can0.h"
#include "instance/ccl.h"
#include "instance/dac.h"
#include "instance/divas.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/hmatrixhs.h"
#include "instance/mclk.h"
#include "instance/mtb.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/ptc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdadc.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tsens.h"
#include "instance/wdt.h"
/*@}*/
/* ************************************************************************** */
/** PERIPHERAL ID DEFINITIONS FOR SAMC21E15A */
/* ************************************************************************** */
/** \defgroup SAMC21E15A_id Peripheral Ids Definitions */
/*@{*/
// Peripheral instances on HPB0 bridge
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM 1 /**< \brief Power Manager (PM) */
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */
// Peripheral instances on HPB1 bridge
#define ID_PORT 32 /**< \brief Port Module (PORT) */
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */
// Peripheral instances on HPB2 bridge
#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */
#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */
#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */
#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */
#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */
#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */
#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */
#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */
#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */
#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */
#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */
#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */
#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */
#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */
#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */
#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */
#define ID_AC 84 /**< \brief Analog Comparators (AC) */
#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */
#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */
#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */
// Peripheral instances on AHB (as if on bridge 3)
#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */
#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */
/*@}*/
/* ************************************************************************** */
/** BASE ADDRESS DEFINITIONS FOR SAMC21E15A */
/* ************************************************************************** */
/** \defgroup SAMC21E15A_base Peripheral Base Address Definitions */
/*@{*/
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42005000) /**< \brief (AC) APB Base Address */
#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */
#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */
#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */
#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */
#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */
#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */
#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */
#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */
#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */
#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */
#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */
#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */
#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */
#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */
#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */
#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
#else
#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */
#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */
#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */
#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */
#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */
#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */
#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */
#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */
#define PTC_GCLK_ID 37
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */
#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */
#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */
#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */
#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */
#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */
#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */
#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */
#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
/* ************************************************************************** */
/** PORT DEFINITIONS FOR SAMC21E15A */
/* ************************************************************************** */
/** \defgroup SAMC21E15A_port PORT Definitions */
/*@{*/
#include "pio/samc21e15a.h"
/*@}*/
/* ************************************************************************** */
/** MEMORY MAPPING DEFINITIONS FOR SAMC21E15A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */
#define FLASH_PAGE_SIZE 64
#define FLASH_NB_OF_PAGES 512
#define FLASH_USER_PAGE_SIZE 64
#define HSRAM_SIZE _UL_(0x00001000) /* 4 kB */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
#define DSU_DID_RESETVALUE _UL_(0x1101050D)
#define AC_PAIRS 2
#define DMAC_CH_NUM 12
#define EVSYS_CHANNELS 12
#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000400) /* 1 kB */
#define PORT_GROUPS 1
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMC21E15A */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* SAMC21E15A_H */

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/**
* \file
*
* \brief Header file for SAMC21E16A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21E16A_
#define _SAMC21E16A_
/**
* \ingroup SAMC21_definitions
* \addtogroup SAMC21E16A_definitions SAMC21E16A definitions
* This file defines all structures and symbols for SAMC21E16A:
* - registers and bitfields
* - peripheral base address
* - peripheral ID
* - PIO definitions
*/
/*@{*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#else
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
#endif
#if !defined(SKIP_INTEGER_LITERALS)
#if defined(_U_) || defined(_L_) || defined(_UL_)
#error "Integer Literals macros already defined elsewhere"
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
#define _L_(x) x ## L /**< C code: Long integer literal constant value */
#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
#define _L_(x) x /**< Assembler: Long integer literal constant value */
#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/* ************************************************************************** */
/** CMSIS DEFINITIONS FOR SAMC21E16A */
/* ************************************************************************** */
/** \defgroup SAMC21E16A_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
/****** SAMC21E16A-specific Interrupt Numbers *********************/
SYSTEM_IRQn = 0, /**< 0 SAMC21E16A System Interrupts */
WDT_IRQn = 1, /**< 1 SAMC21E16A Watchdog Timer (WDT) */
RTC_IRQn = 2, /**< 2 SAMC21E16A Real-Time Counter (RTC) */
EIC_IRQn = 3, /**< 3 SAMC21E16A External Interrupt Controller (EIC) */
FREQM_IRQn = 4, /**< 4 SAMC21E16A Frequency Meter (FREQM) */
TSENS_IRQn = 5, /**< 5 SAMC21E16A Temperature Sensor (TSENS) */
NVMCTRL_IRQn = 6, /**< 6 SAMC21E16A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 7, /**< 7 SAMC21E16A Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMC21E16A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMC21E16A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMC21E16A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMC21E16A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMC21E16A Serial Communication Interface 3 (SERCOM3) */
CAN0_IRQn = 15, /**< 15 SAMC21E16A Control Area Network 0 (CAN0) */
TCC0_IRQn = 17, /**< 17 SAMC21E16A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 18, /**< 18 SAMC21E16A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 19, /**< 19 SAMC21E16A Timer Counter Control 2 (TCC2) */
TC0_IRQn = 20, /**< 20 SAMC21E16A Basic Timer Counter 0 (TC0) */
TC1_IRQn = 21, /**< 21 SAMC21E16A Basic Timer Counter 1 (TC1) */
TC2_IRQn = 22, /**< 22 SAMC21E16A Basic Timer Counter 2 (TC2) */
TC3_IRQn = 23, /**< 23 SAMC21E16A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 24, /**< 24 SAMC21E16A Basic Timer Counter 4 (TC4) */
ADC0_IRQn = 25, /**< 25 SAMC21E16A Analog Digital Converter 0 (ADC0) */
ADC1_IRQn = 26, /**< 26 SAMC21E16A Analog Digital Converter 1 (ADC1) */
AC_IRQn = 27, /**< 27 SAMC21E16A Analog Comparators (AC) */
DAC_IRQn = 28, /**< 28 SAMC21E16A Digital Analog Converter (DAC) */
SDADC_IRQn = 29, /**< 29 SAMC21E16A Sigma-Delta Analog Digital Converter (SDADC) */
PTC_IRQn = 30, /**< 30 SAMC21E16A Peripheral Touch Controller (PTC) */
PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNonMaskableInt_Handler;
void* pfnHardFault_Handler;
void* pvReservedM12;
void* pvReservedM11;
void* pvReservedM10;
void* pvReservedM9;
void* pvReservedM8;
void* pvReservedM7;
void* pvReservedM6;
void* pfnSVCall_Handler;
void* pvReservedM4;
void* pvReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
void* pfnWDT_Handler; /* 1 Watchdog Timer */
void* pfnRTC_Handler; /* 2 Real-Time Counter */
void* pfnEIC_Handler; /* 3 External Interrupt Controller */
void* pfnFREQM_Handler; /* 4 Frequency Meter */
void* pfnTSENS_Handler; /* 5 Temperature Sensor */
void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pvReserved13;
void* pvReserved14;
void* pfnCAN0_Handler; /* 15 Control Area Network 0 */
void* pvReserved16;
void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */
void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */
void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */
void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */
void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */
void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */
void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */
void* pfnAC_Handler; /* 27 Analog Comparators */
void* pfnDAC_Handler; /* 28 Digital Analog Converter */
void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */
void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void SVCall_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void SYSTEM_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void FREQM_Handler ( void );
void TSENS_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void CAN0_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void ADC0_Handler ( void );
void ADC1_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void SDADC_Handler ( void );
void PTC_Handler ( void );
/*
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* \brief CMSIS includes
*/
#include <core_cm0plus.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samc21.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21E16A */
/* ************************************************************************** */
/** \defgroup SAMC21E16A_api Peripheral Software API */
/*@{*/
#include "component/ac.h"
#include "component/adc.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/dac.h"
#include "component/divas.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/mclk.h"
#include "component/mtb.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdadc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/tsens.h"
#include "component/wdt.h"
/*@}*/
/* ************************************************************************** */
/** REGISTERS ACCESS DEFINITIONS FOR SAMC21E16A */
/* ************************************************************************** */
/** \defgroup SAMC21E16A_reg Registers Access Definitions */
/*@{*/
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/can0.h"
#include "instance/ccl.h"
#include "instance/dac.h"
#include "instance/divas.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/hmatrixhs.h"
#include "instance/mclk.h"
#include "instance/mtb.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/ptc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdadc.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tsens.h"
#include "instance/wdt.h"
/*@}*/
/* ************************************************************************** */
/** PERIPHERAL ID DEFINITIONS FOR SAMC21E16A */
/* ************************************************************************** */
/** \defgroup SAMC21E16A_id Peripheral Ids Definitions */
/*@{*/
// Peripheral instances on HPB0 bridge
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM 1 /**< \brief Power Manager (PM) */
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */
// Peripheral instances on HPB1 bridge
#define ID_PORT 32 /**< \brief Port Module (PORT) */
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */
// Peripheral instances on HPB2 bridge
#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */
#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */
#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */
#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */
#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */
#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */
#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */
#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */
#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */
#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */
#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */
#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */
#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */
#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */
#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */
#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */
#define ID_AC 84 /**< \brief Analog Comparators (AC) */
#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */
#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */
#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */
// Peripheral instances on AHB (as if on bridge 3)
#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */
#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */
/*@}*/
/* ************************************************************************** */
/** BASE ADDRESS DEFINITIONS FOR SAMC21E16A */
/* ************************************************************************** */
/** \defgroup SAMC21E16A_base Peripheral Base Address Definitions */
/*@{*/
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42005000) /**< \brief (AC) APB Base Address */
#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */
#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */
#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */
#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */
#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */
#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */
#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */
#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */
#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */
#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */
#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */
#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */
#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */
#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */
#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */
#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
#else
#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */
#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */
#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */
#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */
#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */
#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */
#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */
#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */
#define PTC_GCLK_ID 37
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */
#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */
#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */
#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */
#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */
#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */
#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */
#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */
#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
/* ************************************************************************** */
/** PORT DEFINITIONS FOR SAMC21E16A */
/* ************************************************************************** */
/** \defgroup SAMC21E16A_port PORT Definitions */
/*@{*/
#include "pio/samc21e16a.h"
/*@}*/
/* ************************************************************************** */
/** MEMORY MAPPING DEFINITIONS FOR SAMC21E16A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */
#define FLASH_PAGE_SIZE 64
#define FLASH_NB_OF_PAGES 1024
#define FLASH_USER_PAGE_SIZE 64
#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
#define DSU_DID_RESETVALUE _UL_(0x1101050C)
#define AC_PAIRS 2
#define DMAC_CH_NUM 12
#define EVSYS_CHANNELS 12
#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */
#define PORT_GROUPS 1
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMC21E16A */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* SAMC21E16A_H */

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/**
* \file
*
* \brief Header file for SAMC21E17A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21E17A_
#define _SAMC21E17A_
/**
* \ingroup SAMC21_definitions
* \addtogroup SAMC21E17A_definitions SAMC21E17A definitions
* This file defines all structures and symbols for SAMC21E17A:
* - registers and bitfields
* - peripheral base address
* - peripheral ID
* - PIO definitions
*/
/*@{*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#else
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
#endif
#if !defined(SKIP_INTEGER_LITERALS)
#if defined(_U_) || defined(_L_) || defined(_UL_)
#error "Integer Literals macros already defined elsewhere"
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
#define _L_(x) x ## L /**< C code: Long integer literal constant value */
#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
#define _L_(x) x /**< Assembler: Long integer literal constant value */
#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/* ************************************************************************** */
/** CMSIS DEFINITIONS FOR SAMC21E17A */
/* ************************************************************************** */
/** \defgroup SAMC21E17A_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
/****** SAMC21E17A-specific Interrupt Numbers *********************/
SYSTEM_IRQn = 0, /**< 0 SAMC21E17A System Interrupts */
WDT_IRQn = 1, /**< 1 SAMC21E17A Watchdog Timer (WDT) */
RTC_IRQn = 2, /**< 2 SAMC21E17A Real-Time Counter (RTC) */
EIC_IRQn = 3, /**< 3 SAMC21E17A External Interrupt Controller (EIC) */
FREQM_IRQn = 4, /**< 4 SAMC21E17A Frequency Meter (FREQM) */
TSENS_IRQn = 5, /**< 5 SAMC21E17A Temperature Sensor (TSENS) */
NVMCTRL_IRQn = 6, /**< 6 SAMC21E17A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 7, /**< 7 SAMC21E17A Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMC21E17A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMC21E17A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMC21E17A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMC21E17A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMC21E17A Serial Communication Interface 3 (SERCOM3) */
CAN0_IRQn = 15, /**< 15 SAMC21E17A Control Area Network 0 (CAN0) */
TCC0_IRQn = 17, /**< 17 SAMC21E17A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 18, /**< 18 SAMC21E17A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 19, /**< 19 SAMC21E17A Timer Counter Control 2 (TCC2) */
TC0_IRQn = 20, /**< 20 SAMC21E17A Basic Timer Counter 0 (TC0) */
TC1_IRQn = 21, /**< 21 SAMC21E17A Basic Timer Counter 1 (TC1) */
TC2_IRQn = 22, /**< 22 SAMC21E17A Basic Timer Counter 2 (TC2) */
TC3_IRQn = 23, /**< 23 SAMC21E17A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 24, /**< 24 SAMC21E17A Basic Timer Counter 4 (TC4) */
ADC0_IRQn = 25, /**< 25 SAMC21E17A Analog Digital Converter 0 (ADC0) */
ADC1_IRQn = 26, /**< 26 SAMC21E17A Analog Digital Converter 1 (ADC1) */
AC_IRQn = 27, /**< 27 SAMC21E17A Analog Comparators (AC) */
DAC_IRQn = 28, /**< 28 SAMC21E17A Digital Analog Converter (DAC) */
SDADC_IRQn = 29, /**< 29 SAMC21E17A Sigma-Delta Analog Digital Converter (SDADC) */
PTC_IRQn = 30, /**< 30 SAMC21E17A Peripheral Touch Controller (PTC) */
PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNonMaskableInt_Handler;
void* pfnHardFault_Handler;
void* pvReservedM12;
void* pvReservedM11;
void* pvReservedM10;
void* pvReservedM9;
void* pvReservedM8;
void* pvReservedM7;
void* pvReservedM6;
void* pfnSVCall_Handler;
void* pvReservedM4;
void* pvReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
void* pfnWDT_Handler; /* 1 Watchdog Timer */
void* pfnRTC_Handler; /* 2 Real-Time Counter */
void* pfnEIC_Handler; /* 3 External Interrupt Controller */
void* pfnFREQM_Handler; /* 4 Frequency Meter */
void* pfnTSENS_Handler; /* 5 Temperature Sensor */
void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pvReserved13;
void* pvReserved14;
void* pfnCAN0_Handler; /* 15 Control Area Network 0 */
void* pvReserved16;
void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */
void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */
void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */
void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */
void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */
void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */
void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */
void* pfnAC_Handler; /* 27 Analog Comparators */
void* pfnDAC_Handler; /* 28 Digital Analog Converter */
void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */
void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void SVCall_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void SYSTEM_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void FREQM_Handler ( void );
void TSENS_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void CAN0_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void ADC0_Handler ( void );
void ADC1_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void SDADC_Handler ( void );
void PTC_Handler ( void );
/*
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* \brief CMSIS includes
*/
#include <core_cm0plus.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samc21.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21E17A */
/* ************************************************************************** */
/** \defgroup SAMC21E17A_api Peripheral Software API */
/*@{*/
#include "component/ac.h"
#include "component/adc.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/dac.h"
#include "component/divas.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/mclk.h"
#include "component/mtb.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdadc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/tsens.h"
#include "component/wdt.h"
/*@}*/
/* ************************************************************************** */
/** REGISTERS ACCESS DEFINITIONS FOR SAMC21E17A */
/* ************************************************************************** */
/** \defgroup SAMC21E17A_reg Registers Access Definitions */
/*@{*/
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/can0.h"
#include "instance/ccl.h"
#include "instance/dac.h"
#include "instance/divas.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/hmatrixhs.h"
#include "instance/mclk.h"
#include "instance/mtb.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/ptc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdadc.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tsens.h"
#include "instance/wdt.h"
/*@}*/
/* ************************************************************************** */
/** PERIPHERAL ID DEFINITIONS FOR SAMC21E17A */
/* ************************************************************************** */
/** \defgroup SAMC21E17A_id Peripheral Ids Definitions */
/*@{*/
// Peripheral instances on HPB0 bridge
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM 1 /**< \brief Power Manager (PM) */
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */
// Peripheral instances on HPB1 bridge
#define ID_PORT 32 /**< \brief Port Module (PORT) */
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */
// Peripheral instances on HPB2 bridge
#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */
#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */
#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */
#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */
#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */
#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */
#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */
#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */
#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */
#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */
#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */
#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */
#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */
#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */
#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */
#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */
#define ID_AC 84 /**< \brief Analog Comparators (AC) */
#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */
#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */
#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */
// Peripheral instances on AHB (as if on bridge 3)
#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */
#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */
/*@}*/
/* ************************************************************************** */
/** BASE ADDRESS DEFINITIONS FOR SAMC21E17A */
/* ************************************************************************** */
/** \defgroup SAMC21E17A_base Peripheral Base Address Definitions */
/*@{*/
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42005000) /**< \brief (AC) APB Base Address */
#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */
#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */
#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */
#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */
#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */
#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */
#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */
#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */
#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */
#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */
#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */
#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */
#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */
#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */
#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */
#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
#else
#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */
#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */
#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */
#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */
#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */
#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */
#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */
#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */
#define PTC_GCLK_ID 37
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */
#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */
#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */
#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */
#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */
#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */
#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */
#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */
#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
/* ************************************************************************** */
/** PORT DEFINITIONS FOR SAMC21E17A */
/* ************************************************************************** */
/** \defgroup SAMC21E17A_port PORT Definitions */
/*@{*/
#include "pio/samc21e17a.h"
/*@}*/
/* ************************************************************************** */
/** MEMORY MAPPING DEFINITIONS FOR SAMC21E17A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */
#define FLASH_PAGE_SIZE 64
#define FLASH_NB_OF_PAGES 2048
#define FLASH_USER_PAGE_SIZE 64
#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
#define DSU_DID_RESETVALUE _UL_(0x1101050B)
#define AC_PAIRS 2
#define DMAC_CH_NUM 12
#define EVSYS_CHANNELS 12
#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
#define PORT_GROUPS 1
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMC21E17A */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* SAMC21E17A_H */

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lib/samc21/samc21/include/samc21e18a.h Normal file
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/**
* \file
*
* \brief Header file for SAMC21E18A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21E18A_
#define _SAMC21E18A_
/**
* \ingroup SAMC21_definitions
* \addtogroup SAMC21E18A_definitions SAMC21E18A definitions
* This file defines all structures and symbols for SAMC21E18A:
* - registers and bitfields
* - peripheral base address
* - peripheral ID
* - PIO definitions
*/
/*@{*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#else
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
#endif
#if !defined(SKIP_INTEGER_LITERALS)
#if defined(_U_) || defined(_L_) || defined(_UL_)
#error "Integer Literals macros already defined elsewhere"
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
#define _L_(x) x ## L /**< C code: Long integer literal constant value */
#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
#define _L_(x) x /**< Assembler: Long integer literal constant value */
#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/* ************************************************************************** */
/** CMSIS DEFINITIONS FOR SAMC21E18A */
/* ************************************************************************** */
/** \defgroup SAMC21E18A_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
/****** SAMC21E18A-specific Interrupt Numbers *********************/
SYSTEM_IRQn = 0, /**< 0 SAMC21E18A System Interrupts */
WDT_IRQn = 1, /**< 1 SAMC21E18A Watchdog Timer (WDT) */
RTC_IRQn = 2, /**< 2 SAMC21E18A Real-Time Counter (RTC) */
EIC_IRQn = 3, /**< 3 SAMC21E18A External Interrupt Controller (EIC) */
FREQM_IRQn = 4, /**< 4 SAMC21E18A Frequency Meter (FREQM) */
TSENS_IRQn = 5, /**< 5 SAMC21E18A Temperature Sensor (TSENS) */
NVMCTRL_IRQn = 6, /**< 6 SAMC21E18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 7, /**< 7 SAMC21E18A Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMC21E18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMC21E18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMC21E18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMC21E18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMC21E18A Serial Communication Interface 3 (SERCOM3) */
CAN0_IRQn = 15, /**< 15 SAMC21E18A Control Area Network 0 (CAN0) */
TCC0_IRQn = 17, /**< 17 SAMC21E18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 18, /**< 18 SAMC21E18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 19, /**< 19 SAMC21E18A Timer Counter Control 2 (TCC2) */
TC0_IRQn = 20, /**< 20 SAMC21E18A Basic Timer Counter 0 (TC0) */
TC1_IRQn = 21, /**< 21 SAMC21E18A Basic Timer Counter 1 (TC1) */
TC2_IRQn = 22, /**< 22 SAMC21E18A Basic Timer Counter 2 (TC2) */
TC3_IRQn = 23, /**< 23 SAMC21E18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 24, /**< 24 SAMC21E18A Basic Timer Counter 4 (TC4) */
ADC0_IRQn = 25, /**< 25 SAMC21E18A Analog Digital Converter 0 (ADC0) */
ADC1_IRQn = 26, /**< 26 SAMC21E18A Analog Digital Converter 1 (ADC1) */
AC_IRQn = 27, /**< 27 SAMC21E18A Analog Comparators (AC) */
DAC_IRQn = 28, /**< 28 SAMC21E18A Digital Analog Converter (DAC) */
SDADC_IRQn = 29, /**< 29 SAMC21E18A Sigma-Delta Analog Digital Converter (SDADC) */
PTC_IRQn = 30, /**< 30 SAMC21E18A Peripheral Touch Controller (PTC) */
PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNonMaskableInt_Handler;
void* pfnHardFault_Handler;
void* pvReservedM12;
void* pvReservedM11;
void* pvReservedM10;
void* pvReservedM9;
void* pvReservedM8;
void* pvReservedM7;
void* pvReservedM6;
void* pfnSVCall_Handler;
void* pvReservedM4;
void* pvReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
void* pfnWDT_Handler; /* 1 Watchdog Timer */
void* pfnRTC_Handler; /* 2 Real-Time Counter */
void* pfnEIC_Handler; /* 3 External Interrupt Controller */
void* pfnFREQM_Handler; /* 4 Frequency Meter */
void* pfnTSENS_Handler; /* 5 Temperature Sensor */
void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pvReserved13;
void* pvReserved14;
void* pfnCAN0_Handler; /* 15 Control Area Network 0 */
void* pvReserved16;
void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */
void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */
void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */
void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */
void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */
void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */
void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */
void* pfnAC_Handler; /* 27 Analog Comparators */
void* pfnDAC_Handler; /* 28 Digital Analog Converter */
void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */
void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void SVCall_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void SYSTEM_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void FREQM_Handler ( void );
void TSENS_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void CAN0_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void ADC0_Handler ( void );
void ADC1_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void SDADC_Handler ( void );
void PTC_Handler ( void );
/*
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* \brief CMSIS includes
*/
#include <core_cm0plus.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samc21.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21E18A */
/* ************************************************************************** */
/** \defgroup SAMC21E18A_api Peripheral Software API */
/*@{*/
#include "component/ac.h"
#include "component/adc.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/dac.h"
#include "component/divas.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/mclk.h"
#include "component/mtb.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdadc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/tsens.h"
#include "component/wdt.h"
/*@}*/
/* ************************************************************************** */
/** REGISTERS ACCESS DEFINITIONS FOR SAMC21E18A */
/* ************************************************************************** */
/** \defgroup SAMC21E18A_reg Registers Access Definitions */
/*@{*/
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/can0.h"
#include "instance/ccl.h"
#include "instance/dac.h"
#include "instance/divas.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/hmatrixhs.h"
#include "instance/mclk.h"
#include "instance/mtb.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/ptc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdadc.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tsens.h"
#include "instance/wdt.h"
/*@}*/
/* ************************************************************************** */
/** PERIPHERAL ID DEFINITIONS FOR SAMC21E18A */
/* ************************************************************************** */
/** \defgroup SAMC21E18A_id Peripheral Ids Definitions */
/*@{*/
// Peripheral instances on HPB0 bridge
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM 1 /**< \brief Power Manager (PM) */
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */
// Peripheral instances on HPB1 bridge
#define ID_PORT 32 /**< \brief Port Module (PORT) */
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */
// Peripheral instances on HPB2 bridge
#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */
#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */
#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */
#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */
#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */
#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */
#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */
#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */
#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */
#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */
#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */
#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */
#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */
#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */
#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */
#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */
#define ID_AC 84 /**< \brief Analog Comparators (AC) */
#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */
#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */
#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */
// Peripheral instances on AHB (as if on bridge 3)
#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */
#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */
/*@}*/
/* ************************************************************************** */
/** BASE ADDRESS DEFINITIONS FOR SAMC21E18A */
/* ************************************************************************** */
/** \defgroup SAMC21E18A_base Peripheral Base Address Definitions */
/*@{*/
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42005000) /**< \brief (AC) APB Base Address */
#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */
#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */
#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */
#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */
#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */
#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */
#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */
#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */
#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */
#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */
#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */
#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */
#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */
#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */
#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */
#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
#else
#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */
#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */
#define CAN_INST_NUM 1 /**< \brief (CAN) Number of instances */
#define CAN_INSTS { CAN0 } /**< \brief (CAN) Instances List */
#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */
#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */
#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */
#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */
#define PTC_GCLK_ID 37
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */
#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */
#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */
#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */
#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */
#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */
#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */
#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */
#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
/* ************************************************************************** */
/** PORT DEFINITIONS FOR SAMC21E18A */
/* ************************************************************************** */
/** \defgroup SAMC21E18A_port PORT Definitions */
/*@{*/
#include "pio/samc21e18a.h"
/*@}*/
/* ************************************************************************** */
/** MEMORY MAPPING DEFINITIONS FOR SAMC21E18A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */
#define FLASH_PAGE_SIZE 64
#define FLASH_NB_OF_PAGES 4096
#define FLASH_USER_PAGE_SIZE 64
#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
#define DSU_DID_RESETVALUE _UL_(0x1101050A)
#define AC_PAIRS 2
#define DMAC_CH_NUM 12
#define EVSYS_CHANNELS 12
#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */
#define PORT_GROUPS 1
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMC21E18A */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* SAMC21E18A_H */

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/**
* \file
*
* \brief Header file for SAMC21G15A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21G15A_
#define _SAMC21G15A_
/**
* \ingroup SAMC21_definitions
* \addtogroup SAMC21G15A_definitions SAMC21G15A definitions
* This file defines all structures and symbols for SAMC21G15A:
* - registers and bitfields
* - peripheral base address
* - peripheral ID
* - PIO definitions
*/
/*@{*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#else
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
#endif
#if !defined(SKIP_INTEGER_LITERALS)
#if defined(_U_) || defined(_L_) || defined(_UL_)
#error "Integer Literals macros already defined elsewhere"
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
#define _L_(x) x ## L /**< C code: Long integer literal constant value */
#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
#define _L_(x) x /**< Assembler: Long integer literal constant value */
#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/* ************************************************************************** */
/** CMSIS DEFINITIONS FOR SAMC21G15A */
/* ************************************************************************** */
/** \defgroup SAMC21G15A_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
/****** SAMC21G15A-specific Interrupt Numbers *********************/
SYSTEM_IRQn = 0, /**< 0 SAMC21G15A System Interrupts */
WDT_IRQn = 1, /**< 1 SAMC21G15A Watchdog Timer (WDT) */
RTC_IRQn = 2, /**< 2 SAMC21G15A Real-Time Counter (RTC) */
EIC_IRQn = 3, /**< 3 SAMC21G15A External Interrupt Controller (EIC) */
FREQM_IRQn = 4, /**< 4 SAMC21G15A Frequency Meter (FREQM) */
TSENS_IRQn = 5, /**< 5 SAMC21G15A Temperature Sensor (TSENS) */
NVMCTRL_IRQn = 6, /**< 6 SAMC21G15A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 7, /**< 7 SAMC21G15A Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMC21G15A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMC21G15A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMC21G15A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMC21G15A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMC21G15A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMC21G15A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMC21G15A Serial Communication Interface 5 (SERCOM5) */
CAN0_IRQn = 15, /**< 15 SAMC21G15A Control Area Network 0 (CAN0) */
CAN1_IRQn = 16, /**< 16 SAMC21G15A Control Area Network 1 (CAN1) */
TCC0_IRQn = 17, /**< 17 SAMC21G15A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 18, /**< 18 SAMC21G15A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 19, /**< 19 SAMC21G15A Timer Counter Control 2 (TCC2) */
TC0_IRQn = 20, /**< 20 SAMC21G15A Basic Timer Counter 0 (TC0) */
TC1_IRQn = 21, /**< 21 SAMC21G15A Basic Timer Counter 1 (TC1) */
TC2_IRQn = 22, /**< 22 SAMC21G15A Basic Timer Counter 2 (TC2) */
TC3_IRQn = 23, /**< 23 SAMC21G15A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 24, /**< 24 SAMC21G15A Basic Timer Counter 4 (TC4) */
ADC0_IRQn = 25, /**< 25 SAMC21G15A Analog Digital Converter 0 (ADC0) */
ADC1_IRQn = 26, /**< 26 SAMC21G15A Analog Digital Converter 1 (ADC1) */
AC_IRQn = 27, /**< 27 SAMC21G15A Analog Comparators (AC) */
DAC_IRQn = 28, /**< 28 SAMC21G15A Digital Analog Converter (DAC) */
SDADC_IRQn = 29, /**< 29 SAMC21G15A Sigma-Delta Analog Digital Converter (SDADC) */
PTC_IRQn = 30, /**< 30 SAMC21G15A Peripheral Touch Controller (PTC) */
PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNonMaskableInt_Handler;
void* pfnHardFault_Handler;
void* pvReservedM12;
void* pvReservedM11;
void* pvReservedM10;
void* pvReservedM9;
void* pvReservedM8;
void* pvReservedM7;
void* pvReservedM6;
void* pfnSVCall_Handler;
void* pvReservedM4;
void* pvReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
void* pfnWDT_Handler; /* 1 Watchdog Timer */
void* pfnRTC_Handler; /* 2 Real-Time Counter */
void* pfnEIC_Handler; /* 3 External Interrupt Controller */
void* pfnFREQM_Handler; /* 4 Frequency Meter */
void* pfnTSENS_Handler; /* 5 Temperature Sensor */
void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnCAN0_Handler; /* 15 Control Area Network 0 */
void* pfnCAN1_Handler; /* 16 Control Area Network 1 */
void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */
void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */
void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */
void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */
void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */
void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */
void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */
void* pfnAC_Handler; /* 27 Analog Comparators */
void* pfnDAC_Handler; /* 28 Digital Analog Converter */
void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */
void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void SVCall_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void SYSTEM_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void FREQM_Handler ( void );
void TSENS_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void SERCOM4_Handler ( void );
void SERCOM5_Handler ( void );
void CAN0_Handler ( void );
void CAN1_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void ADC0_Handler ( void );
void ADC1_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void SDADC_Handler ( void );
void PTC_Handler ( void );
/*
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* \brief CMSIS includes
*/
#include <core_cm0plus.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samc21.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21G15A */
/* ************************************************************************** */
/** \defgroup SAMC21G15A_api Peripheral Software API */
/*@{*/
#include "component/ac.h"
#include "component/adc.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/dac.h"
#include "component/divas.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/mclk.h"
#include "component/mtb.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdadc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/tsens.h"
#include "component/wdt.h"
/*@}*/
/* ************************************************************************** */
/** REGISTERS ACCESS DEFINITIONS FOR SAMC21G15A */
/* ************************************************************************** */
/** \defgroup SAMC21G15A_reg Registers Access Definitions */
/*@{*/
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/can0.h"
#include "instance/can1.h"
#include "instance/ccl.h"
#include "instance/dac.h"
#include "instance/divas.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/hmatrixhs.h"
#include "instance/mclk.h"
#include "instance/mtb.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/ptc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdadc.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/sercom4.h"
#include "instance/sercom5.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tsens.h"
#include "instance/wdt.h"
/*@}*/
/* ************************************************************************** */
/** PERIPHERAL ID DEFINITIONS FOR SAMC21G15A */
/* ************************************************************************** */
/** \defgroup SAMC21G15A_id Peripheral Ids Definitions */
/*@{*/
// Peripheral instances on HPB0 bridge
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM 1 /**< \brief Power Manager (PM) */
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */
// Peripheral instances on HPB1 bridge
#define ID_PORT 32 /**< \brief Port Module (PORT) */
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */
// Peripheral instances on HPB2 bridge
#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */
#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */
#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */
#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */
#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */
#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */
#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */
#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */
#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */
#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */
#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */
#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */
#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */
#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */
#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */
#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */
#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */
#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */
#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */
#define ID_AC 84 /**< \brief Analog Comparators (AC) */
#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */
#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */
#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */
// Peripheral instances on AHB (as if on bridge 3)
#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */
#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */
/*@}*/
/* ************************************************************************** */
/** BASE ADDRESS DEFINITIONS FOR SAMC21G15A */
/* ************************************************************************** */
/** \defgroup SAMC21G15A_base Peripheral Base Address Definitions */
/*@{*/
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42005000) /**< \brief (AC) APB Base Address */
#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */
#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */
#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */
#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */
#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */
#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */
#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */
#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */
#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */
#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */
#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */
#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */
#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */
#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */
#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */
#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */
#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
#else
#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */
#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */
#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */
#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */
#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */
#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */
#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */
#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */
#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */
#define PTC_GCLK_ID 37
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */
#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */
#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */
#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */
#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */
#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */
#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */
#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */
#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
/* ************************************************************************** */
/** PORT DEFINITIONS FOR SAMC21G15A */
/* ************************************************************************** */
/** \defgroup SAMC21G15A_port PORT Definitions */
/*@{*/
#include "pio/samc21g15a.h"
/*@}*/
/* ************************************************************************** */
/** MEMORY MAPPING DEFINITIONS FOR SAMC21G15A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */
#define FLASH_PAGE_SIZE 64
#define FLASH_NB_OF_PAGES 512
#define FLASH_USER_PAGE_SIZE 64
#define HSRAM_SIZE _UL_(0x00001000) /* 4 kB */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
#define DSU_DID_RESETVALUE _UL_(0x11010508)
#define AC_PAIRS 2
#define DMAC_CH_NUM 12
#define EVSYS_CHANNELS 12
#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000400) /* 1 kB */
#define PORT_GROUPS 2
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMC21G15A */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* SAMC21G15A_H */

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/**
* \file
*
* \brief Header file for SAMC21G16A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21G16A_
#define _SAMC21G16A_
/**
* \ingroup SAMC21_definitions
* \addtogroup SAMC21G16A_definitions SAMC21G16A definitions
* This file defines all structures and symbols for SAMC21G16A:
* - registers and bitfields
* - peripheral base address
* - peripheral ID
* - PIO definitions
*/
/*@{*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#else
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
#endif
#if !defined(SKIP_INTEGER_LITERALS)
#if defined(_U_) || defined(_L_) || defined(_UL_)
#error "Integer Literals macros already defined elsewhere"
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
#define _L_(x) x ## L /**< C code: Long integer literal constant value */
#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
#define _L_(x) x /**< Assembler: Long integer literal constant value */
#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/* ************************************************************************** */
/** CMSIS DEFINITIONS FOR SAMC21G16A */
/* ************************************************************************** */
/** \defgroup SAMC21G16A_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
/****** SAMC21G16A-specific Interrupt Numbers *********************/
SYSTEM_IRQn = 0, /**< 0 SAMC21G16A System Interrupts */
WDT_IRQn = 1, /**< 1 SAMC21G16A Watchdog Timer (WDT) */
RTC_IRQn = 2, /**< 2 SAMC21G16A Real-Time Counter (RTC) */
EIC_IRQn = 3, /**< 3 SAMC21G16A External Interrupt Controller (EIC) */
FREQM_IRQn = 4, /**< 4 SAMC21G16A Frequency Meter (FREQM) */
TSENS_IRQn = 5, /**< 5 SAMC21G16A Temperature Sensor (TSENS) */
NVMCTRL_IRQn = 6, /**< 6 SAMC21G16A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 7, /**< 7 SAMC21G16A Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMC21G16A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMC21G16A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMC21G16A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMC21G16A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMC21G16A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMC21G16A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMC21G16A Serial Communication Interface 5 (SERCOM5) */
CAN0_IRQn = 15, /**< 15 SAMC21G16A Control Area Network 0 (CAN0) */
CAN1_IRQn = 16, /**< 16 SAMC21G16A Control Area Network 1 (CAN1) */
TCC0_IRQn = 17, /**< 17 SAMC21G16A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 18, /**< 18 SAMC21G16A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 19, /**< 19 SAMC21G16A Timer Counter Control 2 (TCC2) */
TC0_IRQn = 20, /**< 20 SAMC21G16A Basic Timer Counter 0 (TC0) */
TC1_IRQn = 21, /**< 21 SAMC21G16A Basic Timer Counter 1 (TC1) */
TC2_IRQn = 22, /**< 22 SAMC21G16A Basic Timer Counter 2 (TC2) */
TC3_IRQn = 23, /**< 23 SAMC21G16A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 24, /**< 24 SAMC21G16A Basic Timer Counter 4 (TC4) */
ADC0_IRQn = 25, /**< 25 SAMC21G16A Analog Digital Converter 0 (ADC0) */
ADC1_IRQn = 26, /**< 26 SAMC21G16A Analog Digital Converter 1 (ADC1) */
AC_IRQn = 27, /**< 27 SAMC21G16A Analog Comparators (AC) */
DAC_IRQn = 28, /**< 28 SAMC21G16A Digital Analog Converter (DAC) */
SDADC_IRQn = 29, /**< 29 SAMC21G16A Sigma-Delta Analog Digital Converter (SDADC) */
PTC_IRQn = 30, /**< 30 SAMC21G16A Peripheral Touch Controller (PTC) */
PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNonMaskableInt_Handler;
void* pfnHardFault_Handler;
void* pvReservedM12;
void* pvReservedM11;
void* pvReservedM10;
void* pvReservedM9;
void* pvReservedM8;
void* pvReservedM7;
void* pvReservedM6;
void* pfnSVCall_Handler;
void* pvReservedM4;
void* pvReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
void* pfnWDT_Handler; /* 1 Watchdog Timer */
void* pfnRTC_Handler; /* 2 Real-Time Counter */
void* pfnEIC_Handler; /* 3 External Interrupt Controller */
void* pfnFREQM_Handler; /* 4 Frequency Meter */
void* pfnTSENS_Handler; /* 5 Temperature Sensor */
void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnCAN0_Handler; /* 15 Control Area Network 0 */
void* pfnCAN1_Handler; /* 16 Control Area Network 1 */
void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */
void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */
void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */
void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */
void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */
void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */
void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */
void* pfnAC_Handler; /* 27 Analog Comparators */
void* pfnDAC_Handler; /* 28 Digital Analog Converter */
void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */
void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void SVCall_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void SYSTEM_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void FREQM_Handler ( void );
void TSENS_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void SERCOM4_Handler ( void );
void SERCOM5_Handler ( void );
void CAN0_Handler ( void );
void CAN1_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void ADC0_Handler ( void );
void ADC1_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void SDADC_Handler ( void );
void PTC_Handler ( void );
/*
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* \brief CMSIS includes
*/
#include <core_cm0plus.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samc21.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21G16A */
/* ************************************************************************** */
/** \defgroup SAMC21G16A_api Peripheral Software API */
/*@{*/
#include "component/ac.h"
#include "component/adc.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/dac.h"
#include "component/divas.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/mclk.h"
#include "component/mtb.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdadc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/tsens.h"
#include "component/wdt.h"
/*@}*/
/* ************************************************************************** */
/** REGISTERS ACCESS DEFINITIONS FOR SAMC21G16A */
/* ************************************************************************** */
/** \defgroup SAMC21G16A_reg Registers Access Definitions */
/*@{*/
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/can0.h"
#include "instance/can1.h"
#include "instance/ccl.h"
#include "instance/dac.h"
#include "instance/divas.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/hmatrixhs.h"
#include "instance/mclk.h"
#include "instance/mtb.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/ptc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdadc.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/sercom4.h"
#include "instance/sercom5.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tsens.h"
#include "instance/wdt.h"
/*@}*/
/* ************************************************************************** */
/** PERIPHERAL ID DEFINITIONS FOR SAMC21G16A */
/* ************************************************************************** */
/** \defgroup SAMC21G16A_id Peripheral Ids Definitions */
/*@{*/
// Peripheral instances on HPB0 bridge
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM 1 /**< \brief Power Manager (PM) */
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */
// Peripheral instances on HPB1 bridge
#define ID_PORT 32 /**< \brief Port Module (PORT) */
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */
// Peripheral instances on HPB2 bridge
#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */
#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */
#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */
#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */
#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */
#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */
#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */
#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */
#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */
#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */
#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */
#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */
#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */
#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */
#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */
#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */
#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */
#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */
#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */
#define ID_AC 84 /**< \brief Analog Comparators (AC) */
#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */
#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */
#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */
// Peripheral instances on AHB (as if on bridge 3)
#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */
#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */
/*@}*/
/* ************************************************************************** */
/** BASE ADDRESS DEFINITIONS FOR SAMC21G16A */
/* ************************************************************************** */
/** \defgroup SAMC21G16A_base Peripheral Base Address Definitions */
/*@{*/
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42005000) /**< \brief (AC) APB Base Address */
#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */
#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */
#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */
#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */
#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */
#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */
#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */
#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */
#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */
#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */
#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */
#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */
#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */
#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */
#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */
#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */
#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
#else
#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */
#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */
#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */
#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */
#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */
#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */
#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */
#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */
#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */
#define PTC_GCLK_ID 37
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */
#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */
#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */
#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */
#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */
#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */
#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */
#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */
#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
/* ************************************************************************** */
/** PORT DEFINITIONS FOR SAMC21G16A */
/* ************************************************************************** */
/** \defgroup SAMC21G16A_port PORT Definitions */
/*@{*/
#include "pio/samc21g16a.h"
/*@}*/
/* ************************************************************************** */
/** MEMORY MAPPING DEFINITIONS FOR SAMC21G16A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */
#define FLASH_PAGE_SIZE 64
#define FLASH_NB_OF_PAGES 1024
#define FLASH_USER_PAGE_SIZE 64
#define HSRAM_SIZE _UL_(0x00002000) /* 8 kB */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
#define DSU_DID_RESETVALUE _UL_(0x11010507)
#define AC_PAIRS 2
#define DMAC_CH_NUM 12
#define EVSYS_CHANNELS 12
#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00000800) /* 2 kB */
#define PORT_GROUPS 2
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMC21G16A */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* SAMC21G16A_H */

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lib/samc21/samc21/include/samc21g17a.h Normal file
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/**
* \file
*
* \brief Header file for SAMC21G17A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21G17A_
#define _SAMC21G17A_
/**
* \ingroup SAMC21_definitions
* \addtogroup SAMC21G17A_definitions SAMC21G17A definitions
* This file defines all structures and symbols for SAMC21G17A:
* - registers and bitfields
* - peripheral base address
* - peripheral ID
* - PIO definitions
*/
/*@{*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#else
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
#endif
#if !defined(SKIP_INTEGER_LITERALS)
#if defined(_U_) || defined(_L_) || defined(_UL_)
#error "Integer Literals macros already defined elsewhere"
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
#define _L_(x) x ## L /**< C code: Long integer literal constant value */
#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
#define _L_(x) x /**< Assembler: Long integer literal constant value */
#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/* ************************************************************************** */
/** CMSIS DEFINITIONS FOR SAMC21G17A */
/* ************************************************************************** */
/** \defgroup SAMC21G17A_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
/****** SAMC21G17A-specific Interrupt Numbers *********************/
SYSTEM_IRQn = 0, /**< 0 SAMC21G17A System Interrupts */
WDT_IRQn = 1, /**< 1 SAMC21G17A Watchdog Timer (WDT) */
RTC_IRQn = 2, /**< 2 SAMC21G17A Real-Time Counter (RTC) */
EIC_IRQn = 3, /**< 3 SAMC21G17A External Interrupt Controller (EIC) */
FREQM_IRQn = 4, /**< 4 SAMC21G17A Frequency Meter (FREQM) */
TSENS_IRQn = 5, /**< 5 SAMC21G17A Temperature Sensor (TSENS) */
NVMCTRL_IRQn = 6, /**< 6 SAMC21G17A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 7, /**< 7 SAMC21G17A Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMC21G17A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMC21G17A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMC21G17A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMC21G17A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMC21G17A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMC21G17A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMC21G17A Serial Communication Interface 5 (SERCOM5) */
CAN0_IRQn = 15, /**< 15 SAMC21G17A Control Area Network 0 (CAN0) */
CAN1_IRQn = 16, /**< 16 SAMC21G17A Control Area Network 1 (CAN1) */
TCC0_IRQn = 17, /**< 17 SAMC21G17A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 18, /**< 18 SAMC21G17A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 19, /**< 19 SAMC21G17A Timer Counter Control 2 (TCC2) */
TC0_IRQn = 20, /**< 20 SAMC21G17A Basic Timer Counter 0 (TC0) */
TC1_IRQn = 21, /**< 21 SAMC21G17A Basic Timer Counter 1 (TC1) */
TC2_IRQn = 22, /**< 22 SAMC21G17A Basic Timer Counter 2 (TC2) */
TC3_IRQn = 23, /**< 23 SAMC21G17A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 24, /**< 24 SAMC21G17A Basic Timer Counter 4 (TC4) */
ADC0_IRQn = 25, /**< 25 SAMC21G17A Analog Digital Converter 0 (ADC0) */
ADC1_IRQn = 26, /**< 26 SAMC21G17A Analog Digital Converter 1 (ADC1) */
AC_IRQn = 27, /**< 27 SAMC21G17A Analog Comparators (AC) */
DAC_IRQn = 28, /**< 28 SAMC21G17A Digital Analog Converter (DAC) */
SDADC_IRQn = 29, /**< 29 SAMC21G17A Sigma-Delta Analog Digital Converter (SDADC) */
PTC_IRQn = 30, /**< 30 SAMC21G17A Peripheral Touch Controller (PTC) */
PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNonMaskableInt_Handler;
void* pfnHardFault_Handler;
void* pvReservedM12;
void* pvReservedM11;
void* pvReservedM10;
void* pvReservedM9;
void* pvReservedM8;
void* pvReservedM7;
void* pvReservedM6;
void* pfnSVCall_Handler;
void* pvReservedM4;
void* pvReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
void* pfnWDT_Handler; /* 1 Watchdog Timer */
void* pfnRTC_Handler; /* 2 Real-Time Counter */
void* pfnEIC_Handler; /* 3 External Interrupt Controller */
void* pfnFREQM_Handler; /* 4 Frequency Meter */
void* pfnTSENS_Handler; /* 5 Temperature Sensor */
void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnCAN0_Handler; /* 15 Control Area Network 0 */
void* pfnCAN1_Handler; /* 16 Control Area Network 1 */
void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */
void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */
void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */
void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */
void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */
void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */
void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */
void* pfnAC_Handler; /* 27 Analog Comparators */
void* pfnDAC_Handler; /* 28 Digital Analog Converter */
void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */
void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void SVCall_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void SYSTEM_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void FREQM_Handler ( void );
void TSENS_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void SERCOM4_Handler ( void );
void SERCOM5_Handler ( void );
void CAN0_Handler ( void );
void CAN1_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void ADC0_Handler ( void );
void ADC1_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void SDADC_Handler ( void );
void PTC_Handler ( void );
/*
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* \brief CMSIS includes
*/
#include <core_cm0plus.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samc21.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21G17A */
/* ************************************************************************** */
/** \defgroup SAMC21G17A_api Peripheral Software API */
/*@{*/
#include "component/ac.h"
#include "component/adc.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/dac.h"
#include "component/divas.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/mclk.h"
#include "component/mtb.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdadc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/tsens.h"
#include "component/wdt.h"
/*@}*/
/* ************************************************************************** */
/** REGISTERS ACCESS DEFINITIONS FOR SAMC21G17A */
/* ************************************************************************** */
/** \defgroup SAMC21G17A_reg Registers Access Definitions */
/*@{*/
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/can0.h"
#include "instance/can1.h"
#include "instance/ccl.h"
#include "instance/dac.h"
#include "instance/divas.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/hmatrixhs.h"
#include "instance/mclk.h"
#include "instance/mtb.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/ptc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdadc.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/sercom4.h"
#include "instance/sercom5.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tsens.h"
#include "instance/wdt.h"
/*@}*/
/* ************************************************************************** */
/** PERIPHERAL ID DEFINITIONS FOR SAMC21G17A */
/* ************************************************************************** */
/** \defgroup SAMC21G17A_id Peripheral Ids Definitions */
/*@{*/
// Peripheral instances on HPB0 bridge
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM 1 /**< \brief Power Manager (PM) */
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */
// Peripheral instances on HPB1 bridge
#define ID_PORT 32 /**< \brief Port Module (PORT) */
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */
// Peripheral instances on HPB2 bridge
#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */
#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */
#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */
#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */
#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */
#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */
#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */
#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */
#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */
#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */
#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */
#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */
#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */
#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */
#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */
#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */
#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */
#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */
#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */
#define ID_AC 84 /**< \brief Analog Comparators (AC) */
#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */
#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */
#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */
// Peripheral instances on AHB (as if on bridge 3)
#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */
#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */
/*@}*/
/* ************************************************************************** */
/** BASE ADDRESS DEFINITIONS FOR SAMC21G17A */
/* ************************************************************************** */
/** \defgroup SAMC21G17A_base Peripheral Base Address Definitions */
/*@{*/
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42005000) /**< \brief (AC) APB Base Address */
#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */
#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */
#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */
#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */
#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */
#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */
#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */
#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */
#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */
#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */
#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */
#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */
#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */
#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */
#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */
#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */
#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
#else
#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */
#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */
#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */
#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */
#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */
#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */
#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */
#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */
#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */
#define PTC_GCLK_ID 37
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */
#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */
#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */
#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */
#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */
#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */
#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */
#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */
#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
/* ************************************************************************** */
/** PORT DEFINITIONS FOR SAMC21G17A */
/* ************************************************************************** */
/** \defgroup SAMC21G17A_port PORT Definitions */
/*@{*/
#include "pio/samc21g17a.h"
/*@}*/
/* ************************************************************************** */
/** MEMORY MAPPING DEFINITIONS FOR SAMC21G17A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */
#define FLASH_PAGE_SIZE 64
#define FLASH_NB_OF_PAGES 2048
#define FLASH_USER_PAGE_SIZE 64
#define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
#define DSU_DID_RESETVALUE _UL_(0x11010506)
#define AC_PAIRS 2
#define DMAC_CH_NUM 12
#define EVSYS_CHANNELS 12
#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */
#define PORT_GROUPS 2
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMC21G17A */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* SAMC21G17A_H */

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/**
* \file
*
* \brief Header file for SAMC21G18A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAMC21G18A_
#define _SAMC21G18A_
/**
* \ingroup SAMC21_definitions
* \addtogroup SAMC21G18A_definitions SAMC21G18A definitions
* This file defines all structures and symbols for SAMC21G18A:
* - registers and bitfields
* - peripheral base address
* - peripheral ID
* - PIO definitions
*/
/*@{*/
#ifdef __cplusplus
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#include <stdint.h>
#ifndef __cplusplus
typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#else
typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */
typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */
#endif
typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */
typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */
typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */
typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */
#endif
#if !defined(SKIP_INTEGER_LITERALS)
#if defined(_U_) || defined(_L_) || defined(_UL_)
#error "Integer Literals macros already defined elsewhere"
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */
#define _L_(x) x ## L /**< C code: Long integer literal constant value */
#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */
#else /* Assembler */
#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
#define _L_(x) x /**< Assembler: Long integer literal constant value */
#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* SKIP_INTEGER_LITERALS */
/* ************************************************************************** */
/** CMSIS DEFINITIONS FOR SAMC21G18A */
/* ************************************************************************** */
/** \defgroup SAMC21G18A_cmsis CMSIS Definitions */
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers *******************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 System Tick Interrupt */
/****** SAMC21G18A-specific Interrupt Numbers *********************/
SYSTEM_IRQn = 0, /**< 0 SAMC21G18A System Interrupts */
WDT_IRQn = 1, /**< 1 SAMC21G18A Watchdog Timer (WDT) */
RTC_IRQn = 2, /**< 2 SAMC21G18A Real-Time Counter (RTC) */
EIC_IRQn = 3, /**< 3 SAMC21G18A External Interrupt Controller (EIC) */
FREQM_IRQn = 4, /**< 4 SAMC21G18A Frequency Meter (FREQM) */
TSENS_IRQn = 5, /**< 5 SAMC21G18A Temperature Sensor (TSENS) */
NVMCTRL_IRQn = 6, /**< 6 SAMC21G18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 7, /**< 7 SAMC21G18A Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMC21G18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMC21G18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMC21G18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMC21G18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMC21G18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMC21G18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMC21G18A Serial Communication Interface 5 (SERCOM5) */
CAN0_IRQn = 15, /**< 15 SAMC21G18A Control Area Network 0 (CAN0) */
CAN1_IRQn = 16, /**< 16 SAMC21G18A Control Area Network 1 (CAN1) */
TCC0_IRQn = 17, /**< 17 SAMC21G18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 18, /**< 18 SAMC21G18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 19, /**< 19 SAMC21G18A Timer Counter Control 2 (TCC2) */
TC0_IRQn = 20, /**< 20 SAMC21G18A Basic Timer Counter 0 (TC0) */
TC1_IRQn = 21, /**< 21 SAMC21G18A Basic Timer Counter 1 (TC1) */
TC2_IRQn = 22, /**< 22 SAMC21G18A Basic Timer Counter 2 (TC2) */
TC3_IRQn = 23, /**< 23 SAMC21G18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 24, /**< 24 SAMC21G18A Basic Timer Counter 4 (TC4) */
ADC0_IRQn = 25, /**< 25 SAMC21G18A Analog Digital Converter 0 (ADC0) */
ADC1_IRQn = 26, /**< 26 SAMC21G18A Analog Digital Converter 1 (ADC1) */
AC_IRQn = 27, /**< 27 SAMC21G18A Analog Comparators (AC) */
DAC_IRQn = 28, /**< 28 SAMC21G18A Digital Analog Converter (DAC) */
SDADC_IRQn = 29, /**< 29 SAMC21G18A Sigma-Delta Analog Digital Converter (SDADC) */
PTC_IRQn = 30, /**< 30 SAMC21G18A Peripheral Touch Controller (PTC) */
PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNonMaskableInt_Handler;
void* pfnHardFault_Handler;
void* pvReservedM12;
void* pvReservedM11;
void* pvReservedM10;
void* pvReservedM9;
void* pvReservedM8;
void* pvReservedM7;
void* pvReservedM6;
void* pfnSVCall_Handler;
void* pvReservedM4;
void* pvReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
void* pfnWDT_Handler; /* 1 Watchdog Timer */
void* pfnRTC_Handler; /* 2 Real-Time Counter */
void* pfnEIC_Handler; /* 3 External Interrupt Controller */
void* pfnFREQM_Handler; /* 4 Frequency Meter */
void* pfnTSENS_Handler; /* 5 Temperature Sensor */
void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnCAN0_Handler; /* 15 Control Area Network 0 */
void* pfnCAN1_Handler; /* 16 Control Area Network 1 */
void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */
void* pfnTC0_Handler; /* 20 Basic Timer Counter 0 */
void* pfnTC1_Handler; /* 21 Basic Timer Counter 1 */
void* pfnTC2_Handler; /* 22 Basic Timer Counter 2 */
void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */
void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */
void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */
void* pfnAC_Handler; /* 27 Analog Comparators */
void* pfnDAC_Handler; /* 28 Digital Analog Converter */
void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */
void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
void Reset_Handler ( void );
void NonMaskableInt_Handler ( void );
void HardFault_Handler ( void );
void SVCall_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void SYSTEM_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void FREQM_Handler ( void );
void TSENS_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void SERCOM4_Handler ( void );
void SERCOM5_Handler ( void );
void CAN0_Handler ( void );
void CAN1_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC0_Handler ( void );
void TC1_Handler ( void );
void TC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void ADC0_Handler ( void );
void ADC1_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void SDADC_Handler ( void );
void PTC_Handler ( void );
/*
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */
#define __VTOR_PRESENT 1 /*!< VTOR present or not */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
* \brief CMSIS includes
*/
#include <core_cm0plus.h>
#if !defined DONT_USE_CMSIS_INIT
#include "system_samc21.h"
#endif /* DONT_USE_CMSIS_INIT */
/*@}*/
/* ************************************************************************** */
/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21G18A */
/* ************************************************************************** */
/** \defgroup SAMC21G18A_api Peripheral Software API */
/*@{*/
#include "component/ac.h"
#include "component/adc.h"
#include "component/can.h"
#include "component/ccl.h"
#include "component/dac.h"
#include "component/divas.h"
#include "component/dmac.h"
#include "component/dsu.h"
#include "component/eic.h"
#include "component/evsys.h"
#include "component/freqm.h"
#include "component/gclk.h"
#include "component/hmatrixb.h"
#include "component/mclk.h"
#include "component/mtb.h"
#include "component/nvmctrl.h"
#include "component/oscctrl.h"
#include "component/osc32kctrl.h"
#include "component/pac.h"
#include "component/pm.h"
#include "component/port.h"
#include "component/rstc.h"
#include "component/rtc.h"
#include "component/sdadc.h"
#include "component/sercom.h"
#include "component/supc.h"
#include "component/tc.h"
#include "component/tcc.h"
#include "component/tsens.h"
#include "component/wdt.h"
/*@}*/
/* ************************************************************************** */
/** REGISTERS ACCESS DEFINITIONS FOR SAMC21G18A */
/* ************************************************************************** */
/** \defgroup SAMC21G18A_reg Registers Access Definitions */
/*@{*/
#include "instance/ac.h"
#include "instance/adc0.h"
#include "instance/adc1.h"
#include "instance/can0.h"
#include "instance/can1.h"
#include "instance/ccl.h"
#include "instance/dac.h"
#include "instance/divas.h"
#include "instance/dmac.h"
#include "instance/dsu.h"
#include "instance/eic.h"
#include "instance/evsys.h"
#include "instance/freqm.h"
#include "instance/gclk.h"
#include "instance/hmatrixhs.h"
#include "instance/mclk.h"
#include "instance/mtb.h"
#include "instance/nvmctrl.h"
#include "instance/oscctrl.h"
#include "instance/osc32kctrl.h"
#include "instance/pac.h"
#include "instance/pm.h"
#include "instance/port.h"
#include "instance/ptc.h"
#include "instance/rstc.h"
#include "instance/rtc.h"
#include "instance/sdadc.h"
#include "instance/sercom0.h"
#include "instance/sercom1.h"
#include "instance/sercom2.h"
#include "instance/sercom3.h"
#include "instance/sercom4.h"
#include "instance/sercom5.h"
#include "instance/supc.h"
#include "instance/tc0.h"
#include "instance/tc1.h"
#include "instance/tc2.h"
#include "instance/tc3.h"
#include "instance/tc4.h"
#include "instance/tcc0.h"
#include "instance/tcc1.h"
#include "instance/tcc2.h"
#include "instance/tsens.h"
#include "instance/wdt.h"
/*@}*/
/* ************************************************************************** */
/** PERIPHERAL ID DEFINITIONS FOR SAMC21G18A */
/* ************************************************************************** */
/** \defgroup SAMC21G18A_id Peripheral Ids Definitions */
/*@{*/
// Peripheral instances on HPB0 bridge
#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */
#define ID_PM 1 /**< \brief Power Manager (PM) */
#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */
#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */
#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */
#define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */
#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */
#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */
#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */
#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */
#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */
#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */
#define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */
// Peripheral instances on HPB1 bridge
#define ID_PORT 32 /**< \brief Port Module (PORT) */
#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */
#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */
#define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */
#define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */
#define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */
// Peripheral instances on HPB2 bridge
#define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */
#define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */
#define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */
#define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */
#define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */
#define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */
#define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */
#define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */
#define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */
#define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */
#define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */
#define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */
#define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */
#define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */
#define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */
#define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */
#define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */
#define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */
#define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */
#define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */
#define ID_AC 84 /**< \brief Analog Comparators (AC) */
#define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */
#define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */
#define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */
// Peripheral instances on AHB (as if on bridge 3)
#define ID_DIVAS 96 /**< \brief Divide and Square Root Accelerator (DIVAS) */
#define ID_PERIPH_COUNT 97 /**< \brief Max number of peripheral IDs */
/*@}*/
/* ************************************************************************** */
/** BASE ADDRESS DEFINITIONS FOR SAMC21G18A */
/* ************************************************************************** */
/** \defgroup SAMC21G18A_base Peripheral Base Address Definitions */
/*@{*/
#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)
#define AC (0x42005000) /**< \brief (AC) APB Base Address */
#define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */
#define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */
#define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */
#define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */
#define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */
#define DAC (0x42005400) /**< \brief (DAC) APB Base Address */
#define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */
#define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */
#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */
#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */
#define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */
#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */
#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */
#define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */
#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */
#define MTB (0x41008000) /**< \brief (MTB) APB Base Address */
#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */
#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */
#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */
#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */
#define PM (0x40000400) /**< \brief (PM) APB Base Address */
#define PORT (0x41000000) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */
#define PTC (0x42005800) /**< \brief (PTC) APB Base Address */
#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */
#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */
#define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */
#define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */
#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */
#define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */
#define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */
#define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */
#define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */
#define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */
#define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */
#define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */
#define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */
#define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */
#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */
#else
#define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */
#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */
#define AC_INSTS { AC } /**< \brief (AC) Instances List */
#define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */
#define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */
#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */
#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */
#define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */
#define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */
#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */
#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */
#define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */
#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */
#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */
#define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */
#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */
#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */
#define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */
#define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */
#define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */
#define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */
#define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */
#define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */
#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */
#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */
#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */
#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */
#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */
#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */
#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */
#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */
#define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */
#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */
#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */
#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */
#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */
#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */
#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */
#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */
#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
#define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */
#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */
#define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */
#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */
#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */
#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */
#define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */
#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */
#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */
#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
#define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */
#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */
#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */
#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */
#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */
#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */
#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */
#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */
#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */
#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */
#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */
#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */
#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */
#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */
#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */
#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */
#define PM_INSTS { PM } /**< \brief (PM) Instances List */
#define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */
#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */
#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */
#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */
#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */
#define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */
#define PTC_GCLK_ID 37
#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */
#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */
#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */
#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */
#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */
#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */
#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */
#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */
#define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */
#define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */
#define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */
#define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */
#define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */
#define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */
#define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */
#define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */
#define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */
#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */
#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */
#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */
#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */
#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */
#define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */
#define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */
#define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */
#define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */
#define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */
#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */
#define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
#define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */
#define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */
#define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */
#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */
#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */
#define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */
#define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */
#define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */
#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */
#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */
#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/*@}*/
/* ************************************************************************** */
/** PORT DEFINITIONS FOR SAMC21G18A */
/* ************************************************************************** */
/** \defgroup SAMC21G18A_port PORT Definitions */
/*@{*/
#include "pio/samc21g18a.h"
/*@}*/
/* ************************************************************************** */
/** MEMORY MAPPING DEFINITIONS FOR SAMC21G18A */
/* ************************************************************************** */
#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */
#define FLASH_PAGE_SIZE 64
#define FLASH_NB_OF_PAGES 4096
#define FLASH_USER_PAGE_SIZE 64
#define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */
#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */
#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */
#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */
#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */
#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */
#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */
#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */
#define DSU_DID_RESETVALUE _UL_(0x11010505)
#define AC_PAIRS 2
#define DMAC_CH_NUM 12
#define EVSYS_CHANNELS 12
#define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */
#define PORT_GROUPS 2
/* ************************************************************************** */
/** ELECTRICAL DEFINITIONS FOR SAMC21G18A */
/* ************************************************************************** */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* SAMC21G18A_H */

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