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88 lines
5.5 KiB
C
88 lines
5.5 KiB
C
/**
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* \file
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*
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* \brief Instance description for SDADC
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMC21_SDADC_INSTANCE_
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#define _SAMC21_SDADC_INSTANCE_
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/* ========== Register definition for SDADC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SDADC_CTRLA (0x42004C00) /**< \brief (SDADC) Control A */
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#define REG_SDADC_REFCTRL (0x42004C01) /**< \brief (SDADC) Reference Control */
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#define REG_SDADC_CTRLB (0x42004C02) /**< \brief (SDADC) Control B */
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#define REG_SDADC_EVCTRL (0x42004C04) /**< \brief (SDADC) Event Control */
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#define REG_SDADC_INTENCLR (0x42004C05) /**< \brief (SDADC) Interrupt Enable Clear */
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#define REG_SDADC_INTENSET (0x42004C06) /**< \brief (SDADC) Interrupt Enable Set */
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#define REG_SDADC_INTFLAG (0x42004C07) /**< \brief (SDADC) Interrupt Flag Status and Clear */
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#define REG_SDADC_SEQSTATUS (0x42004C08) /**< \brief (SDADC) Sequence Status */
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#define REG_SDADC_INPUTCTRL (0x42004C09) /**< \brief (SDADC) Input Control */
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#define REG_SDADC_CTRLC (0x42004C0A) /**< \brief (SDADC) Control C */
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#define REG_SDADC_WINCTRL (0x42004C0B) /**< \brief (SDADC) Window Monitor Control */
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#define REG_SDADC_WINLT (0x42004C0C) /**< \brief (SDADC) Window Monitor Lower Threshold */
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#define REG_SDADC_WINUT (0x42004C10) /**< \brief (SDADC) Window Monitor Upper Threshold */
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#define REG_SDADC_OFFSETCORR (0x42004C14) /**< \brief (SDADC) Offset Correction */
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#define REG_SDADC_GAINCORR (0x42004C18) /**< \brief (SDADC) Gain Correction */
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#define REG_SDADC_SHIFTCORR (0x42004C1A) /**< \brief (SDADC) Shift Correction */
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#define REG_SDADC_SWTRIG (0x42004C1C) /**< \brief (SDADC) Software Trigger */
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#define REG_SDADC_SYNCBUSY (0x42004C20) /**< \brief (SDADC) Synchronization Busy */
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#define REG_SDADC_RESULT (0x42004C24) /**< \brief (SDADC) Result */
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#define REG_SDADC_SEQCTRL (0x42004C28) /**< \brief (SDADC) Sequence Control */
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#define REG_SDADC_ANACTRL (0x42004C2C) /**< \brief (SDADC) Analog Control */
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#define REG_SDADC_DBGCTRL (0x42004C2E) /**< \brief (SDADC) Debug Control */
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#else
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#define REG_SDADC_CTRLA (*(RwReg8 *)0x42004C00UL) /**< \brief (SDADC) Control A */
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#define REG_SDADC_REFCTRL (*(RwReg8 *)0x42004C01UL) /**< \brief (SDADC) Reference Control */
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#define REG_SDADC_CTRLB (*(RwReg16*)0x42004C02UL) /**< \brief (SDADC) Control B */
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#define REG_SDADC_EVCTRL (*(RwReg8 *)0x42004C04UL) /**< \brief (SDADC) Event Control */
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#define REG_SDADC_INTENCLR (*(RwReg8 *)0x42004C05UL) /**< \brief (SDADC) Interrupt Enable Clear */
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#define REG_SDADC_INTENSET (*(RwReg8 *)0x42004C06UL) /**< \brief (SDADC) Interrupt Enable Set */
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#define REG_SDADC_INTFLAG (*(RwReg8 *)0x42004C07UL) /**< \brief (SDADC) Interrupt Flag Status and Clear */
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#define REG_SDADC_SEQSTATUS (*(RoReg8 *)0x42004C08UL) /**< \brief (SDADC) Sequence Status */
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#define REG_SDADC_INPUTCTRL (*(RwReg8 *)0x42004C09UL) /**< \brief (SDADC) Input Control */
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#define REG_SDADC_CTRLC (*(RwReg8 *)0x42004C0AUL) /**< \brief (SDADC) Control C */
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#define REG_SDADC_WINCTRL (*(RwReg8 *)0x42004C0BUL) /**< \brief (SDADC) Window Monitor Control */
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#define REG_SDADC_WINLT (*(RwReg *)0x42004C0CUL) /**< \brief (SDADC) Window Monitor Lower Threshold */
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#define REG_SDADC_WINUT (*(RwReg *)0x42004C10UL) /**< \brief (SDADC) Window Monitor Upper Threshold */
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#define REG_SDADC_OFFSETCORR (*(RwReg *)0x42004C14UL) /**< \brief (SDADC) Offset Correction */
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#define REG_SDADC_GAINCORR (*(RwReg16*)0x42004C18UL) /**< \brief (SDADC) Gain Correction */
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#define REG_SDADC_SHIFTCORR (*(RwReg8 *)0x42004C1AUL) /**< \brief (SDADC) Shift Correction */
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#define REG_SDADC_SWTRIG (*(RwReg8 *)0x42004C1CUL) /**< \brief (SDADC) Software Trigger */
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#define REG_SDADC_SYNCBUSY (*(RoReg *)0x42004C20UL) /**< \brief (SDADC) Synchronization Busy */
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#define REG_SDADC_RESULT (*(RoReg *)0x42004C24UL) /**< \brief (SDADC) Result */
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#define REG_SDADC_SEQCTRL (*(RwReg8 *)0x42004C28UL) /**< \brief (SDADC) Sequence Control */
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#define REG_SDADC_ANACTRL (*(RwReg8 *)0x42004C2CUL) /**< \brief (SDADC) Analog Control */
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#define REG_SDADC_DBGCTRL (*(RwReg8 *)0x42004C2EUL) /**< \brief (SDADC) Debug Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for SDADC peripheral ========== */
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#define SDADC_DMAC_ID_RESRDY 44 // Index of DMA RESRDY trigger
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#define SDADC_EXT_CHANNELS 3 // Number of external channels
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#define SDADC_GCLK_ID 35 // Index of generic clock
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#endif /* _SAMC21_SDADC_INSTANCE_ */
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