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90 lines
5.6 KiB
C
90 lines
5.6 KiB
C
/**
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* \file
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*
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* \brief Instance description for ADC0
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMC21_ADC0_INSTANCE_
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#define _SAMC21_ADC0_INSTANCE_
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/* ========== Register definition for ADC0 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_ADC0_CTRLA (0x42004400) /**< \brief (ADC0) Control A */
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#define REG_ADC0_CTRLB (0x42004401) /**< \brief (ADC0) Control B */
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#define REG_ADC0_REFCTRL (0x42004402) /**< \brief (ADC0) Reference Control */
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#define REG_ADC0_EVCTRL (0x42004403) /**< \brief (ADC0) Event Control */
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#define REG_ADC0_INTENCLR (0x42004404) /**< \brief (ADC0) Interrupt Enable Clear */
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#define REG_ADC0_INTENSET (0x42004405) /**< \brief (ADC0) Interrupt Enable Set */
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#define REG_ADC0_INTFLAG (0x42004406) /**< \brief (ADC0) Interrupt Flag Status and Clear */
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#define REG_ADC0_SEQSTATUS (0x42004407) /**< \brief (ADC0) Sequence Status */
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#define REG_ADC0_INPUTCTRL (0x42004408) /**< \brief (ADC0) Input Control */
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#define REG_ADC0_CTRLC (0x4200440A) /**< \brief (ADC0) Control C */
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#define REG_ADC0_AVGCTRL (0x4200440C) /**< \brief (ADC0) Average Control */
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#define REG_ADC0_SAMPCTRL (0x4200440D) /**< \brief (ADC0) Sample Time Control */
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#define REG_ADC0_WINLT (0x4200440E) /**< \brief (ADC0) Window Monitor Lower Threshold */
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#define REG_ADC0_WINUT (0x42004410) /**< \brief (ADC0) Window Monitor Upper Threshold */
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#define REG_ADC0_GAINCORR (0x42004412) /**< \brief (ADC0) Gain Correction */
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#define REG_ADC0_OFFSETCORR (0x42004414) /**< \brief (ADC0) Offset Correction */
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#define REG_ADC0_SWTRIG (0x42004418) /**< \brief (ADC0) Software Trigger */
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#define REG_ADC0_DBGCTRL (0x4200441C) /**< \brief (ADC0) Debug Control */
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#define REG_ADC0_SYNCBUSY (0x42004420) /**< \brief (ADC0) Synchronization Busy */
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#define REG_ADC0_RESULT (0x42004424) /**< \brief (ADC0) Result */
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#define REG_ADC0_SEQCTRL (0x42004428) /**< \brief (ADC0) Sequence Control */
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#define REG_ADC0_CALIB (0x4200442C) /**< \brief (ADC0) Calibration */
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#else
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#define REG_ADC0_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (ADC0) Control A */
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#define REG_ADC0_CTRLB (*(RwReg8 *)0x42004401UL) /**< \brief (ADC0) Control B */
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#define REG_ADC0_REFCTRL (*(RwReg8 *)0x42004402UL) /**< \brief (ADC0) Reference Control */
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#define REG_ADC0_EVCTRL (*(RwReg8 *)0x42004403UL) /**< \brief (ADC0) Event Control */
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#define REG_ADC0_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (ADC0) Interrupt Enable Clear */
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#define REG_ADC0_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (ADC0) Interrupt Enable Set */
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#define REG_ADC0_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (ADC0) Interrupt Flag Status and Clear */
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#define REG_ADC0_SEQSTATUS (*(RoReg8 *)0x42004407UL) /**< \brief (ADC0) Sequence Status */
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#define REG_ADC0_INPUTCTRL (*(RwReg16*)0x42004408UL) /**< \brief (ADC0) Input Control */
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#define REG_ADC0_CTRLC (*(RwReg16*)0x4200440AUL) /**< \brief (ADC0) Control C */
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#define REG_ADC0_AVGCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (ADC0) Average Control */
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#define REG_ADC0_SAMPCTRL (*(RwReg8 *)0x4200440DUL) /**< \brief (ADC0) Sample Time Control */
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#define REG_ADC0_WINLT (*(RwReg16*)0x4200440EUL) /**< \brief (ADC0) Window Monitor Lower Threshold */
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#define REG_ADC0_WINUT (*(RwReg16*)0x42004410UL) /**< \brief (ADC0) Window Monitor Upper Threshold */
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#define REG_ADC0_GAINCORR (*(RwReg16*)0x42004412UL) /**< \brief (ADC0) Gain Correction */
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#define REG_ADC0_OFFSETCORR (*(RwReg16*)0x42004414UL) /**< \brief (ADC0) Offset Correction */
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#define REG_ADC0_SWTRIG (*(RwReg8 *)0x42004418UL) /**< \brief (ADC0) Software Trigger */
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#define REG_ADC0_DBGCTRL (*(RwReg8 *)0x4200441CUL) /**< \brief (ADC0) Debug Control */
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#define REG_ADC0_SYNCBUSY (*(RoReg16*)0x42004420UL) /**< \brief (ADC0) Synchronization Busy */
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#define REG_ADC0_RESULT (*(RoReg16*)0x42004424UL) /**< \brief (ADC0) Result */
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#define REG_ADC0_SEQCTRL (*(RwReg *)0x42004428UL) /**< \brief (ADC0) Sequence Control */
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#define REG_ADC0_CALIB (*(RwReg16*)0x4200442CUL) /**< \brief (ADC0) Calibration */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for ADC0 peripheral ========== */
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#define ADC0_DMAC_ID_RESRDY 42 // index of DMA RESRDY trigger
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#define ADC0_EXTCHANNEL_MSB 11 // Number of external channels
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#define ADC0_GCLK_ID 33 // index of Generic Clock
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#define ADC0_INT_CH30 0 // Select OPAMP or CTAT on Channel 30
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#define ADC0_MASTER_SLAVE_MODE 1 // ADC Master/Slave Mode
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#endif /* _SAMC21_ADC0_INSTANCE_ */
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