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andreili 2024-09-30 01:21:31 +02:00
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3
.gitignore vendored Normal file
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build/*
work_dir/ROMs/Sjasm
*.user

100
CMakeLists.txt Normal file
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cmake_minimum_required(VERSION 3.16)
project(OriVEmu VERSION 0.1 LANGUAGES CXX)
find_package(QT NAMES Qt6 Qt5 REQUIRED COMPONENTS Widgets)
find_package(Qt${QT_VERSION_MAJOR} REQUIRED COMPONENTS Widgets)
find_package(Verilator REQUIRED)
add_library(Vemulate STATIC sim_wrappers/sim_top.cpp
.gitignore
sim_common/common/tb.h
sim_common/common/tb.cpp
sim_wrappers/sim_top.cpp
sim_wrappers/sim_top.h)
add_definitions(-DTOP_NAME=emulate -DTO_SIM)
target_include_directories(Vemulate PRIVATE sim_common/common)
target_include_directories(Vemulate PRIVATE /usr/include/qt${QT_VERSION_MAJOR})
target_include_directories(Vemulate PRIVATE /usr/include/qt${QT_VERSION_MAJOR}/QtCore)
set_property(TARGET Vemulate PROPERTY POSITION_INDEPENDENT_CODE ON)
verilate(Vemulate
PREFIX Vemulate
INCLUDE_DIRS "rtl"
INCLUDE_DIRS "rtl/TV80-verilog"
SOURCES rtl/emulate.sv
THREADS 1
TOP_MODULE emulate)
# -x-assign fast -Wall
#VERILATOR_ARGS --timescale-override 1ps/1ps
# --no-timing
set(CMAKE_AUTOUIC ON)
set(CMAKE_AUTOMOC ON)
set(CMAKE_AUTORCC ON)
set(CMAKE_CXX_STANDARD 17)
set(CMAKE_CXX_STANDARD_REQUIRED ON)
set(PROJECT_SOURCES
gui/main.cpp
gui/mainwindow.cpp
gui/mainwindow.h
gui/mainwindow.ui
sim_wrappers/kbd.hpp
sim_wrappers/gui_output.hpp
)
if(${QT_VERSION_MAJOR} GREATER_EQUAL 6)
qt_add_executable(OriVEmu
MANUAL_FINALIZATION
${PROJECT_SOURCES}
)
# Define target properties for Android with Qt 6 as:
# set_property(TARGET OriVEmu APPEND PROPERTY QT_ANDROID_PACKAGE_SOURCE_DIR
# ${CMAKE_CURRENT_SOURCE_DIR}/android)
# For more information, see https://doc.qt.io/qt-6/qt-add-executable.html#target-creation
else()
if(ANDROID)
add_library(OriVEmu SHARED
${PROJECT_SOURCES}
)
# Define properties for Android with Qt 5 after find_package() calls as:
# set(ANDROID_PACKAGE_SOURCE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/android")
else()
add_executable(OriVEmu
${PROJECT_SOURCES}
)
endif()
endif()
target_link_libraries(OriVEmu PRIVATE Qt${QT_VERSION_MAJOR}::Widgets)
target_link_libraries(OriVEmu PRIVATE Vemulate)
target_include_directories(OriVEmu PRIVATE sim_wrappers)
# Qt for iOS sets MACOSX_BUNDLE_GUI_IDENTIFIER automatically since Qt 6.1.
# If you are developing for iOS or macOS you should consider setting an
# explicit, fixed bundle identifier manually though.
if(${QT_VERSION} VERSION_LESS 6.1.0)
set(BUNDLE_ID_OPTION MACOSX_BUNDLE_GUI_IDENTIFIER com.example.OriVEmu)
endif()
set_target_properties(OriVEmu PROPERTIES
${BUNDLE_ID_OPTION}
MACOSX_BUNDLE_BUNDLE_VERSION ${PROJECT_VERSION}
MACOSX_BUNDLE_SHORT_VERSION_STRING ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}
MACOSX_BUNDLE TRUE
WIN32_EXECUTABLE TRUE
)
include(GNUInstallDirs)
install(TARGETS OriVEmu
BUNDLE DESTINATION .
LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR}
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}
)
if(QT_VERSION_MAJOR EQUAL 6)
qt_finalize_executable(OriVEmu)
endif()

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gui/main.cpp Normal file
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#include "mainwindow.h"
#include <QApplication>
int main(int argc, char *argv[])
{
QApplication a(argc, argv);
MainWindow w;
w.show();
return a.exec();
}

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<?xml version="1.0" encoding="UTF-8"?>
<ui version="4.0">
<class>MainWindow</class>
<widget class="QMainWindow" name="MainWindow">
<property name="geometry">
<rect>
<x>0</x>
<y>0</y>
<width>627</width>
<height>409</height>
</rect>
</property>
<property name="windowTitle">
<string>MainWindow</string>
</property>
<widget class="QWidget" name="centralwidget">
<widget class="QWidget" name="widget" native="true">
<property name="geometry">
<rect>
<x>0</x>
<y>0</y>
<width>512</width>
<height>256</height>
</rect>
</property>
</widget>
</widget>
<widget class="QMenuBar" name="menubar">
<property name="geometry">
<rect>
<x>0</x>
<y>0</y>
<width>627</width>
<height>34</height>
</rect>
</property>
</widget>
<widget class="QStatusBar" name="statusbar"/>
</widget>
<resources/>
<connections/>
</ui>

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gui/mainwindow.cpp Normal file
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#include "mainwindow.h"
#include "./ui_mainwindow.h"
#include <QPainter>
MainWindow* p_mw;
MainWindow::MainWindow(QWidget *parent)
: QMainWindow(parent)
, ui(new Ui::MainWindow)
{
p_mw = this;
ui->setupUi(this);
QStringList args = QCoreApplication::arguments();
const char* argv[10];
for (size_t i=0 ; i<1 ; ++i)
{
if (i < args.size())
{
argv[i] = args[i].toStdString().c_str();
}
else
{
argv[i] = NULL;
}
}
sim = new SIM_TOP(args.size(), argv, thread_start_draw, thread_resize);
connect(this, SIGNAL(start_draw()), SLOT(draw()));
connect(this, SIGNAL(start_resize()), SLOT(resize_window()));
image_scr = new QImage();
cur_zoom = 1;
ui->actionx1->setChecked(true);
status_screen = new QLabel();
//ui->statusbar->addPermanentWidget(status_screen);
}
MainWindow::~MainWindow()
{
delete ui;
}
void MainWindow::thread_start_draw()
{
emit p_mw->start_draw();
}
void MainWindow::thread_resize()
{
p_mw->scr_h = p_mw->sim->get_height();
p_mw->scr_w = p_mw->sim->get_width();
if (p_mw->image_scr->width() != p_mw->scr_w)
{
delete p_mw->image_scr;
p_mw->image_scr = new QImage(p_mw->scr_w, p_mw->scr_h, QImage::Format_RGB32);
emit p_mw->start_resize();
//p_mw->sim->set_screen((uint32_t*)p_mw->image_scr->data_ptr());
}
}
void MainWindow::resize_window()
{
setMaximumSize(scr_w * cur_zoom, scr_h * cur_zoom);
ui->label->setMaximumSize(scr_w * cur_zoom, scr_h * cur_zoom);
}
void MainWindow::draw()
{
memcpy(image_scr->bits(), sim->get_screen(), image_scr->sizeInBytes());
QImage img = image_scr->scaled(scr_w * cur_zoom, scr_h * cur_zoom);
this->ui->label->setPixmap(QPixmap::fromImage(img));
status_screen->setText(QString("%1:%2").arg(scr_w, scr_h));
}
void MainWindow::on_actionx1_triggered()
{
ui->actionx2->setChecked(false);
ui->actionx3->setChecked(false);
ui->actionx4->setChecked(false);
cur_zoom = 1;
resize_window();
}
void MainWindow::on_actionx2_triggered()
{
ui->actionx1->setChecked(false);
ui->actionx3->setChecked(false);
ui->actionx4->setChecked(false);
cur_zoom = 2;
resize_window();
}
void MainWindow::on_actionx3_triggered()
{
ui->actionx1->setChecked(false);
ui->actionx2->setChecked(false);
ui->actionx4->setChecked(false);
cur_zoom = 3;
resize_window();
}
void MainWindow::on_actionx4_triggered()
{
ui->actionx1->setChecked(false);
ui->actionx2->setChecked(false);
ui->actionx3->setChecked(false);
cur_zoom = 4;
resize_window();
}
void MainWindow::keyPressEvent(QKeyEvent *evt)
{
if (this->isActiveWindow())
{
//
}
//this->p_kbd->add_event(evt);
}
void MainWindow::keyReleaseEvent(QKeyEvent *evt)
{
if (this->isActiveWindow())
{
//
}
//this->p_kbd->add_event(evt);
}
void MainWindow::closeEvent(QCloseEvent *evt)
{
sim->stop();
evt->accept();
}

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gui/mainwindow.h Normal file
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#ifndef MAINWINDOW_H
#define MAINWINDOW_H
#include <QMainWindow>
#include <QPainter>
#include <QImage>
#include <QLabel>
#include <QCloseEvent>
#include "sim_top.h"
QT_BEGIN_NAMESPACE
namespace Ui {
class MainWindow;
}
QT_END_NAMESPACE
class MainWindow : public QMainWindow
{
Q_OBJECT
public:
MainWindow(QWidget *parent = nullptr);
~MainWindow();
private:
Ui::MainWindow *ui;
SIM_TOP *sim;
QImage *image_scr;
int cur_zoom;
int scr_h, scr_w;
QLabel *status_screen;
static void thread_start_draw();
static void thread_resize();
public slots:
void resize_window();
void draw();
void keyPressEvent(QKeyEvent *evt);
void keyReleaseEvent(QKeyEvent *evt);
void closeEvent(QCloseEvent *evt);
signals:
void start_draw();
void start_resize();
private slots:
void on_actionx1_triggered();
void on_actionx2_triggered();
void on_actionx3_triggered();
void on_actionx4_triggered();
};
#endif // MAINWINDOW_H

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<?xml version="1.0" encoding="UTF-8"?>
<ui version="4.0">
<class>MainWindow</class>
<widget class="QMainWindow" name="MainWindow">
<property name="geometry">
<rect>
<x>0</x>
<y>0</y>
<width>800</width>
<height>600</height>
</rect>
</property>
<property name="sizePolicy">
<sizepolicy hsizetype="Minimum" vsizetype="Minimum">
<horstretch>0</horstretch>
<verstretch>0</verstretch>
</sizepolicy>
</property>
<property name="windowTitle">
<string>OrionPro Verilog Emulator/Simulator</string>
</property>
<widget class="QWidget" name="centralwidget">
<layout class="QGridLayout" name="gridLayout">
<item row="0" column="0">
<widget class="QLabel" name="label">
<property name="mouseTracking">
<bool>false</bool>
</property>
<property name="focusPolicy">
<enum>Qt::FocusPolicy::NoFocus</enum>
</property>
<property name="text">
<string>TextLabel</string>
</property>
</widget>
</item>
</layout>
</widget>
<widget class="QMenuBar" name="menubar">
<property name="geometry">
<rect>
<x>0</x>
<y>0</y>
<width>800</width>
<height>23</height>
</rect>
</property>
<widget class="QMenu" name="menuDebugger">
<property name="title">
<string>Debugger</string>
</property>
</widget>
<widget class="QMenu" name="menuSettings">
<property name="title">
<string>Settings</string>
</property>
</widget>
<widget class="QMenu" name="menuView">
<property name="title">
<string>View</string>
</property>
<addaction name="actionx1"/>
<addaction name="actionx2"/>
<addaction name="actionx3"/>
<addaction name="actionx4"/>
</widget>
<addaction name="menuDebugger"/>
<addaction name="menuSettings"/>
<addaction name="menuView"/>
</widget>
<widget class="QStatusBar" name="statusbar"/>
<action name="actionx1">
<property name="checkable">
<bool>true</bool>
</property>
<property name="checked">
<bool>true</bool>
</property>
<property name="text">
<string>&amp;x1</string>
</property>
</action>
<action name="actionx2">
<property name="checkable">
<bool>true</bool>
</property>
<property name="text">
<string>x&amp;2</string>
</property>
</action>
<action name="actionx3">
<property name="checkable">
<bool>true</bool>
</property>
<property name="text">
<string>x&amp;3</string>
</property>
</action>
<action name="actionx4">
<property name="checkable">
<bool>true</bool>
</property>
<property name="text">
<string>x&amp;4</string>
</property>
</action>
</widget>
<resources/>
<connections/>
</ui>

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rtl/TV80-verilog/tv80_alu.v Normal file
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`timescale 1ps/1ps
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* verilator lint_off UNUSEDSIGNAL */
module tv80_alu (/*AUTOARG*/
// Outputs
Q, F_Out,
// Inputs
Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
);
parameter Mode = 0;
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
input Arith16;
input Z16;
input [3:0] ALU_Op ;
input [5:0] IR;
input [1:0] ISet;
input [7:0] BusA;
input [7:0] BusB;
input [7:0] F_In;
output [7:0] Q;
output [7:0] F_Out;
reg [7:0] Q;
reg [7:0] F_Out;
function [4:0] AddSub4;
input [3:0] A;
input [3:0] B;
input Sub;
input Carry_In;
begin
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In};
end
endfunction // AddSub4
function [3:0] AddSub3;
input [2:0] A;
input [2:0] B;
input Sub;
input Carry_In;
begin
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In};
end
endfunction // AddSub4
function [1:0] AddSub1;
input A;
input B;
input Sub;
input Carry_In;
begin
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In};
end
endfunction // AddSub4
// AddSub variables (temporary signals)
reg UseCarry;
reg Carry7_v;
reg OverFlow_v;
reg HalfCarry_v;
reg Carry_v;
reg [7:0] Q_v;
reg [7:0] BitMask;
always_comb
begin
case (IR[5:3])
3'b000 : BitMask = 8'b00000001;
3'b001 : BitMask = 8'b00000010;
3'b010 : BitMask = 8'b00000100;
3'b011 : BitMask = 8'b00001000;
3'b100 : BitMask = 8'b00010000;
3'b101 : BitMask = 8'b00100000;
3'b110 : BitMask = 8'b01000000;
default: BitMask = 8'b10000000;
endcase // case(IR[5:3])
UseCarry = ~ ALU_Op[2] && ALU_Op[0];
{ HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
{ Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
{ Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
OverFlow_v = Carry_v ^ Carry7_v;
end // always @ *
reg [7:0] Q_t;
reg [8:0] DAA_Q;
always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
or Carry_v or F_In or HalfCarry_v or IR or ISet
or OverFlow_v or Q_v or Z16)
begin
Q_t = 8'hxx;
DAA_Q = {9{1'bx}};
F_Out = F_In;
case (ALU_Op)
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
begin
F_Out[Flag_N] = 1'b0;
F_Out[Flag_C] = 1'b0;
case (ALU_Op[2:0])
3'b000, 3'b001 : // ADD, ADC
begin
Q_t = Q_v;
F_Out[Flag_C] = Carry_v;
F_Out[Flag_H] = HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
begin
Q_t = Q_v;
F_Out[Flag_N] = 1'b1;
F_Out[Flag_C] = ~ Carry_v;
F_Out[Flag_H] = ~ HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b100 : // AND
begin
Q_t[7:0] = BusA & BusB;
F_Out[Flag_H] = 1'b1;
end
3'b101 : // XOR
begin
Q_t[7:0] = BusA ^ BusB;
F_Out[Flag_H] = 1'b0;
end
default : // OR 3'b110
begin
Q_t[7:0] = BusA | BusB;
F_Out[Flag_H] = 1'b0;
end
endcase // case(ALU_OP[2:0])
if (ALU_Op[2:0] == 3'b111 )
begin // CP
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
else
begin
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
end
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
if (Z16 == 1'b1 )
begin
F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC
end
end
else
begin
F_Out[Flag_Z] = 1'b0;
end // else: !if(Q_t[7:0] == 8'b00000000 )
F_Out[Flag_S] = Q_t[7];
case (ALU_Op[2:0])
3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
;
default :
F_Out[Flag_P] = ~(^Q_t);
endcase // case(ALU_Op[2:0])
if (Arith16 == 1'b1 )
begin
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
F_Out[Flag_P] = F_In[Flag_P];
end
end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
4'b1100 :
begin
// DAA
F_Out[Flag_H] = F_In[Flag_H];
F_Out[Flag_C] = F_In[Flag_C];
DAA_Q[7:0] = BusA;
DAA_Q[8] = 1'b0;
if (F_In[Flag_N] == 1'b0 )
begin
// After addition
// Alow > 9 || H == 1
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if ((DAA_Q[3:0] > 9) )
begin
F_Out[Flag_H] = 1'b1;
end
else
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q = DAA_Q + 6;
end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
// new Ahigh > 9 || C == 1
if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q + 96; // 0x60
end
end
else
begin
// After subtraction
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if (DAA_Q[3:0] > 5 )
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q[7:0] = DAA_Q[7:0] - 6;
end
if (BusA > 153 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q - 352; // 0x160
end
end // else: !if(F_In[Flag_N] == 1'b0 )
F_Out[Flag_X] = DAA_Q[3];
F_Out[Flag_Y] = DAA_Q[5];
F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
Q_t = DAA_Q[7:0];
if (DAA_Q[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = DAA_Q[7];
F_Out[Flag_P] = ~ (^DAA_Q);
end // case: 4'b1100
4'b1101, 4'b1110 :
begin
// RLD, RRD
Q_t[7:4] = BusA[7:4];
if (ALU_Op[0] == 1'b1 )
begin
Q_t[3:0] = BusB[7:4];
end
else
begin
Q_t[3:0] = BusB[3:0];
end
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = Q_t[7];
F_Out[Flag_P] = ~(^Q_t);
end // case: when 4'b1101, 4'b1110
4'b1001 :
begin
// BIT
Q_t[7:0] = BusB & BitMask;
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
F_Out[Flag_P] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
F_Out[Flag_P] = 1'b0;
end
F_Out[Flag_H] = 1'b1;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = 1'b0;
F_Out[Flag_Y] = 1'b0;
if (IR[2:0] != 3'b110 )
begin
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
end // case: when 4'b1001
4'b1010 :
// SET
Q_t[7:0] = BusB | BitMask;
4'b1011 :
// RES
Q_t[7:0] = BusB & ~ BitMask;
4'b1000 :
begin
// ROT
case (IR[5:3])
3'b000 : // RLC
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = BusA[7];
F_Out[Flag_C] = BusA[7];
end
3'b010 : // RL
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = F_In[Flag_C];
F_Out[Flag_C] = BusA[7];
end
3'b001 : // RRC
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[0];
F_Out[Flag_C] = BusA[0];
end
3'b011 : // RR
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = F_In[Flag_C];
F_Out[Flag_C] = BusA[0];
end
3'b100 : // SLA
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b0;
F_Out[Flag_C] = BusA[7];
end
3'b110 : // SLL (Undocumented) / SWAP
begin
if (Mode == 3 )
begin
Q_t[7:4] = BusA[3:0];
Q_t[3:0] = BusA[7:4];
F_Out[Flag_C] = 1'b0;
end
else
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b1;
F_Out[Flag_C] = BusA[7];
end // else: !if(Mode == 3 )
end // case: 3'b110
3'b101 : // SRA
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[7];
F_Out[Flag_C] = BusA[0];
end
default : // SRL
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = 1'b0;
F_Out[Flag_C] = BusA[0];
end
endcase // case(IR[5:3])
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_P] = ~(^Q_t);
if (ISet == 2'b00 )
begin
F_Out[Flag_P] = F_In[Flag_P];
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
end
end // case: 4'b1000
default :
;
endcase // case(ALU_Op)
Q = Q_t;
end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
endmodule // T80_ALU
/* verilator lint_on UNUSEDSIGNAL */

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`timescale 1ps/1ps
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* verilator lint_off UNUSEDSIGNAL */
module tv80_reg (/*AUTOARG*/
// Outputs
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
// Inputs
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
reg [7:0] RegsH [0:7];
reg [7:0] RegsL [0:7];
always @(posedge clk)
begin
if (CEN)
begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
// break out ram bits for waveform debug
// synopsys translate_off
wire [7:0] B = RegsH[0];
wire [7:0] C = RegsL[0];
wire [7:0] D = RegsH[1];
wire [7:0] E = RegsL[1];
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
wire [15:0] IX = { RegsH[3], RegsL[3] };
wire [15:0] IY = { RegsH[7], RegsL[7] };
// synopsys translate_on
endmodule
/* verilator lint_on UNUSEDSIGNAL */

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`timescale 1ps/1ps
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
//
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/* verilator lint_off UNUSEDSIGNAL */
/* verilator lint_off PINCONNECTEMPTY */
module tv80s (/*AUTOARG*/
// Outputs
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
// Inputs
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di, cen
);
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
input reset_n;
input clk;
input cen;
input wait_n;
input int_n;
input nmi_n;
input busrq_n;
output m1_n;
output mreq_n;
output iorq_n;
output rd_n;
output wr_n;
output rfsh_n;
output halt_n;
output busak_n;
output [15:0] A;
input [7:0] di;
output [7:0] dout;
reg mreq_n;
reg iorq_n;
reg rd_n;
reg wr_n;
wire intcycle_n;
wire no_read;
wire write;
wire iorq;
reg [7:0] di_reg;
wire [6:0] mcycle;
wire [6:0] tstate;
tv80_core #(Mode, IOWait) i_tv80_core
(
.cen (cen),
.m1_n (m1_n),
.iorq (iorq),
.no_read (no_read),
.write (write),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.reset_n (reset_n),
.busrq_n (busrq_n),
.busak_n (busak_n),
.clk (clk),
.IntE (),
.stop (),
.A (A),
.dinst (di),
.di (di_reg),
.dout (dout),
.mc (mcycle),
.ts (tstate),
.intcycle_n (intcycle_n)
);
always @(posedge clk)
begin
if (!reset_n)
begin
rd_n <= 1'b1;
wr_n <= 1'b1;
iorq_n <= 1'b1;
mreq_n <= 1'b1;
di_reg <= 0;
end
else if(cen)
begin
rd_n <= 1'b1;
wr_n <= 1'b1;
iorq_n <= 1'b1;
mreq_n <= 1'b1;
if (mcycle[0])
begin
if (tstate[1] || (tstate[2] && wait_n == 1'b0))
begin
rd_n <= ~ intcycle_n;
mreq_n <= ~ intcycle_n;
iorq_n <= intcycle_n;
end
`ifdef TV80_REFRESH
if (tstate[3])
mreq_n <= 1'b0;
`endif
end // if (mcycle[0])
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
begin
rd_n <= 1'b0;
iorq_n <= ~ iorq;
mreq_n <= iorq;
end
if (T2Write == 0)
begin
if (tstate[2] && write == 1'b1)
begin
wr_n <= 1'b0;
iorq_n <= ~ iorq;
mreq_n <= iorq;
end
end
else
begin
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
begin
wr_n <= 1'b0;
iorq_n <= ~ iorq;
mreq_n <= iorq;
end
end // else: !if(T2write == 0)
end // else: !if(mcycle[0])
if (tstate[2] && wait_n == 1'b1)
di_reg <= di;
end // else: !if(!reset_n)
end // always @ (posedge clk)
endmodule // t80s
/* verilator lint_on PINCONNECTEMPTY */
/* verilator lint_on UNUSEDSIGNAL */

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`timescale 1ps/1ps
module clk_sel
(
input wire i_clk1,
input wire i_clk2,
input wire i_sel,
output wire o_clk
);
logic and11, and12, and21, and22;
logic[1:0] sync1, sync2;
assign and11 = (!i_sel) & (!sync2[1]);
assign and12 = (!sync1[1]) & i_sel;
always_ff @(posedge i_clk1)
sync1 <= { sync1[0], and11 };
always_ff @(posedge i_clk2)
sync2 <= { sync2[0], and12 };
assign and21 = sync1[1] & i_clk1;
assign and22 = sync2[1] & i_clk2;
assign o_clk = and21 | and22;
endmodule

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`timescale 1ps/1ps
module emulate
(
input wire i_clk,
input wire i_reset_n
);
orion_pro_top
#(
.TURBO_CLK_10 (1'b1)
)
u_orion_core
(
.i_clk (i_clk),
.i_reset_n (i_reset_n),
.i_cfg_sw (8'b0000_1011)
);
endmodule

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`timescale 1ps/1ps
module i8255
(
input wire i_clk,
input wire[1:0] i_addr,
input wire[7:0] i_data,
output wire[7:0] o_data,
input wire i_rd_n,
input wire i_wr_n,
input wire i_cs_n,
input wire i_reset,
input wire[7:0] i_PA,
output wire[7:0] o_PA,
input wire[7:0] i_PB,
output wire[7:0] o_PB,
input wire[7:0] i_PC,
output wire[7:0] o_PC
);
logic[7:0] reg_A;
logic[7:0] reg_B;
logic[7:0] reg_C;
logic[7:0] control_reg;
logic[7:0] Ain;
logic[7:0] Bin;
logic[7:0] Cin;
logic[3:0] Cinl;
logic[3:0] Cinh;
always_ff @(posedge i_clk)
begin
if (i_reset)
begin
reg_A <= '0;
reg_B <= '0;
reg_C <= '0;
control_reg <= 8'h9B;
end
else if ((!i_cs_n) & (!i_wr_n))
begin
case (i_addr)
2'b00: reg_A <= i_data;
2'b01: reg_B <= i_data;
2'b10: reg_C <= i_data;
2'b11:
begin
if (i_data[7] == 1'b1) // immediate value
control_reg <= i_data;
else // set/reset bit in port C
begin
if (i_data[1] == '1) // set bit
reg_C[i_data[3:1]] <= '1;
else // reset bit
reg_C[i_data[3:1]] <= '0;
end
end
endcase
end
end
logic[7:0] reg_o_A, reg_o_B, reg_o_C;
always_ff @(posedge i_clk)
begin
if (control_reg[4] == '0)
reg_o_A <= reg_A;
if (control_reg[1] == '0)
reg_o_B <= reg_B;
if (control_reg[0] == '0)
reg_o_C[3:0] <= reg_C[3:0];
if (control_reg[3] == '0)
reg_o_C[7:4] <= reg_C[7:4];
end;
assign o_PA = reg_o_A;
assign o_PB = reg_o_B;
assign o_PC = reg_o_C;
assign Cinl = control_reg[0] ? i_PC[3:0] : reg_C[3:0];
assign Bin = control_reg[1] ? i_PB : reg_B;
assign Cinh = control_reg[3] ? i_PC[7:4] : reg_C[7:4];
assign Ain = control_reg[4] ? i_PA : reg_A;
assign Cin = { Cinh, Cinl };
logic[7:0] r_data;
always_ff @(posedge i_clk)
begin
if ((!i_cs_n) & (!i_rd_n))
begin
case (i_addr)
2'b00: r_data <= Ain;
2'b01: r_data <= Bin;
2'b10: r_data <= Cin;
2'b11: r_data <= control_reg;
endcase;
end
end;
assign o_data = r_data;
endmodule

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`timescale 1ps/1ps
/* verilator lint_off UNUSEDSIGNAL */
module orion_pro_top
#(
parameter logic TURBO_CLK_10 = 1'b1
)
(
input wire i_clk,
input wire i_reset_n,
input wire[7:0] i_cfg_sw
);
////
logic blio = 1'b1;
////
logic o128_mode, ram0_en, ram1_en, ram2_en, rom1_en, rom2_en, turbo_n, top_mem_en;
logic[7:0] ram_page_pro, rom2_addr, ram0_page, ram1_page, ram2_page;
logic ctrl_FB_erom, ctrl_FB_xmem, ctrl_FB_int, ctrl_FB_mz;
logic[1:0] ctrl_FB_SS;
logic[2:0] ctrl_FB_BS;
logic[1:0] clk_div;
logic turbo_clk, cpu_clk;
always_ff @(posedge i_clk)
begin
clk_div <= clk_div + 1'b1;
end
assign turbo_clk = TURBO_CLK_10 ? i_clk : clk_div[0];
clk_sel
u_clk_sel
(
.i_clk1 (clk_div[1]),
.i_clk2 (turbo_clk),
.i_sel (turbo_n),
.o_clk (cpu_clk)
);
logic reset_n_sync_0, reset_n_sync_1;
logic reset_n;
always_ff @(posedge i_clk)
reset_n_sync_0 <= i_reset_n;
always_ff @(posedge cpu_clk)
begin
reset_n_sync_1 <= reset_n_sync_0;
reset_n <= reset_n_sync_1;
end
logic cpu_m1_n, cpu_mreq_n, cpu_wr_n, cpu_rd_n, cpu_iorq_n;
logic cpu_rfsh_n, cpu_halt_n, cpu_busak_n;
logic[7:0] cpu_wdata, cpu_rdata;
logic[15:0] cpu_addr;
tv80s
u_cpu
(
// Outputs
.m1_n (cpu_m1_n),
.mreq_n (cpu_mreq_n),
.iorq_n (cpu_iorq_n),
.rd_n (cpu_rd_n),
.wr_n (cpu_wr_n),
.rfsh_n (cpu_rfsh_n),
.halt_n (cpu_halt_n),
.busak_n (cpu_busak_n),
.A (cpu_addr),
.dout (cpu_wdata),
// Inputs
.reset_n (reset_n),
.clk (cpu_clk),
.wait_n ('1),
.int_n ('1),
.nmi_n ('1),
.busrq_n ('1),
.di (cpu_rdata),
.cen ('1)
);
logic[4:0] r_ctrl_f9;
logic[7:0] r_ctrl_1a;
logic[7:0] r_ctrl_1b;
logic[7:0] r_ctrl_1c;
logic[7:0] r_ctrl_2a;
logic[7:0] r_ctrl_2b;
logic[7:0] r_ctrl_2c;
logic w_sel_mem;
logic w_sel_mem_f4, w_sel_mem_f8, w_sel_mem_f9, w_sel_mem_fa;
logic w_sel_io;
logic w_sel_io_f8, w_sel_io_f9, w_sel_io_fa, w_sel_io_fb, w_sel_io_fc;
logic w_sel_io_00, w_sel_io_01, w_sel_io_02, w_sel_io_06;
logic w_sel_io_0a, w_sel_io_0b;
logic w_sel_f9_write, w_sel_fb_write;
logic w_sel_01_write, w_sel_02_write;
logic w_erom;
logic[4:0] w_ram_page;
logic[4:0] video_mode /* verilator public */;
logic[7:0] screen_mode /* verilator public */;
logic[7:0] colors_pseudo /* verilator public */;
// IO/MEM ports addresses
assign w_sel_mem = ~(cpu_mreq_n | ~cpu_rfsh_n) & o128_mode;
assign w_sel_io = ~cpu_iorq_n;
assign w_sel_mem_f4 = (cpu_addr[15:8] == 8'hf4) & w_sel_mem;
assign w_sel_mem_f8 = (cpu_addr[15:8] == 8'hf8) & w_sel_mem;
assign w_sel_mem_f9 = (cpu_addr[15:8] == 8'hf9) & w_sel_mem;
assign w_sel_mem_fa = (cpu_addr[15:8] == 8'hfa) & w_sel_mem;
assign w_sel_io_00 = (cpu_addr[7:2] == 6'h00) & w_sel_io; //00..03
assign w_sel_io_01 = (cpu_addr[7:2] == 6'h01) & w_sel_io; //04..07
assign w_sel_io_02 = (cpu_addr[7:2] == 6'h02) & w_sel_io; //08..0b
//...
assign w_sel_io_06 = (cpu_addr[7:2] == 6'h06) & w_sel_io; //18..1b
//...
assign w_sel_io_0a = (cpu_addr[7:2] == 6'h0a) & w_sel_io; //28..2b
assign w_sel_io_0b = (cpu_addr[7:2] == 6'h0b) & w_sel_io; //2c..2f
assign w_sel_io_f8 = (cpu_addr[7:0] == 8'hf8) & w_sel_io;
assign w_sel_io_f9 = (cpu_addr[7:0] == 8'hf9) & w_sel_io;
assign w_sel_io_fa = (cpu_addr[7:0] == 8'hfa) & w_sel_io;
assign w_sel_io_fb = (cpu_addr[7:0] == 8'hfb) & w_sel_io;
assign w_sel_io_fc = (cpu_addr[7:0] == 8'hfc) & w_sel_io;
// port 01
assign w_sel_01_write = w_sel_io_01 & (~cpu_wr_n);
always @(posedge cpu_clk)
begin
if (~reset_n)
begin
r_ctrl_1a <= '0;
r_ctrl_1b <= '0;
r_ctrl_1c <= '0;
end
else if (w_sel_io_02 & (cpu_addr[1:0] == 2'b00) & (~cpu_wr_n))
r_ctrl_1a <= cpu_wdata;
else if (w_sel_io_02 & (cpu_addr[1:0] == 2'b01) & (~cpu_wr_n))
r_ctrl_1b <= cpu_wdata;
else if (w_sel_io_02 & (cpu_addr[1:0] == 2'b10) & (~cpu_wr_n))
r_ctrl_1c <= cpu_wdata;
end
assign ram_page_pro = r_ctrl_1a;
assign rom2_addr = r_ctrl_1b;
assign ram0_en = r_ctrl_1c[0];
assign ram1_en = r_ctrl_1c[1];
assign ram2_en = r_ctrl_1c[2];
assign rom2_en = r_ctrl_1c[3];
assign rom1_en = r_ctrl_1c[4];
assign turbo_n = r_ctrl_1c[5];
assign top_mem_en = r_ctrl_1c[6];
assign o128_mode = r_ctrl_1c[7];
// port 02
always @(posedge cpu_clk)
begin
if (~reset_n)
begin
r_ctrl_2a <= '0;
r_ctrl_2b <= '0;
r_ctrl_2c <= '0;
end
else if (w_sel_io_01 & (cpu_addr[1:0] == 2'b00) & (~cpu_wr_n))
r_ctrl_2a <= cpu_wdata;
else if (w_sel_io_01 & (cpu_addr[1:0] == 2'b01) & (~cpu_wr_n))
r_ctrl_2b <= cpu_wdata;
else if (w_sel_io_01 & (cpu_addr[1:0] == 2'b10) & (~cpu_wr_n))
r_ctrl_2c <= cpu_wdata;
end
assign ram0_page = r_ctrl_2a;
assign ram1_page = r_ctrl_2b;
assign ram2_page = r_ctrl_2c;
assign w_ram_page = r_ctrl_f9;
always @(posedge cpu_clk)
begin
if (~reset_n)
begin
ctrl_FB_SS <= '0;
ctrl_FB_BS <= '0;
ctrl_FB_xmem <= '0;
ctrl_FB_int <= '0;
ctrl_FB_mz <= '0;
ctrl_FB_erom <= '1;
r_ctrl_f9 <= '0;
video_mode <= '0;
screen_mode <= '0;
colors_pseudo <= '0;
end
else if ((w_sel_mem_f8 | w_sel_io_f8) & (~cpu_wr_n))
begin
ctrl_FB_erom <= '0;
video_mode <= cpu_wdata[4:0];
end
else if ((w_sel_mem_f9 | w_sel_io_f9) & (~cpu_wr_n))
begin
r_ctrl_f9 <= cpu_wdata[4:0];
end
else if ((w_sel_mem_fa | w_sel_io_fa) & (~cpu_wr_n))
begin
screen_mode <= cpu_wdata;
end
else if (w_sel_io_fb & (~cpu_wr_n))
begin
ctrl_FB_SS <= cpu_wdata[1:0];
ctrl_FB_BS <= cpu_wdata[4:2];
ctrl_FB_xmem <= cpu_wdata[5];
ctrl_FB_int <= cpu_wdata[6];
ctrl_FB_mz <= cpu_wdata[7];
end
else if (w_sel_io_fc & (~cpu_wr_n))
begin
colors_pseudo <= cpu_wdata;
end
end
logic ctrl_mz;
assign w_erom = rom1_en | ctrl_FB_erom;
//assign intn = !(ctrl_FB_int & frame_end);
assign ctrl_mz = (!ctrl_FB_mz) & o128_mode & (!cpu_addr[15]) & (!cpu_addr[14]);
assign cpu_rdata = (w_sel_io_00 & (!cpu_rd_n) & (cpu_addr[1:0] == 2'b00)) ? i_cfg_sw :
(w_sel_io_02 & (!cpu_rd_n) & (cpu_addr[1:0] == 2'b00)) ? r_ctrl_1a :
(w_sel_io_02 & (!cpu_rd_n) & (cpu_addr[1:0] == 2'b01)) ? r_ctrl_1b :
(w_sel_io_02 & (!cpu_rd_n) & (cpu_addr[1:0] == 2'b10)) ? r_ctrl_1c :
(w_sel_io_01 & (!cpu_rd_n) & (cpu_addr[1:0] == 2'b00)) ? r_ctrl_2a :
(w_sel_io_01 & (!cpu_rd_n) & (cpu_addr[1:0] == 2'b01)) ? r_ctrl_2b :
(w_sel_io_01 & (!cpu_rd_n) & (cpu_addr[1:0] == 2'b10)) ? r_ctrl_2c :
((w_sel_mem_f9 | w_sel_io_f9) & (!cpu_rd_n)) ? { 3'b0, r_ctrl_f9 } :
'z;
// memory management for all modes
logic mem_hi, mem_fxxx, mem_top;
logic[2:0] mb;
logic[20:14] mem_addr_hi;
assign mem_hi = cpu_addr[12] & cpu_addr[13] & cpu_addr[14] & cpu_addr[15];
assign mem_fxxx = mem_hi & o128_mode;
assign mem_top = mem_hi & (o128_mode | top_mem_en);
assign mb[0] = ram0_en & (!cpu_addr[14]) & (!cpu_addr[15]); // RAM0
assign mb[1] = ram1_en & cpu_addr[14] & (!cpu_addr[15]); // RAM1
assign mb[2] = ram2_en & (!cpu_addr[14]) & cpu_addr[15]; // RAM2
assign mem_addr_hi = ctrl_mz ? { 2'b00, ctrl_FB_BS, ctrl_FB_SS }
: mem_top ? { 5'b0_0111, cpu_addr[15:14] } // segment 0x1f!!!
: mb[0] ? r_ctrl_2a[6:0]
: mb[1] ? r_ctrl_2b[6:0]
: mb[2] ? r_ctrl_2c[6:0]
: o128_mode ? { w_ram_page, cpu_addr[15:14] }
: { ram_page_pro[4:0], cpu_addr[15:14] };
// ROM selection
logic rom_sel, rom1_sel, rom2_sel;
assign rom_sel = cpu_iorq_n & (!cpu_addr[15]) & (!cpu_addr[14]);
assign rom1_sel = rom_sel & (!cpu_addr[13]) & (rom1_en | ctrl_FB_erom);
assign rom2_sel = rom_sel & cpu_addr[13] & rom2_en;
logic blram, mem_blk, mem_rd_en, mem_wrn, mem_rdn, mem_req;
assign blram = rom1_sel | rom2_sel | (cpu_mreq_n | ~cpu_rfsh_n);
assign mem_blk = (((cpu_addr[10] | cpu_addr[11]) & mem_fxxx) & (!ctrl_FB_xmem));
assign mem_rd_en = (!mem_blk) | cpu_addr[11];
assign mem_wrn = cpu_wr_n | mem_blk | blram;
assign mem_rdn = cpu_rd_n | (!mem_rd_en) | blram;
assign mem_req = !(mem_wrn & mem_rdn);
// ROM's
logic[7:0] rom_1[8*1024];
logic[7:0] rom_2[1024*1024];
logic[19:0] rom2_addr_full;
assign cpu_rdata = (rom1_sel & (!cpu_rd_n)) ? rom_1[cpu_addr[12:0]] : 'z;
assign rom2_addr_full = { rom2_addr[6:0], cpu_addr[12:0] };
assign cpu_rdata = (rom2_sel & (!cpu_rd_n)) ? rom_2[rom2_addr_full] : 'z;
// RAM's
logic[7:0] ram[1024*1024*2] /* verilator public */;
logic[20:0] ram_addr;
logic[7:0] ram_rdata;
assign ram_addr = { mem_addr_hi, cpu_addr[13:0] };
always_ff @(posedge cpu_clk)
begin
if (!mem_wrn)
ram[ram_addr] <= cpu_wdata;
end
assign ram_rdata = ram[ram_addr];
assign cpu_rdata = (!mem_rdn) ? ram_rdata : 'z;
// keyboard
logic sel_kbd;
logic[7:0] kbd_rdata;
logic[23:0] kbd_input /* verilator public */;
logic[23:0] kbd_output /* verilator public */;
assign sel_kbd = w_sel_mem_f4 | w_sel_io_06;
i8255
u_kbd_io
(
.i_clk (cpu_clk),
.i_addr (cpu_addr[1:0]),
.i_data (cpu_wdata),
.o_data (kbd_rdata),
.i_rd_n (cpu_rd_n),
.i_wr_n (cpu_wr_n),
.i_cs_n (!sel_kbd),
.i_reset (!reset_n),
.i_PA (kbd_input[7:0]),
.o_PA (kbd_output[7:0]),
.i_PB (kbd_input[15:8]),
.o_PB (kbd_output[15:8]),
.i_PC (kbd_input[23:16]),
.o_PC (kbd_output[23:16])
);
assign cpu_rdata = sel_kbd ? kbd_rdata : 'z;
// ROM disk
logic[7:0] rom_dsk_page;
logic[15:0] rom_dsk_addr_lo;
logic[7:0] rom_dsk_data, rom_rdata;
logic[7:0] rom_dsk[1024*1024];
always @(posedge cpu_clk)
begin
if (~reset_n)
begin
rom_dsk_page <= '0;
end
/*else if (w_sel_io_0b & (~cpu_wr_n))
rom_dsk_page <= cpu_wdata;*/
end
/* verilator lint_off PINCONNECTEMPTY */
i8255
u_rom_dsk_io
(
.i_clk (cpu_clk),
.i_addr (cpu_addr[1:0]),
.i_data (cpu_wdata),
.o_data (rom_rdata),
.i_rd_n (cpu_rd_n),
.i_wr_n (cpu_wr_n),
.i_cs_n (!w_sel_io_0a),
.i_reset (!reset_n),
.i_PA (rom_dsk_data),
.o_PA (),
.i_PB (),
.o_PB (rom_dsk_addr_lo[7:0]),
.i_PC (),
.o_PC (rom_dsk_addr_lo[15:8])
);
/* verilator lint_on PINCONNECTEMPTY */
assign rom_dsk_data = rom_dsk[{ rom_dsk_page[3:0], rom_dsk_addr_lo }];
assign cpu_rdata = w_sel_io_0a ? rom_rdata : 'z;
initial
begin
clk_div = '0;
$readmemh("./ROMs/ROM1-321.hex", rom_1);
$readmemh("./ROMs/ROM2-321.hex", rom_2);
$readmemh("./ROMs/romdisk1.hex", rom_dsk);
end
/* verilator lint_on UNUSEDSIGNAL */
endmodule

20
rtl/tb_top.sv Normal file
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`timescale 1ps/1ps
module tb_top
(
input wire i_clk,
input wire i_reset_n
);
orion_pro_top
#(
.TURBO_CLK_10 (1'b1)
)
u_orion_core
(
.i_clk (i_clk),
.i_reset_n (i_reset_n),
.i_cfg_sw (8'b0000_1111)
);
endmodule

1
sim_common Submodule

@ -0,0 +1 @@
Subproject commit edd2059a6a33544365fb2271bab6eaa225fcad72

2
sim_wrappers/CMakeLists.txt Normal file
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project(Vemulate)
cmake_minimum_required(VERSION 3.16)

218
sim_wrappers/sim_top.cpp Normal file
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#include "sim_top.h"
#include "tb.h"
#include CONCAT5(V,TOP_NAME,_,TOP_NAME,.h)
#include CONCAT5(V,TOP_NAME,_,orion_pro_top,.h)
double sc_time_stamp() { return 0; }
#define TICK_TIME 2
#define TICK_PERIOD (TICK_TIME / 2)
#define SIM_TIME_MAX (1000*10)
#define SIM_TIME_MAX_TICK (TICK_TIME * SIM_TIME_MAX)
#define RGB(b,g,r) (((r) << 16) | ((g) << 8) | (b))
static TB* obj_tb;
static int on_step_cb(uint64_t time, TOP_CLASS* p_top)
{
p_top->i_clk = !p_top->i_clk;
return 0;
}
SIM_TOP::SIM_TOP(int argc, const char** argv, thread_cb_t cb_to_draw, thread_cb_t cb_resize)
{
m_active = true;
m_cur_width = 0;
m_cb_start_draw = cb_to_draw;
m_cb_resize = cb_resize;
//this->p_gui = p_gui;
//this->p_kbd = p_kbd;
obj_tb = new TB(TOP_NAME_STR, argc, argv);
obj_tb->init(on_step_cb);
TOP_CLASS* top = obj_tb->get_top();
p_storage = (uint8_t*)top->TOP_NAME->u_orion_core->ram.m_storage;
p_video_mode = (video_mode_u*) &top->TOP_NAME->u_orion_core->video_mode;
p_screen_mode = (screen_mode_u*) &top->TOP_NAME->u_orion_core->screen_mode;
p_colors_pseudo = (colors_pseudo_u*)&top->TOP_NAME->u_orion_core->colors_pseudo;
p_kbd_input = (uint8_t*)&top->TOP_NAME->u_orion_core->kbd_input;
p_kbd_output = (uint8_t*)&top->TOP_NAME->u_orion_core->kbd_output;
p_thr = new std::thread(&SIM_TOP::thread_main, this);
//p_thr->join();
}
void SIM_TOP::thread_main()
{
TOP_CLASS* top = obj_tb->get_top();
// wait for reset
top->i_reset_n = 0;
obj_tb->run_steps(20 * TICK_TIME);
top->i_reset_n = 1;
const uint32_t tick_speed = (10 * 1000 * 1000); // 10MHZ
const uint32_t screen_period = tick_speed / 50;
//float sim_time;
uint32_t screen_cycle = 0;
uint32_t sec_cycle = 0;
time_t time_prev = time(0);
while (m_active)
{
obj_tb->run_steps(2);
//sim_time = (cycle * 1.f) / cycle_len;
//p_instance->p_gui->draw(sim_time);
if (++screen_cycle == screen_period)
{
screen_proc();
m_cb_start_draw();
screen_cycle = 0;
}
if (++sec_cycle == tick_speed)
{
time_t time_new = time(0);
time_t delta = time_new - time_prev;
time_prev = time_new;
printf("Sim time for 1 second: %ld\n", delta);
sec_cycle = 0;
}
}
obj_tb->finish();
top->final();
}
void SIM_TOP::screen_proc()
{
int width;
width = (p_screen_mode->wide_scr) ? 512 : 384;
if (m_cur_width != width)
{
printf("Set width %d->%d\n", m_cur_width, width);
m_cur_width = width;
m_cb_resize();
}
for (int i=0 ; i<SCREEN_HEIGHT*m_cur_width ; ++i)
{
p_screen[i] = 0;
}
if ((p_video_mode->mode == 2) || (p_video_mode->mode == 3))
{
return;
}
int scr_no = (p_video_mode->mode > 15) ? (p_screen_mode->scr_no | 1) : p_screen_mode->scr_no;
uintptr_t scr_start_addr;
switch (scr_no)
{
case 0: scr_start_addr = 0x0c000;
break;
case 1: scr_start_addr = 0x08000;
break;
case 2: scr_start_addr = 0x04000;
break;
case 3: scr_start_addr = 0x00000;
break;
}
uintptr_t scr_plane_0, scr_plane_1, scr_plane_2, scr_plane_3;
scr_plane_0 = scr_start_addr;
scr_plane_1 = scr_start_addr + 0x04000;
scr_plane_2 = scr_start_addr + 0x10000;
scr_plane_3 = scr_start_addr + 0x14000;
uint32_t c0, c1, c2, c3;
switch (p_video_mode->mode)
{
case 0: c0 = RGB(0x00, 0x00, 0x00); c1 = RGB(0x00, 0xff, 0x00);
break;
case 1: c0 = RGB(0xc8, 0xb4, 0x28); c1 = RGB(0x32, 0xfa, 0xfa);
break;
case 4: c0 = RGB(0x00, 0x00, 0x00); c1 = RGB(0x00, 0x00, 0xc0); c2 = RGB(0x00, 0xc0, 0x00); c3 = RGB(0xc0, 0x00, 0x00);
break;
case 5: c0 = RGB(0xc0, 0xc0, 0xc0); c1 = RGB(0x00, 0x00, 0xc0); c2 = RGB(0x00, 0xc0, 0x00); c3 = RGB(0xc0, 0x00, 0x00);
break;
}
uint32_t cur_pxl;
for (int x=0 ; x<m_cur_width ; x+=8)
{
for (int y=0 ; y<SCREEN_HEIGHT ; ++y)
{
uint8_t pixels0 = p_storage[(scr_plane_0 + ((x >> 3) << 8)) | y];
uint8_t pixels1 = p_storage[(scr_plane_1 + ((x >> 3) << 8)) | y];
uint8_t pixels2 = p_storage[(scr_plane_2 + ((x >> 3) << 8)) | y];
uint8_t pixels3 = p_storage[(scr_plane_3 + ((x >> 3) << 8)) | y];
if ((p_video_mode->mode == 14) || (p_video_mode->mode == 15))
{
pixels2 = p_colors_pseudo->bt;
}
if ((p_video_mode->mode == 6) || (p_video_mode->mode == 7) ||
(p_video_mode->mode == 14) || (p_video_mode->mode == 15))
{
uint32_t ci, cr, cg, cb;
ci = (pixels2 & (1 << 7)) >> 1;
cr = (pixels2 & (1 << 6)) ? (ci | 0xbf) : 0x00;
cg = (pixels2 & (1 << 5)) ? (ci | 0xbf) : 0x00;
cb = (pixels2 & (1 << 4)) ? (ci | 0xbf) : 0x00;
c0 = RGB(cb, cg, cr);
ci = (pixels2 & (1 << 3)) << 3;
cr = (pixels2 & (1 << 2)) ? (ci | 0xbf) : 0x00;
cg = (pixels2 & (1 << 1)) ? (ci | 0xbf) : 0x00;
cb = (pixels2 & (1 << 0)) ? (ci | 0xbf) : 0x00;
c1 = RGB(cb, cg, cr);
}
for (int i=0 ; i<8 ; ++i)
{
uint8_t pxl0 = (pixels0 & 0x80);
uint8_t pxl1 = (pixels1 & 0x80);
uint8_t pxl2 = (pixels2 & 0x80);
uint8_t pxl3 = (pixels3 & 0x80);
switch (p_video_mode->mode)
{
case 0:
case 1:
case 6:
case 7:
case 14:
case 15:
cur_pxl = (pxl0) ? c1 : c0;
break;
case 4:
case 5:
switch ((pxl0 << 1) | pxl2)
{
case 0: cur_pxl = c0;
break;
case 1: cur_pxl = c1;
break;
case 2: cur_pxl = c2;
break;
default:cur_pxl = c3;
break;
}
break;
}
switch (p_video_mode->mode & 0x14)
{
case 0x10:
c0 = 0;
if (pxl0) { c0 |= RGB(0x00, 0x00, 0xbf); }
if (pxl1) { c0 |= RGB(0x00, 0xbf, 0x00); }
if (pxl2) { c0 |= RGB(0xbf, 0x00, 0x00); }
cur_pxl = c0;
break;
case 0x14:
c0 = 0;
if (pxl0) { c0 |= RGB(0x00, 0x00, 0xbf); }
if (pxl1) { c0 |= RGB(0x00, 0xbf, 0x00); }
if (pxl2) { c0 |= RGB(0xbf, 0x00, 0x00); }
if (pxl3) { c0 |= RGB(0x40, 0x40, 0x40); }
cur_pxl = c0;
break;
}
//[x+i, y] = cur_pxl
p_screen[x + i + (y * m_cur_width)] = cur_pxl;
pixels0 <<= 1;
pixels1 <<= 1;
pixels2 <<= 1;
pixels3 <<= 1;
}
}
}
}

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#pragma once
#include <thread>
#include <functional>
typedef union
{
struct
{
uint8_t mode: 5;
};
uint8_t bt;
} video_mode_u;
typedef union
{
struct
{
uint8_t scr_no: 2;
uint8_t : 4;
uint8_t ram_reg_off: 1;
uint8_t wide_scr: 1;
};
uint8_t bt;
} screen_mode_u;
typedef union
{
struct
{
uint8_t pen : 4;
uint8_t back: 4;
};
uint8_t bt;
} colors_pseudo_u;
#define SCREEN_HEIGHT 256
#define SCREEN_WIDTH_NORMAL 384
#define SCREEN_WIDTH_WIDE 512
typedef std::function<void()> thread_cb_t;
class SIM_TOP
{
public:
SIM_TOP(int argc, const char** argv, thread_cb_t cb_to_draw, thread_cb_t cb_resize);
int get_width() { return m_cur_width; }
int get_height() { return SCREEN_HEIGHT; }
uint32_t* get_screen() { return p_screen; }
void stop() { m_active = false; }
private:
std::thread* p_thr;
bool m_active;
int m_cur_width;
uint32_t p_screen[SCREEN_HEIGHT*SCREEN_WIDTH_WIDE];
uint8_t* p_storage;
video_mode_u* p_video_mode;
screen_mode_u* p_screen_mode;
colors_pseudo_u*p_colors_pseudo;
uint8_t* p_kbd_input;
uint8_t* p_kbd_output;
thread_cb_t m_cb_start_draw;
thread_cb_t m_cb_resize;
void thread_main();
void screen_proc();
};

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80 3E 30 28 02 3E 31 CD 37 FC 78 FE 05 20 05 3E
5F CD 37 FC 79 07 10 E6 C9 4D ED 59 C9 7D E6 03
6F 4F 3E 01 2C 2D 28 03 07 18 FA 6F 7B FE FF 20
08 7D 2F 6F DB 0A A5 18 1B 0C 0D 20 04 D3 04 18
10 0D 20 04 D3 05 18 09 0D 20 04 D3 06 18 02 D3
09 DB 0A B5 D3 0A C9 CD B7 03 1E FF 0E 04 06 08
7B C6 04 F5 CD AF 03 F1 10 F7 CD B7 03 1D 0D 20
ED CD B7 03 3E 30 CD 37 FC 3E 33 CD 37 FC CD B2
03 DB 09 CD E1 05 2E 02 CD AE 03 DB 06 CD E1 05
2D CD AE 03 DB 05 CD E1 05 2D CD AE 03 DB 04 CD
E1 05 3E 44 CD 37 FC 3E 50 CD 37 FC CD B2 03 DB
0A CD 22 05 C3 B7 03 71 CD C1 03 C8 23 18 F8 3E
80 21 BB FF AE 77 D3 FA C9 CD C1 03 C8 0A BE 20
04 23 03 18 F4 CD B7 03 CD AA 03 CD B2 03 CD 8F
03 CD B2 03 0A CD 90 03 CD 84 12 FE 1B C8 3C 20
F7 18 DE 7E 02 7C BA 20 03 7D BB C8 23 03 18 F3
DB 0A F6 20 D3 0A C9 DB 0A E6 DF D3 0A C9 DD 7D
B7 20 1E F3 21 40 00 11 50 FF 01 3D 00 ED B0 21
7D 00 3E F7 ED 47 57 1E 00 01 10 00 ED B0 ED 5E
C9 3D 20 10 AF D3 04 D3 05 D3 06 D3 09 DB 0A E6
F0 D3 0A C9 3D 20 06 DD 21 03 20 18 06 3D C0 DD
21 06 20 FD E5 DB 09 FD 6F 3E 01 D3 09 DB 0A CB
DF D3 0A CD 9F 06 F5 FD 7D D3 09 F1 FD E1 C9 DD
E9 CD 15 10 20 FB CD 84 12 38 FB F5 CD 72 FC CD
15 10 20 FB F1 FE 03 37 C8 FE 1B 37 C8 B7 C9 0E
1F CD 09 F8 01 00 00 59 51 CD FB 06 3E 0D 0E FF
11 7F 01 CD 2A F8 0E 02 11 03 00 D5 CD FB 06 3E
0D 01 FD 00 11 7C 01 CD 2A F8 D1 01 1B 00 CD FB
06 11 7C 01 3E 07 2E 01 C3 2A F8 3E 05 C3 2A F8
01 32 B4 11 14 00 21 54 01 CD 19 07 3E 12 CD 0C
F8 01 00 00 59 51 21 80 01 3E 10 C3 0C F8 E5 CA
00 E5 C9 00 E5 C4 00 E5 C5 00 C5 E5 DD 6E 01 DD
66 02 DD 5E 03 DD 56 04 0C 0D 28 0A EB 46 23 04
10 FB EB 24 18 F3 F5 CD 3C F8 F1 B7 21 1E 07 C4
90 FC EB CD 90 FC 21 21 07 CD 90 FC E1 C1 C9 DD
46 00 0E 00 AF CD 2A 07 0C 10 F9 4E 3E FF CD 2A
07 E5 21 27 07 CD 90 FC CD A3 10 F5 21 24 07 CD
90 FC AF CD 2A 07 F1 E1 FE 1B 37 C8 FE 03 37 C8
FE 0D 20 16 7E 87 5F 16 00 DD 6E 05 DD 66 06 19
7E 23 66 6F CD A9 07 B7 C9 E9 11 6B 07 D5 FE 19
20 08 35 F0 DD 7E 00 3D 77 C9 FE 1A C0 34 DD 7E
00 BE C0 36 00 C9 CD BF 06 21 38 0E CD 90 FC 01
63 00 11 7E 00 CD FB 06 3E 0D 01 A9 00 11 07 01
CD 2A F8 DD 21 A0 0D 21 FD FF CD 5F 07 30 D7 C9
CD 00 07 0E 4F 06 6E 11 72 00 21 9E 00 CD 19 07
01 00 00 59 51 CD FB 06 3E 0D 01 6D 00 11 9D 00
D5 CD 2A F8 01 14 00 58 50 CD FB 06 D1 CD F4 06
01 54 68 11 85 00 21 80 00 CD 19 07 21 E1 08 CD
90 FC CD 3B 08 CD A1 06 C3 11 07 DB 00 0E FF CD
BD 08 CB 47 06 00 28 01 04 CD AB 08 CD BD 08 CB
4F 06 00 28 01 04 CD AB 08 CD BD 08 CB 57 06 03
28 01 05 CD AB 08 CD BD 08 CB 5F C5 0E 32 28 01
0D F5 CD B2 03 F1 CD 09 F8 C1 CD BD 08 CB 67 06
00 28 01 04 CD AB 08 CD BD 08 CB 6F 06 00 28 01
04 CD AB 08 CD BD 08 CB 77 06 04 28 01 04 CD AB
08 CD BD 08 CB 7F 06 07 28 01 05 F5 CD B2 03 F1
C5 F5 21 F4 08 78 87 87 80 06 05 18 13 F5 CD B7
03 F1 0C C5 F5 06 0E 21 1C 09 79 5F 87 87 87 87
5F 16 00 19 7E ED 44 4F CD 09 F8 23 10 F6 F1 C1
C9 E0 E0 E0 BD B1 B2 BA B7 B9 AB AE BF AC B7 B1
B2 F3 F6 00 A7 9B 8D E0 E0 B2 91 E0 E0 E0 B0 B5
D3 C8 CA B3 C9 D0 D0 C9 AE B1 B3 D3 CE AE B1 B3
D3 BC B1 AE BC B1 AD BD B0 B3 C8 D0 CF E0 BA 94
91 90 90 87 E0 9C 8E 97 8A 9B E0 D3 CE E0 B8 9F
8E 9C E0 9C 8E 97 8A 9B E0 E0 E0 D3 CD E0 B5 9B
87 9E 91 9F 8E 9C E0 E0 E0 E0 E0 D3 CC E0 B0 9F
99 9B E0 BD B0 D1 B3 D3 C8 D0 E0 D3 CB E0 BB 88
8C D2 9C 97 8D 90 94 9F 87 E0 E0 D3 CA E0 AD 8C
9F 8E 8C D3 B3 9B 92 8B E0 E0 E0 D3 C9 E0 B4 91
9F 9C E0 B1 AE BC B1 AD E0 E0 E0 D3 C8 E0 AD 87
8D 8C 9B 93 E0 E0 E0 E0 E0 E0 E0 D3 CD 00 07 01
37 00 11 46 00 D5 CD FB 06 01 D7 00 11 3E 01 3E
0D CD 2A F8 01 4B 00 CD FB 06 D1 CD F4 06 01 C3
00 CD FB 06 11 3E 01 CD F4 06 21 F3 0B CD 90 FC
01 00 10 11 9B 0B 26 08 79 FE 08 38 04 26 0E D6
08 87 87 C6 11 6F CD 3C F8 3E 44 CD 37 FC 1A CD
15 F8 13 0C 10 E0 DD 21 AB 0B DD 6E 00 DD 66 01
DD 23 DD 23 7D B4 28 1D 11 CD 0B 0E 20 1A B7 28
E9 47 13 1A 77 2C 0D 20 07 0E 20 24 7D 91 6F 1A
10 F2 13 18 E8 21 C9 D0 0E 11 06 08 36 00 78 FE
04 20 02 36 AA 2C 10 F4 2E C9 24 0D 20 EC DB 0A
CB CF D3 0A FD 26 00 FD 2E 00 FD 7D FE 20 30 5D
D3 05 FE 03 28 12 FE 1F 28 0E 21 00 40 11 01 40
FD 7C 77 01 FF 3F ED B0 21 C9 D0 7E E6 01 28 03
24 18 F8 FD 7D E6 07 3C 47 3E 01 0F 10 FD 4F 06
08 7E B1 77 2C 10 FA DB 00 E6 04 28 12 AF D3 18
DB 19 EE FF 28 13 CD 72 FC CD A1 06 30 0B C9 AF
D3 1A D3 19 DB 18 3C 20 ED FD 2C 18 9D FD 2E 00
FD 7D FE 20 D2 73 0B D3 05 FE 03 CA 2D 0B FE 1F
CA 2D 0B 21 00 40 44 4D FD 5C 7E AB CA 26 0B D9
4F 1E 00 06 08 DB 05 CB 57 28 02 1E 10 CB 09 30
3E 21 AB 0B 16 00 19 7E 23 66 6F 2C 7E 2D E6 7F
20 2D FD 6B DD 69 DD 60 11 E0 0B 0E 20 1A B7 28
14 47 13 1A 77 2C 0D 20 07 0E 20 24 7D 91 6F 1A
10 F2 13 18 E8 FD 5D DD 4D DD 44 DB 05 FD 6F 1C
1C 05 C2 DD 0A D9 23 0B 78 B1 C2 CA 0A 21 C9 D0
7E E6 01 28 03 24 18 F8 FD 7D E6 07 3C 47 3E 01
0F 10 FD 4F 06 08 7E B1 77 2C 10 FA DB 00 E6 04
28 12 AF D3 18 DB 19 EE FF 28 13 CD 72 FC CD A1
06 30 0B C9 AF D3 1A D3 19 DB 18 3C 20 ED FD 2C
C3 B0 0A FD 7C 2F FD 67 B7 C2 47 0A 21 C9 E0 06
08 3E FC 77 2C 10 FC 21 00 F0 2B 7C B5 20 FB AF
D3 05 DB 0A CB 8F D3 0A C3 25 0A 70 60 61 59 73
65 62 64 52 71 54 57 63 74 72 53 9A D3 5E D3 9A
D0 5E D0 9A D6 5E D6 5E CD 9A CD 9A E2 5E E2 5E
DC 9A DC 9A D9 5E D9 5E DF 9A DF 00 00 01 FF 1A
80 01 83 03 84 02 FF 1A 01 01 C1 03 21 01 FF 00
1B FF 01 FC 02 FB 01 F8 1C FF 01 3F 02 DF 01 1F
01 FF 00 E5 A7 DA C4 AE BF B3 E0 AC BB AD AC 00
CD 00 07 01 73 00 11 74 00 D5 CD FB 06 3E 0D 01
A2 00 11 11 01 CD 2A F8 01 87 00 CD FB 06 D1 CD
F4 06 21 64 0C CD 90 FC CD 22 0D E5 CD 15 F8 CD
FE 0C D1 21 21 0E E5 CD 3C F8 78 CD 15 F8 79 CD
15 F8 E1 24 CD 3C F8 7A CD 15 F8 7B CD 15 F8 01
00 10 CD 12 F8 28 06 CD 72 FC C3 A1 06 0B 78 B1
20 F0 18 BE E5 A7 D4 C3 AE B1 B3 E0 AC BB AD AC
E5 A7 D2 C9 AE B1 B3 CF E0 BD AD C6 E0 E0 E0 E0
E0 E0 E0 D8 E0 C8 B5 D7 E5 A7 D1 C9 AE B1 B3 CE
E0 BD AD C6 E0 E0 E0 E0 E0 E0 E0 D8 E0 E0 B5 D7
F8 F8 F8 F8 00 3E 02 D3 F8 11 EE 0C 21 00 C0 06
03 36 FF 1A 4F 3E 01 CD 39 F8 2C 20 F4 24 7C FE
F0 28 05 10 EC 13 18 E7 01 00 10 79 07 07 07 07
B1 D3 E0 D3 E1 D3 E2 0C 10 F1 3E 06 D3 F8 CD A1
06 38 06 CD 18 01 CD A1 06 3E 0F D3 F8 C9 00 08
01 09 04 0C 05 0D 02 0A 03 0B 06 0E 07 0F 21 00
00 11 FF 1F EB E5 7D 21 00 00 18 06 EB 46 48 23
EB 09 BB 20 F7 C1 C5 78 BA 79 20 F0 1A 85 4F 44
E1 C9 21 08 20 0E 04 CD 8D 00 06 08 3E 64 20 04
06 04 3E 32 F5 11 00 40 AF 12 4F 6F 67 DB 0A F5
CB DF D3 0A 78 3D 20 01 1B 79 D3 09 C5 D5 E5 21
00 20 CD 04 0D E1 09 D1 C1 0C 10 E8 F1 D3 0A F1
C9 04 1B 0B 68 0D 98 0D E0 E0 B3 91 92 97 8C 91
8E E0 E0 00 E0 B1 8E 97 91 92 D3 B0 AE B1 E0 00
E0 B1 8E 97 91 92 D3 CF CE C8 E0 00 E0 E0 AC E0
BB E0 AD E0 AC E0 E0 00 67 02 C5 01 D0 01 C6 07
05 19 0B A7 0D F7 0D E0 BD 91 92 9A 97 99 8B 8E
9F 8C 97 91 92 E0 00 E0 AE BF B3 E0 D3 E0 AC E0
9B E0 8D E0 8C E0 00 E0 AE B1 B3 E0 D3 E0 AC E0
9B E0 8D E0 8C E0 00 E0 AC AA E0 E0 D3 E0 AC E0
9B E0 8D E0 8C E0 00 E0 E0 E0 B3 9F 97 92 E0 B3
9B 92 8B E0 E0 E0 00 F0 07 9C 09 00 0C A5 0C 36
02 E5 A7 DF DE D8 BD D7 E0 CF C7 C7 CD D3 CE D0
D0 D0 E0 B1 8E 97 91 92 8D 91 9A 8C E0 BD 91 D2
D4 B4 8C 9C E5 A7 DF B1 B1 8E 97 91 92 D3 B0 8E
91 E0 AA CD D2 CF D0 00 E5 A7 DF CB D6 E0 AC BB
AD AC E0 B1 AE B7 B1 B2 D3 B0 AE B1 E0 D6 00 E1
E5 A7 DF DE D8 BD D7 E0 CF C7 C7 CD D3 CF C7 C7
C9 E0 B1 8E 97 91 92 8D 91 9A 8C E0 BD 91 D2 E5
A7 DF B1 B1 8E 97 91 92 D3 B0 8E 91 E0 AA CD D2
CF D0 F3 F6 00 E1 F6 F6 E0 AD 87 8D 8C 9B 93 E0
B3 B1 B2 B7 AC B1 AE E0 E0 AA CE D2 CF D0 F3 F6
00 F3 F6 E0 D3 E0 B3 E0 BC E0 BA E0 AC E0 BD E0
D3 E0 B7 E0 B1 E0 AA E0 A9 E0 A8 E0 CE E0 C8 E0
D3 E0 B9 E0 D3 F3 F6 00 F3 F6 F6 C3 C2 F9 00 DD
7D D6 13 D2 F0 0F C6 13 20 0C E5 2A 69 FF AF 77
E1 ED 53 66 FF C9 3D 20 16 2A 69 FF 7E 5F B7 16
00 E5 19 0E FF 28 01 4E E1 23 ED 5B 66 FF C9 3D
20 08 22 6E FF ED 53 6B FF C9 3D 20 08 2A 6E FF
ED 5B 6B FF C9 3D 20 09 ED 43 74 FF ED 53 76 FF
C9 3D 20 09 ED 4B 74 FF ED 5B 76 FF C9 3D 20 09
ED 43 78 FF ED 53 7A FF C9 3D 20 09 ED 4B 78 FF
ED 5B 7A FF C9 3D 20 09 ED 43 7C FF ED 53 7E FF
C9 3D 20 09 ED 4B 7C FF ED 5B 7E FF C9 3D 20 08
22 84 FF 79 32 86 FF C9 3D 20 08 2A 84 FF 3A 86
FF 4F C9 3D 20 08 22 87 FF 79 32 89 FF C9 3D 20
08 2A 87 FF 3A 89 FF 4F C9 3D 20 08 22 8A FF 79
32 8C FF C9 3D 20 08 2A 8A FF 3A 8C FF 4F C9 3D
20 29 D5 E5 2A 82 FF 11 A6 FF 71 CD C5 0F 23 38
03 21 97 FF ED 5B 80 FF CD C5 0F 37 28 04 22 82
FF B7 E1 D1 C9 E5 B7 ED 52 E1 C9 3D 20 19 D5 E5
CD FA 0F 38 ED 4E 11 A6 FF CD C5 0F 23 38 03 21
97 FF 22 80 FF 18 DA E5 2A 82 FF 22 80 FF E1 C9
20 16 D5 E5 CD FA 0F E1 D1 C9 2A 80 FF ED 5B 82
FF CD C5 0F 37 C8 B7 C9 3D 20 04 22 72 FF C9 3D
C0 2A 72 FF C9 DB 00 E6 04 28 0B AF D3 18 DB 19
EE FF C8 3E FF C9 AF D3 1A D3 19 DB 18 3C C8 3E
FF D3 1A 3E FC D3 19 00 DB 18 E6 E3 FE E3 20 11
3E 03 D3 19 00 DB 18 3C 20 07 D3 1A 00 DB 18 3C
C8 3E FF C9 CD 84 12 CB 69 C8 CB 61 C8 1B 1C 1D
C0 14 15 C0 ED 5B 6B FF CB 79 28 15 CB B9 C5 D5
E5 F5 3E 06 CD 0F F8 3E 03 CD 0F F8 F1 E1 D1 C1
C9 CB F9 C5 D5 E5 F5 3E 06 CD 0F F8 3E 02 18 E9
3A 66 FF E6 03 FE 02 C9 DB 00 E6 04 C0 3A 66 FF
CB 7F C9 C5 D5 E5 3E F1 CD CE 0F 79 30 2D CD 39
11 F5 CD E9 0E FE 03 30 21 46 7A E6 03 FE 03 28
19 5F 87 83 5F 16 00 21 84 FF 19 79 FE 04 28 04
FE 0A 20 01 78 CD DF 10 30 CD F1 E1 D1 C1 C9 0E
0A ED 40 C5 CB C8 ED 41 CB 39 ED 40 C5 5E 23 56
23 ED A3 EB CB BC CB F4 E5 CD 0A 11 E1 D4 1D 11
D4 29 11 C1 ED 41 C1 ED 41 C9 06 00 4E 37 0C 0D
C8 23 C5 ED B1 79 C1 37 C0 91 2F B7 C9 4E 23 09
3C 3D B7 C8 4E 23 09 18 F8 46 37 04 05 C8 23 4E
CD A2 0F 38 02 10 F7 B7 C9 3E 0F CD 0F F8 CB B9
CB 69 C4 81 10 ED 5B 6B FF 18 0D F1 2A 6E FF 18
04 F1 21 01 00 22 70 FF CD 54 10 47 30 07 C5 CD
A1 11 C1 18 ED CD 19 12 30 E8 2A 70 FF E5 AF 3D
20 FD CD 54 10 38 DA B8 20 D1 2B 7C B5 20 EF E1
2B 7C B5 2A 6E FF 28 03 21 02 00 22 70 FF CB 79
C4 6C 10 78 32 68 FF ED 5B 66 FF F5 CD 60 F8 F1
C9 21 67 FF 4E CD 98 10 78 28 55 FE FE 20 2B CD
90 10 28 06 30 44 CB 7E 20 12 7E EE 40 77 C5 D5
E5 79 ED 5B 66 FF CD 63 F8 E1 D1 C1 CD 84 12 30
FB 3C 20 F8 7E E6 1F 20 F3 C9 FE 0F 20 04 CB BE
18 DC FE 0E 20 09 CD 90 10 30 E1 CB FE 18 CF CB
4E C8 CB 46 C8 CD 90 10 28 C0 7E EE 20 77 18 BE
CB 56 C8 CB 4E 20 EE CB 5E 20 A4 CB 66 C8 CD 90
10 30 B9 7E EE 80 77 18 A5 CD 98 10 37 C8 CD 90
10 3F D8 21 73 FF 7E 2B BE 20 0C B8 37 C0 21 67
FF CB 7E 28 B1 18 A7 7E B8 23 7E 21 67 FF 28 9E
B8 28 A3 37 C9 DB 00 E6 04 28 13 AF D3 18 DB 19
B7 20 15 DB 1A F6 1F 3C 20 0E F6 FF 37 C9 AF D3
19 D3 1A DB 18 3C 28 F2 CD 84 12 E5 C5 D5 47 30
09 CD A1 11 F6 FF 37 C3 C3 12 CD 19 12 30 F5 78
B7 C3 C3 12 E5 C5 D5 CD 46 16 A7 28 2A FE 04 30
26 21 67 FF 57 1E 00 7E E6 1F 28 49 06 05 0F 30
01 1C 10 FA 7A BB 20 1F 3D 20 0C CB 56 20 0B CB
66 20 0A CB 5E 20 09 3E FF 21 3E FE 21 3E 0E 21
3E 0F 37 D1 C1 E1 C9 79 FE 0D 30 15 7A FE 02 20
E6 79 FE 0A 30 04 FE 04 20 07 E5 2A 69 FF 23 4E
E1 CB 56 20 D2 51 79 21 A2 13 01 04 00 ED B1 20
1B 3E 03 91 4F 21 74 FF 09 3A 67 FF E6 03 87 87
4F 7B FE 02 38 02 0E 00 09 7E 18 B7 4A 21 B6 13
11 0E 14 CD 90 10 3A 67 FF 38 10 EB 20 32 CB 5F
28 02 EE 40 CB 77 20 2D EB 18 2A CB 47 20 26 21
16 15 11 50 FF CB 67 28 02 EE 80 CB 7F 20 0C 19
CB 5F 28 02 EE 40 CB 77 20 01 19 EB 21 58 00 19
CB 6F 28 01 EB CB 4F 28 19 EB 09 DB 00 E6 04 20
18 79 E5 21 A6 13 0E 10 ED B1 E1 20 0C 7E EE 10
18 08 09 DB 00 E6 04 20 E8 7E 4F CD 90 10 3D 20
0B 21 C6 15 79 D6 80 38 03 4F 09 4E 21 C3 12 E5
3A 67 FF B7 CB 47 79 C8 FE 40 3F D0 FE 7F D0 E6
1F C9 4C 35 3E 3D 19 21 29 30 39 41 48 50 57 4F
47 46 10 37 54 45 39 38 00 00 00 34 35 36 1B 09
00 0E 0F 2B 2D 0D 2B 4A 46 51 00 30 2E 2C 00 21
43 59 5E 31 32 33 01 22 55 57 53 37 0C 1F 02 23
4B 41 4D 7F 1E 0A 24 45 50 49 20 18 0D 3F 03 25
4E 52 54 1A 19 5F 04 26 47 4F 58 3E 2A 3D 27 5B
4C 42 08 5C 48 20 28 5D 44 40 3C 56 5A 29 39 38
00 00 00 34 35 36 1B 09 00 0E 0F 2B 2D 0D 2B 6A
66 71 00 30 2E 2C 00 21 63 79 7E 31 32 33 01 22
75 77 73 37 0C 1F 02 23 6B 61 6D 7F 1E 0A 24 65
70 69 20 18 0D 3F 03 25 6E 72 74 1A 19 5F 04 26
67 6F 78 3E 2A 3D 27 7B 6C 62 08 7C 68 20 28 7D
64 60 3C 76 7A 29 39 38 00 00 00 34 35 36 1B 09
00 0E 0F 2B 2D 0D 2B 89 94 9F 00 30 2E 2C 00 21
96 9B 97 31 32 33 01 22 93 82 91 37 0C 1F 02 23
8A 80 8C 7F 1E 0A 24 85 8F 88 20 18 0D 3F 03 25
8D 90 92 1A 19 9A 04 26 83 8E 9C 3E 2A 3D 27 98
8B 81 08 9D 95 20 28 99 84 9E 3C 86 87 29 39 38
00 00 00 34 35 36 1B 09 00 0E 0F 2B 2D 0D 2B A9
E4 EF 00 30 2E 2C 00 21 E6 EB E7 31 32 33 01 22
E3 A2 E1 37 0C 1F 02 23 AA A0 AC 7F 1E 0A 24 A5
AF A8 20 18 0D 3F 03 25 AD E0 E2 1A 19 EA 04 26
A3 AE EC 3E 2A 3D 27 E8 AB A1 08 ED E5 20 28 E9
A4 EE 3C A6 A7 29 39 38 00 00 00 34 35 36 1B 09
00 0E 0F 2B 2D 0D 2B C9 CC C8 00 30 2E 2C 00 21
CB CE CA 31 32 33 01 22 BB B9 BC 37 0C 1F 02 23
D6 C7 D3 7F 1E 0A 24 D2 D7 D0 20 18 0D 3F 03 25
B7 B6 BD 1A 19 F0 04 26 B0 DD B2 3E 2A 3D 27 DF
FE DC 08 BA CD 20 28 B1 DE DB 3C FD FB 29 39 38
00 00 00 34 35 36 1B 09 00 0E 0F 2B 2D 0D 2B DA
C3 C0 00 30 2E 2C 00 21 C2 C5 C1 31 32 33 01 22
BF B4 D9 37 0C 1F 02 23 D5 C6 D4 7F 1E 0A 24 D1
D8 CF 20 18 0D 3F 03 25 B8 B5 BE 1A 19 F1 04 26
F5 F7 F2 3E 2A 3D 27 F8 FF F9 08 B3 C4 20 28 F4
F6 F3 3C FC FA 29 E1 E2 F7 E7 E4 E5 F6 FA E9 EA
EB EC ED EE EF F0 F2 F3 F4 F5 E6 E8 E3 FE FB FD
FF F9 F8 FC E0 F1 C1 C2 D7 C7 C4 C5 D6 DA C9 CA
CB CC CD CE CF D0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
BA BB BC BD BE BF 80 81 82 83 84 85 86 87 88 89
8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99
9A 9B 9C 9D 9E 9F D2 D3 D4 D5 C6 C8 C3 DE DB DD
DF D9 D8 DC C0 D1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
AA AB AC AD AE AF 21 67 FF 3E E0 A6 77 AF 2A 69
FF 77 23 EB 21 FE FF DB 00 E6 04 20 73 0E 00 7D
D3 19 7C D3 1A DB 18 FE FF 28 49 47 3A 6D FF 3D
20 FD DB 18 B8 20 3D 06 09 0D 0C 05 28 3A 0F 38
F9 EB 71 23 F6 80 77 EB E5 F5 21 67 FF 79 FE 04
20 02 CB CE FE 0A 20 02 CB C6 FE 14 20 02 CB D6
FE 0B 20 02 CB E6 FE 0C 20 02 CB DE 2A 69 FF 34
F1 E1 18 C6 79 C6 08 4F CB 35 CB 14 7C FE F7 20
9E 2A 69 FF EB 1A A7 0E FF 28 02 2B 4E EB 23 C9
21 7F 09 0E 00 DB 1A F6 1F FE FF 28 51 18 15 7D
D3 18 DB 19 FE FF 28 46 47 3A 6D FF 3D 20 FD DB
19 B8 20 3A 06 09 0D 0C 05 28 37 0F 38 F9 EB F5
C5 E5 21 67 FF 79 FE 05 20 02 CB CE FE 06 20 02
CB C6 FE 07 20 02 CB D6 2A 69 FF 34 21 34 17 06
00 09 7E E1 77 C1 F1 23 F6 80 77 EB 18 C9 79 C6
08 4F CB 05 25 20 A8 18 88 04 0A 14 26 27 08 18
20 28 38 40 09 2F 36 2D 4C 3E 35 3D 4F 19 21 29
30 39 41 48 50 57 46 10 54 47 45 37 53 2B 4B 1A
52 31 12 42 4E 33 11 2A 4A 2C 3A 43 32 13 3B 24
3C 22 55 23 44 1B 56 49 4D 51 1C 34 DD 7D B7 C2
09 19 CD B4 18 2A 57 FF E5 26 00 22 AF FF 7D 25
ED 44 6F 22 B1 FF E1 6C 26 00 22 AB FF 7D 25 ED
44 6F 22 AD FF ED 4B A9 FF ED 5B A7 FF 3E 02 CD
0F F8 30 08 3E 03 CD 0F F8 37 18 63 CD 4E F8 CB
67 28 F9 CB 6F 28 F5 CD 15 10 20 FB CD 6E 18 30
FB ED 43 A9 FF ED 53 A7 FF 6F 3E 03 CD 0F F8 7D
E6 30 FE 30 20 2B 7D CB 47 CC 54 18 CB 4F CC 5A
18 CB 57 CC 60 18 CB 5F CC 67 18 3E 02 CD 0F F8
30 CA ED 4B A9 FF ED 5B A7 FF 3E 02 CD 0F F8 18
BB AF CB 65 20 02 CB FF CB 6D 20 02 CB F7 B7 F5
ED 4B BD FF ED 5B BF FF 2A C1 FF 3E 14 CD 0F F8
ED 4B B9 FF 2A BB FF 3E 12 CD 0F F8 ED 4B B3 FF
ED 5B B5 FF 2A B7 FF 3E 10 CD 0F F8 4C 3E 0E CD
0F F8 F1 C9 2A AD FF 19 EB C9 2A AB FF 19 EB C9
2A AF FF 09 44 4D C9 2A B1 FF 09 44 4D C9 CD 4E
F8 E6 3F FE 3F 37 C0 21 00 02 2B 7C B5 20 FB CD
27 F8 E6 F0 20 11 CD 84 12 2E 1F FE 0D 28 22 2E
2F FE 1B 28 1C AF C9 2E 3F CB 67 28 02 CB 85 CB
6F 28 02 CB 9D CB 77 28 02 CB 8D CB 7F 28 02 CB
95 7D 37 C9 3E 0F CD 0F F8 61 3E 11 CD 0F F8 ED
43 B3 FF ED 53 B5 FF 22 B7 FF 3E 13 CD 0F F8 ED
43 B9 FF 22 BB FF 3E 15 CD 0F F8 ED 43 BD FF ED
53 BF FF 22 C1 FF CD 14 19 3E 0E CD 0F F8 CD 2C
19 01 00 00 3E 10 CD 0F F8 CD 47 19 3E 12 CD 0F
F8 CD 61 19 3E 14 C3 0F F8 3D 20 05 79 32 50 FF
C9 3D 20 05 3A 50 FF 4F C9 3D 20 0D ED 53 54 FF
ED 43 57 FF 7D 32 56 FF C9 3D 20 0D ED 5B 54 FF
ED 4B 57 FF 3A 56 FF 6F C9 3D 20 08 22 51 FF 79
32 53 FF C9 3D 20 08 2A 51 FF 3A 53 FF 4F C9 3D
20 0C 22 5D FF ED 43 59 FF ED 53 5B FF C9 3D 20
0C 2A 5D FF ED 4B 59 FF ED 5B 5B FF C9 3D C0 C5
E5 CD B4 18 3E 16 CD 0F F8 D5 CD 1F 18 D1 E1 C1
C9 F7 9A 8E 91 93 E0 9A 94 91 90 90 87 E0 9C 97
8D 95 F3 F6 00 F7 E0 9A 8E 91 93 E0 98 9F 8E 9C
E0 9C 97 8D 95 F3 F6 00 B2 91 92 D3 8D 87 8D 8C
9B 93 E0 9C 97 8D 95 DF 00 BC 97 8D 95 E0 9E 91
91 8C E0 9A 9F 97 94 8B 8E 9B DF 00 F3 F6 F6 E0
BB AE AE B1 AE C6 E0 00 E0 A5 BF B0 CE D3 AF 8B
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30 F8 C7 C3 66 F8 C3 32 FB C3 37 FB C3 58 FA C3
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513
work_dir/ROMs/ROM1-320.hex Normal file
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@ -0,0 +1,513 @@
@00000000
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CD B2 03 0C 10 F6 CD B2 03 79 FE 10 20 EC 79 FE
20 28 09 CD 99 03 0C 18 F5 CD B2 03 E5 21 21 07
CD 90 FC E1 C9 E6 0F CD 36 F8 79 C9 CD B2 03 4D
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80 3E 30 28 02 3E 31 CD 37 FC 78 FE 05 20 05 3E
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03 DB 09 CD E1 05 2E 02 CD AE 03 DB 06 CD E1 05
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04 23 03 18 F4 CD B7 03 CD AA 03 CD B2 03 CD 8F
03 CD B2 03 0A CD 90 03 CD 84 12 FE 1B C8 3C 20
F7 18 DE 7E 02 7C BA 20 03 7D BB C8 23 03 18 F3
DB 0A F6 20 D3 0A C9 DB 0A E6 DF D3 0A C9 DD 7D
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CD 00 07 01 73 00 11 74 00 D5 CD FB 06 3E 0D 01
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B1 D3 E0 D3 E1 D3 E2 0C 10 F1 3E 06 D3 F8 CD A1
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01 09 04 0C 05 0D 02 0A 03 0B 06 0E 07 0F 21 00
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18 08 09 DB 00 E6 04 20 E8 7E 4F CD 90 10 3D 20
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3A 67 FF B7 CB 47 79 C8 FE 40 3F D0 FE 7F D0 E6
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18 CB 57 CC 60 18 CB 5F CC 67 18 3E 02 CD 0F F8
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2A AF FF 09 44 4D C9 2A B1 FF 09 44 4D C9 CD 4E
F8 E6 3F FE 3F 37 C0 21 00 02 2B 7C B5 20 FB CD
27 F8 E6 F0 20 11 CD 84 12 2E 1F FE 0D 28 22 2E
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32 53 FF C9 3D 20 08 2A 51 FF 3A 53 FF 4F C9 3D
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E5 CD B4 18 3E 16 CD 0F F8 D5 CD 1F 18 D1 E1 C1
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8D 95 F3 F6 00 F7 E0 9A 8E 91 93 E0 98 9F 8E 9C
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87 8D 8C 9B 93 F3 F6 00 CD 03 20 F1 4F 3E 01 CD
30 F8 C7 C3 66 F8 C3 32 FB C3 37 FB C3 58 FA C3
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FB C3 4C FA C3 25 FD C3 01 FC C3 A9 FC C3 4B FA
C3 4B FA C3 52 FD C3 6F FD C3 6B FA C3 5F FA C3
44 FA C3 3E FC C3 7A FA C3 93 FA C3 AC FA C3 D9
FA C3 F6 FB C3 43 FB C3 01 FA C3 0C FA C3 1C FB
C3 21 FD C3 72 FC C3 4B FA 31 C0 F7 DB 0A F6 18
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3E 08 CD E6 F9 06 0A C5 01 01 00 11 00 00 CD 3F
F8 C1 DB 10 CB 4F 28 05 10 ED C3 5D F9 11 00 00
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90 FC E1 CD 90 FC 21 D8 19 CD 90 FC CD 32 FB FE
03 28 05 FE 1B C2 66 F8 DB 0A F6 10 D3 0A C3 1C
02 21 81 19 CD 90 FC 3E 01 D3 12 21 00 B0 CD 01
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20 C3 1C 02 CD E1 F9 21 95 19 CD 90 FC 3E 02 D3
56 11 FF 06 1B 7A B3 CA D5 F8 06 FF E3 E3 E3 E3
E3 10 F9 DB 5F B7 FA 91 F9 DB 59 E6 7F FE 01 C2
D5 F8 21 00 B0 3E 21 D3 5F DB 5F CB 7F 20 FA CB
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77 23 18 F3 E5 CD EF F9 EB E1 DB 10 E6 DD C9 3E
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FB E1 D1 C1 F5 3E 10 CD 0C F8 F1 E1 F5 CD 3C F8
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FD E1 D1 C1 C9 F5 DB 08 32 6B FD F1 E6 0F D3 08
71 42 4B 54 5D 13 0B 79 B0 28 02 ED B0 3E 00 D3
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78 B1 20 E9 3E 00 D3 08 31 00 00 C9 FB ED 4D 00
FF FF FF FF FF FF FF FF FF 3E 80 D3 FB AF C9 FF

513
work_dir/ROMs/ROM1-321.hex Normal file
View File

@ -0,0 +1,513 @@
@00000000
C3 5B 01 C3 D0 00 C3 CF 0E C3 A3 10 C3 15 10 C3
45 12 C3 46 16 C3 3E 06 C3 7C 17 00 00 00 31 46
52 4F 4D 31 2D 42 49 4F 53 20 56 32 2E 31 30 20
28 43 29 20 22 4F 52 49 4F 4E 53 4F 46 54 22 20
03 5E FF 1F 08 05 00 02 02 1B 1C 1D 1E B0 80 C0
E0 F0 F8 F0 B0 30 00 00 00 8D FF 00 02 40 50 01
01 00 0F 0E 08 18 19 1A 08 18 19 1A 08 18 19 1A
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1B CD 43 06 21 43 1A 11 00 F8 01 BD 05 ED B0 C9
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21 0D F8 CD 10 01 21 10 F8 CD 10 01 21 2B F8 CD
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1A 77 13 23 1A 77 13 C9 21 2B 01 01 E0 10 ED B3
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56 D3 3B 3E 96 D3 3B 3E 80 D3 07 D3 0B 3E 50 D3
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36 00 2B 36 00 31 C0 F7 CD B5 00 CD 18 01 DB 00
CB 6F CA 1C 02 CD 46 16 A7 28 04 3D C2 1C 02 DB
00 CB 7F 20 14 3E 01 CD D5 00 CA EA 01 C3 00 F8
01 F4 01 11 00 00 CD 3F F8 DB 0A CB DF D3 0A AF
D3 09 2A 00 20 7D BC C2 00 20 CD FF 01 3E E0 D3
FC 3E 0F D3 F8 CD 0D 02 CD 0D 02 CD 0D 02 76 01
00 30 21 00 C0 11 01 C0 36 00 ED B0 C9 01 C8 00
11 00 04 CD 3F F8 11 00 00 C3 3F F8 31 C0 F7 AF
CD D5 00 CA EA 01 AF D3 08 D3 FA 3E 4F D3 FC 3E
0F D3 F8 CD 43 06 31 C0 F7 CD BF 06 21 01 0E CD
90 FC 3E 05 01 63 00 11 92 00 CD 2A F8 3E 0D 01
9F 00 11 F3 00 CD 2A F8 DD 21 61 0D 21 FE FF CD
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85 0E CD 90 FC CD C7 03 21 A1 0E CD 90 FC CD C7
03 31 C0 F7 21 C8 0E CD 90 FC 21 81 02 E5 CD E3
02 CD 2A 03 3A A7 FF B7 FA 85 03 FE 40 38 02 E6
DF FE 4D CA D4 03 FE 44 CA F1 03 FE 46 CA E7 05
FE 54 CA 23 06 FE 43 CA F9 05 FE 49 CA 1C 05 FE
4F CA 49 05 FE 56 CA EF 05 FE 57 CA 4D 05 FE 58
CA 87 05 FE 32 CA 30 06 FE 38 CA 37 06 FE 47 C2
85 03 E9 11 A7 FF 06 00 CD A3 10 FE 03 CA A5 01
FE 1B CA 67 02 FE 7F 28 04 FE 08 20 15 04 05 28
E7 1B 05 3E 08 CD 37 FC CD B2 03 3E 08 CD 37 FC
18 D6 FE 0D 28 04 FE 20 38 CE 12 04 FE 0D C8 CD
37 FC 13 3E 0F B8 30 C0 18 D7 11 A8 FF 21 00 00
22 B9 FF CD 4F 03 22 B7 FF D8 CD 4F 03 22 B9 FF
38 08 CD 4F 03 44 4D 2A B9 FF EB 2A B7 FF C9 21
00 00 45 4D 09 1A 13 FE 20 28 FA FE 0D 28 2E FE
2C C8 FE 40 38 02 E6 DF D6 30 FA 85 03 FE 0A FA
7E 03 FE 11 FA 85 03 FE 17 F2 85 03 D6 07 4F 29
29 29 29 30 CF 3E 3F CD 37 FC C3 81 02 37 C9 7E
F5 0F 0F 0F 0F CD 99 03 F1 E6 0F FE 0A FA A2 03
C6 07 C6 30 C3 37 FC CD B7 03 7C CD 90 03 7D CD
90 03 3E 20 C3 37 FC 3E 0D CD 37 FC 3E 0A C3 37
FC 7C BA C0 7D BB C9 01 C4 3E CD B2 03 CD 09 F8
10 FB C9 23 CD A7 03 CD 8F 03 CD B2 03 CD E3 02
11 A7 FF 1A FE 0D 28 EB E5 CD 4F 03 EB E1 73 18
E2 2A B7 FF 2E 00 06 FF CD C9 04 CD A7 03 CD B2
03 E5 06 02 3A B9 FF CD 15 05 CD 90 03 23 10 05
CD B2 03 06 02 7D E6 0F 20 EA E1 CD B2 03 3A B9
FF CD 15 05 FE 20 38 0C FE B0 38 0A FE E0 38 04
FE F2 38 02 3E 2E CD 37 FC 23 7D E6 0F 20 DF 7D
A7 20 B8 CD B7 03 CD B6 04 CD A3 10 FE 1B CA 67
02 FE 0C 28 9C FE 42 28 98 FE 62 28 94 FE 19 28
03 B7 20 04 25 25 18 8E FE 1A 28 8A FE 02 28 86
18 D7 E5 CA E0 E0 E0 E0 E0 E0 BB AD BD E0 D3 E0
AF 8B 97 8C E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0 E0
E0 E0 E0 E0 E0 E0 E0 E0 D8 BE D7 9B 99 97 92 E0
E0 E0 E0 B0 99 D3 08 E0 E0 E0 E0 B0 99 D3 07 E0
E0 E0 E0 E5 C9 00 E5 21 72 04 CD 90 FC E1 C9 E5
A7 D9 E0 E5 CA E0 B0 C3 00 E5 21 BF 04 CD 90 FC
E1 3A B9 FF 4F E6 F0 79 20 02 F6 30 CD 37 FC CD
B2 03 CD B2 03 CD B2 03 0E 00 06 02 79 CD 99 03
CD B2 03 0C 10 F6 CD B2 03 79 FE 10 20 EC 79 FE
20 28 09 CD 99 03 0C 18 F5 CD B2 03 E5 21 21 07
CD 90 FC E1 C9 E6 0F CD 36 F8 79 C9 CD B2 03 4D
ED 78 4F CD 90 03 3E 3D CD 37 FC 79 06 08 4F E6
80 3E 30 28 02 3E 31 CD 37 FC 78 FE 05 20 05 3E
5F CD 37 FC 79 07 10 E6 C9 4D ED 59 C9 7D E6 03
6F 4F 3E 01 2C 2D 28 03 07 18 FA 6F 7B FE FF 20
08 7D 2F 6F DB 0A A5 18 1B 0C 0D 20 04 D3 04 18
10 0D 20 04 D3 05 18 09 0D 20 04 D3 06 18 02 D3
09 DB 0A B5 D3 0A C9 CD B7 03 1E FF 0E 04 06 08
7B C6 04 F5 CD AF 03 F1 10 F7 CD B7 03 1D 0D 20
ED CD B7 03 3E 30 CD 37 FC 3E 33 CD 37 FC CD B2
03 DB 09 CD E1 05 2E 02 CD AE 03 DB 06 CD E1 05
2D CD AE 03 DB 05 CD E1 05 2D CD AE 03 DB 04 CD
E1 05 3E 44 CD 37 FC 3E 50 CD 37 FC CD B2 03 DB
0A CD 22 05 C3 B7 03 71 CD C1 03 C8 23 18 F8 3E
80 21 BB FF AE 77 D3 FA C9 CD C1 03 C8 0A BE 20
04 23 03 18 F4 CD B7 03 CD AA 03 CD B2 03 CD 8F
03 CD B2 03 0A CD 90 03 CD 84 12 FE 1B C8 3C 20
F7 18 DE 7E 02 7C BA 20 03 7D BB C8 23 03 18 F3
DB 0A F6 20 D3 0A C9 DB 0A E6 DF D3 0A C9 DD 7D
B7 20 1E F3 21 40 00 11 50 FF 01 3D 00 ED B0 21
7D 00 3E F7 ED 47 57 1E 00 01 10 00 ED B0 ED 5E
C9 3D 20 10 AF D3 04 D3 05 D3 06 D3 09 DB 0A E6
F0 D3 0A C9 3D 20 06 DD 21 03 20 18 06 3D C0 DD
21 06 20 FD E5 DB 09 FD 6F 3E 01 D3 09 DB 0A CB
DF D3 0A CD 9F 06 F5 FD 7D D3 09 F1 FD E1 C9 DD
E9 CD 15 10 20 FB CD 84 12 38 FB F5 CD 72 FC CD
15 10 20 FB F1 FE 03 37 C8 FE 1B 37 C8 B7 C9 0E
1F CD 09 F8 01 00 00 59 51 CD FB 06 3E 0D 0E FF
11 7F 01 CD 2A F8 0E 02 11 03 00 D5 CD FB 06 3E
0D 01 FD 00 11 7C 01 CD 2A F8 D1 01 1B 00 CD FB
06 11 7C 01 3E 07 2E 01 C3 2A F8 3E 05 C3 2A F8
01 32 B4 11 14 00 21 54 01 CD 19 07 3E 12 CD 0C
F8 01 00 00 59 51 21 80 01 3E 10 C3 0C F8 E5 CA
00 E5 C9 00 E5 C4 00 E5 C5 00 C5 E5 DD 6E 01 DD
66 02 DD 5E 03 DD 56 04 0C 0D 28 0A EB 46 23 04
10 FB EB 24 18 F3 F5 CD 3C F8 F1 B7 21 1E 07 C4
90 FC EB CD 90 FC 21 21 07 CD 90 FC E1 C1 C9 DD
46 00 0E 00 AF CD 2A 07 0C 10 F9 4E 3E FF CD 2A
07 E5 21 27 07 CD 90 FC CD A3 10 F5 21 24 07 CD
90 FC AF CD 2A 07 F1 E1 FE 1B 37 C8 FE 03 37 C8
FE 0D 20 16 7E 87 5F 16 00 DD 6E 05 DD 66 06 19
7E 23 66 6F CD A9 07 B7 C9 E9 11 6B 07 D5 FE 19
20 08 35 F0 DD 7E 00 3D 77 C9 FE 1A C0 34 DD 7E
00 BE C0 36 00 C9 CD BF 06 21 38 0E CD 90 FC 01
63 00 11 7E 00 CD FB 06 3E 0D 01 A9 00 11 07 01
CD 2A F8 DD 21 A0 0D 21 FD FF CD 5F 07 30 D7 C9
CD 00 07 0E 4F 06 6E 11 72 00 21 9E 00 CD 19 07
01 00 00 59 51 CD FB 06 3E 0D 01 6D 00 11 9D 00
D5 CD 2A F8 01 14 00 58 50 CD FB 06 D1 CD F4 06
01 54 68 11 85 00 21 80 00 CD 19 07 21 E1 08 CD
90 FC CD 3B 08 CD A1 06 C3 11 07 DB 00 0E FF CD
BD 08 CB 47 06 00 28 01 04 CD AB 08 CD BD 08 CB
4F 06 00 28 01 04 CD AB 08 CD BD 08 CB 57 06 03
28 01 05 CD AB 08 CD BD 08 CB 5F C5 0E 32 28 01
0D F5 CD B2 03 F1 CD 09 F8 C1 CD BD 08 CB 67 06
00 28 01 04 CD AB 08 CD BD 08 CB 6F 06 00 28 01
04 CD AB 08 CD BD 08 CB 77 06 04 28 01 04 CD AB
08 CD BD 08 CB 7F 06 07 28 01 05 F5 CD B2 03 F1
C5 F5 21 F4 08 78 87 87 80 06 05 18 13 F5 CD B7
03 F1 0C C5 F5 06 0E 21 1C 09 79 5F 87 87 87 87
5F 16 00 19 7E ED 44 4F CD 09 F8 23 10 F6 F1 C1
C9 E0 E0 E0 BD B1 B2 BA B7 B9 AB AE BF AC B7 B1
B2 F3 F6 00 A7 9B 8D E0 E0 B2 91 E0 E0 E0 B0 B5
D3 C8 CA B3 C9 D0 D0 C9 AE B1 B3 D3 CE AE B1 B3
D3 BC B1 AE BC B1 AD BD B0 B3 C8 D0 CF E0 BA 94
91 90 90 87 E0 9C 8E 97 8A 9B E0 D3 CE E0 B8 9F
8E 9C E0 9C 8E 97 8A 9B E0 E0 E0 D3 CD E0 B5 9B
87 9E 91 9F 8E 9C E0 E0 E0 E0 E0 D3 CC E0 B0 9F
99 9B E0 BD B0 D1 B3 D3 C8 D0 E0 D3 CB E0 BB 88
8C D2 9C 97 8D 90 94 9F 87 E0 E0 D3 CA E0 AD 8C
9F 8E 8C D3 B3 9B 92 8B E0 E0 E0 D3 C9 E0 B4 91
9F 9C E0 B1 AE BC B1 AD E0 E0 E0 D3 C8 E0 AD 87
8D 8C 9B 93 E0 E0 E0 E0 E0 E0 E0 D3 CD 00 07 01
37 00 11 46 00 D5 CD FB 06 01 D7 00 11 3E 01 3E
0D CD 2A F8 01 4B 00 CD FB 06 D1 CD F4 06 01 C3
00 CD FB 06 11 3E 01 CD F4 06 21 F3 0B CD 90 FC
01 00 10 11 9B 0B 26 08 79 FE 08 38 04 26 0E D6
08 87 87 C6 11 6F CD 3C F8 3E 44 CD 37 FC 1A CD
15 F8 13 0C 10 E0 DD 21 AB 0B DD 6E 00 DD 66 01
DD 23 DD 23 7D B4 28 1D 11 CD 0B 0E 20 1A B7 28
E9 47 13 1A 77 2C 0D 20 07 0E 20 24 7D 91 6F 1A
10 F2 13 18 E8 21 C9 D0 0E 11 06 08 36 00 78 FE
04 20 02 36 AA 2C 10 F4 2E C9 24 0D 20 EC DB 0A
CB CF D3 0A FD 26 00 FD 2E 00 FD 7D FE 20 30 5D
D3 05 FE 03 28 12 FE 1F 28 0E 21 00 40 11 01 40
FD 7C 77 01 FF 3F ED B0 21 C9 D0 7E E6 01 28 03
24 18 F8 FD 7D E6 07 3C 47 3E 01 0F 10 FD 4F 06
08 7E B1 77 2C 10 FA DB 00 E6 04 28 12 AF D3 18
DB 19 EE FF 28 13 CD 72 FC CD A1 06 30 0B C9 AF
D3 1A D3 19 DB 18 3C 20 ED FD 2C 18 9D FD 2E 00
FD 7D FE 20 D2 73 0B D3 05 FE 03 CA 2D 0B FE 1F
CA 2D 0B 21 00 40 44 4D FD 5C 7E AB CA 26 0B D9
4F 1E 00 06 08 DB 05 CB 57 28 02 1E 10 CB 09 30
3E 21 AB 0B 16 00 19 7E 23 66 6F 2C 7E 2D E6 7F
20 2D FD 6B DD 69 DD 60 11 E0 0B 0E 20 1A B7 28
14 47 13 1A 77 2C 0D 20 07 0E 20 24 7D 91 6F 1A
10 F2 13 18 E8 FD 5D DD 4D DD 44 DB 05 FD 6F 1C
1C 05 C2 DD 0A D9 23 0B 78 B1 C2 CA 0A 21 C9 D0
7E E6 01 28 03 24 18 F8 FD 7D E6 07 3C 47 3E 01
0F 10 FD 4F 06 08 7E B1 77 2C 10 FA DB 00 E6 04
28 12 AF D3 18 DB 19 EE FF 28 13 CD 72 FC CD A1
06 30 0B C9 AF D3 1A D3 19 DB 18 3C 20 ED FD 2C
C3 B0 0A FD 7C 2F FD 67 B7 C2 47 0A 21 C9 E0 06
08 3E FC 77 2C 10 FC 21 00 F0 2B 7C B5 20 FB AF
D3 05 DB 0A CB 8F D3 0A C3 25 0A 70 60 61 59 73
65 62 64 52 71 54 57 63 74 72 53 9A D3 5E D3 9A
D0 5E D0 9A D6 5E D6 5E CD 9A CD 9A E2 5E E2 5E
DC 9A DC 9A D9 5E D9 5E DF 9A DF 00 00 01 FF 1A
80 01 83 03 84 02 FF 1A 01 01 C1 03 21 01 FF 00
1B FF 01 FC 02 FB 01 F8 1C FF 01 3F 02 DF 01 1F
01 FF 00 E5 A7 DA C4 AE BF B3 E0 AC BB AD AC 00
CD 00 07 01 73 00 11 74 00 D5 CD FB 06 3E 0D 01
A2 00 11 11 01 CD 2A F8 01 87 00 CD FB 06 D1 CD
F4 06 21 64 0C CD 90 FC CD 22 0D E5 CD 15 F8 CD
FE 0C D1 21 21 0E E5 CD 3C F8 78 CD 15 F8 79 CD
15 F8 E1 24 CD 3C F8 7A CD 15 F8 7B CD 15 F8 01
00 10 CD 12 F8 28 06 CD 72 FC C3 A1 06 0B 78 B1
20 F0 18 BE E5 A7 D4 C3 AE B1 B3 E0 AC BB AD AC
E5 A7 D2 C9 AE B1 B3 CF E0 BD AD C6 E0 E0 E0 E0
E0 E0 E0 D8 E0 C8 B5 D7 E5 A7 D1 C9 AE B1 B3 CE
E0 BD AD C6 E0 E0 E0 E0 E0 E0 E0 D8 E0 E0 B5 D7
F8 F8 F8 F8 00 3E 02 D3 F8 11 EE 0C 21 00 C0 06
03 36 FF 1A 4F 3E 01 CD 39 F8 2C 20 F4 24 7C FE
F0 28 05 10 EC 13 18 E7 01 00 10 79 07 07 07 07
B1 D3 E0 D3 E1 D3 E2 0C 10 F1 3E 06 D3 F8 CD A1
06 38 06 CD 18 01 CD A1 06 3E 0F D3 F8 C9 00 08
01 09 04 0C 05 0D 02 0A 03 0B 06 0E 07 0F 21 00
00 11 FF 1F EB E5 7D 21 00 00 18 06 EB 46 48 23
EB 09 BB 20 F7 C1 C5 78 BA 79 20 F0 1A 85 4F 44
E1 C9 21 08 20 0E 04 CD 8D 00 06 08 3E 64 20 04
06 04 3E 32 F5 11 00 40 AF 12 4F 6F 67 DB 0A F5
CB DF D3 0A 78 3D 20 01 1B 79 D3 09 C5 D5 E5 21
00 20 CD 04 0D E1 09 D1 C1 0C 10 E8 F1 D3 0A F1
C9 04 1B 0B 68 0D 98 0D E0 E0 B3 91 92 97 8C 91
8E E0 E0 00 E0 B1 8E 97 91 92 D3 B0 AE B1 E0 00
E0 B1 8E 97 91 92 D3 CF CE C8 E0 00 E0 E0 AC E0
BB E0 AD E0 AC E0 E0 00 67 02 C5 01 D0 01 C6 07
05 19 0B A7 0D F7 0D E0 BD 91 92 9A 97 99 8B 8E
9F 8C 97 91 92 E0 00 E0 AE BF B3 E0 D3 E0 AC E0
9B E0 8D E0 8C E0 00 E0 AE B1 B3 E0 D3 E0 AC E0
9B E0 8D E0 8C E0 00 E0 AC AA E0 E0 D3 E0 AC E0
9B E0 8D E0 8C E0 00 E0 E0 E0 B3 9F 97 92 E0 B3
9B 92 8B E0 E0 E0 00 F0 07 9C 09 00 0C A5 0C 36
02 E5 A7 DF DE D8 BD D7 E0 CF C7 C7 CD D3 CE D0
D0 D0 E0 B1 8E 97 91 92 8D 91 9A 8C E0 BD 91 D2
D4 B4 8C 9C E5 A7 DF B1 B1 8E 97 91 92 D3 B0 8E
91 E0 AA CD D2 CF D0 00 E5 A7 DF CB D6 E0 AC BB
AD AC E0 B1 AE B7 B1 B2 D3 B0 AE B1 E0 D6 00 E1
E5 A7 DF DE D8 BD D7 E0 CF C7 C7 CD D3 CF C7 C7
C9 E0 B1 8E 97 91 92 8D 91 9A 8C E0 BD 91 D2 E5
A7 DF B1 B1 8E 97 91 92 D3 B0 8E 91 E0 AA CD D2
CF D0 F3 F6 00 E1 F6 F6 E0 AD 87 8D 8C 9B 93 E0
B3 B1 B2 B7 AC B1 AE E0 E0 AA CE D2 CF D0 F3 F6
00 F3 F6 E0 D3 E0 B3 E0 BC E0 BA E0 AC E0 BD E0
D3 E0 B7 E0 B1 E0 AA E0 A9 E0 A8 E0 CE E0 C8 E0
D3 E0 B9 E0 D3 F3 F6 00 F3 F6 F6 C3 C2 F9 00 DD
7D D6 13 D2 F0 0F C6 13 20 0C E5 2A 69 FF AF 77
E1 ED 53 66 FF C9 3D 20 16 2A 69 FF 7E 5F B7 16
00 E5 19 0E FF 28 01 4E E1 23 ED 5B 66 FF C9 3D
20 08 22 6E FF ED 53 6B FF C9 3D 20 08 2A 6E FF
ED 5B 6B FF C9 3D 20 09 ED 43 74 FF ED 53 76 FF
C9 3D 20 09 ED 4B 74 FF ED 5B 76 FF C9 3D 20 09
ED 43 78 FF ED 53 7A FF C9 3D 20 09 ED 4B 78 FF
ED 5B 7A FF C9 3D 20 09 ED 43 7C FF ED 53 7E FF
C9 3D 20 09 ED 4B 7C FF ED 5B 7E FF C9 3D 20 08
22 84 FF 79 32 86 FF C9 3D 20 08 2A 84 FF 3A 86
FF 4F C9 3D 20 08 22 87 FF 79 32 89 FF C9 3D 20
08 2A 87 FF 3A 89 FF 4F C9 3D 20 08 22 8A FF 79
32 8C FF C9 3D 20 08 2A 8A FF 3A 8C FF 4F C9 3D
20 29 D5 E5 2A 82 FF 11 A6 FF 71 CD C5 0F 23 38
03 21 97 FF ED 5B 80 FF CD C5 0F 37 28 04 22 82
FF B7 E1 D1 C9 E5 B7 ED 52 E1 C9 3D 20 19 D5 E5
CD FA 0F 38 ED 4E 11 A6 FF CD C5 0F 23 38 03 21
97 FF 22 80 FF 18 DA E5 2A 82 FF 22 80 FF E1 C9
20 16 D5 E5 CD FA 0F E1 D1 C9 2A 80 FF ED 5B 82
FF CD C5 0F 37 C8 B7 C9 3D 20 04 22 72 FF C9 3D
C0 2A 72 FF C9 DB 00 E6 04 28 0B AF D3 18 DB 19
EE FF C8 3E FF C9 AF D3 1A D3 19 DB 18 3C C8 3E
FF D3 1A 3E FC D3 19 00 DB 18 E6 E3 FE E3 20 11
3E 03 D3 19 00 DB 18 3C 20 07 D3 1A 00 DB 18 3C
C8 3E FF C9 CD 84 12 CB 69 C8 CB 61 C8 1B 1C 1D
C0 14 15 C0 ED 5B 6B FF CB 79 28 15 CB B9 C5 D5
E5 F5 3E 06 CD 0F F8 3E 03 CD 0F F8 F1 E1 D1 C1
C9 CB F9 C5 D5 E5 F5 3E 06 CD 0F F8 3E 02 18 E9
3A 66 FF E6 03 FE 02 C9 DB 00 E6 04 C0 3A 66 FF
CB 7F C9 C5 D5 E5 3E F1 CD CE 0F 79 30 2D CD 39
11 F5 CD E9 0E FE 03 30 21 46 7A E6 03 FE 03 28
19 5F 87 83 5F 16 00 21 84 FF 19 79 FE 04 28 04
FE 0A 20 01 78 CD DF 10 30 CD F1 E1 D1 C1 C9 0E
0A ED 40 C5 CB C8 ED 41 CB 39 ED 40 C5 5E 23 56
23 ED A3 EB CB BC CB F4 E5 CD 0A 11 E1 D4 1D 11
D4 29 11 C1 ED 41 C1 ED 41 C9 06 00 4E 37 0C 0D
C8 23 C5 ED B1 79 C1 37 C0 91 2F B7 C9 4E 23 09
3C 3D B7 C8 4E 23 09 18 F8 46 37 04 05 C8 23 4E
CD A2 0F 38 02 10 F7 B7 C9 3E 0F CD 0F F8 CB B9
CB 69 C4 81 10 ED 5B 6B FF 18 0D F1 2A 6E FF 18
04 F1 21 01 00 22 70 FF CD 54 10 47 30 07 C5 CD
A1 11 C1 18 ED CD 19 12 30 E8 2A 70 FF E5 AF 3D
20 FD CD 54 10 38 DA B8 20 D1 2B 7C B5 20 EF E1
2B 7C B5 2A 6E FF 28 03 21 02 00 22 70 FF CB 79
C4 6C 10 78 32 68 FF ED 5B 66 FF F5 CD 60 F8 F1
C9 21 67 FF 4E CD 98 10 78 28 55 FE FE 20 2B CD
90 10 28 06 30 44 CB 7E 20 12 7E EE 40 77 C5 D5
E5 79 ED 5B 66 FF CD 63 F8 E1 D1 C1 CD 84 12 30
FB 3C 20 F8 7E E6 1F 20 F3 C9 FE 0F 20 04 CB BE
18 DC FE 0E 20 09 CD 90 10 30 E1 CB FE 18 CF CB
4E C8 CB 46 C8 CD 90 10 28 C0 7E EE 20 77 18 BE
CB 56 C8 CB 4E 20 EE CB 5E 20 A4 CB 66 C8 CD 90
10 30 B9 7E EE 80 77 18 A5 CD 98 10 37 C8 CD 90
10 3F D8 21 73 FF 7E 2B BE 20 0C B8 37 C0 21 67
FF CB 7E 28 B1 18 A7 7E B8 23 7E 21 67 FF 28 9E
B8 28 A3 37 C9 DB 00 E6 04 28 13 AF D3 18 DB 19
B7 20 15 DB 1A F6 1F 3C 20 0E F6 FF 37 C9 AF D3
19 D3 1A DB 18 3C 28 F2 CD 84 12 E5 C5 D5 47 30
09 CD A1 11 F6 FF 37 C3 C3 12 CD 19 12 30 F5 78
B7 C3 C3 12 E5 C5 D5 CD 46 16 A7 28 2A FE 04 30
26 21 67 FF 57 1E 00 7E E6 1F 28 49 06 05 0F 30
01 1C 10 FA 7A BB 20 1F 3D 20 0C CB 56 20 0B CB
66 20 0A CB 5E 20 09 3E FF 21 3E FE 21 3E 0E 21
3E 0F 37 D1 C1 E1 C9 79 FE 0D 30 15 7A FE 02 20
E6 79 FE 0A 30 04 FE 04 20 07 E5 2A 69 FF 23 4E
E1 CB 56 20 D2 51 79 21 A2 13 01 04 00 ED B1 20
1B 3E 03 91 4F 21 74 FF 09 3A 67 FF E6 03 87 87
4F 7B FE 02 38 02 0E 00 09 7E 18 B7 4A 21 B6 13
11 0E 14 CD 90 10 3A 67 FF 38 10 EB 20 32 CB 5F
28 02 EE 40 CB 77 20 2D EB 18 2A CB 47 20 26 21
16 15 11 50 FF CB 67 28 02 EE 80 CB 7F 20 0C 19
CB 5F 28 02 EE 40 CB 77 20 01 19 EB 21 58 00 19
CB 6F 28 01 EB CB 4F 28 19 EB 09 DB 00 E6 04 20
18 79 E5 21 A6 13 0E 10 ED B1 E1 20 0C 7E EE 10
18 08 09 DB 00 E6 04 20 E8 7E 4F CD 90 10 3D 20
0B 21 C6 15 79 D6 80 38 03 4F 09 4E 21 C3 12 E5
3A 67 FF B7 CB 47 79 C8 FE 40 3F D0 FE 7F D0 E6
1F C9 4C 35 3E 3D 19 21 29 30 39 41 48 50 57 4F
47 46 10 37 54 45 39 38 00 00 00 34 35 36 1B 09
00 0E 0F 2B 2D 0D 2B 4A 46 51 00 30 2E 2C 00 21
43 59 5E 31 32 33 01 22 55 57 53 37 0C 1F 02 23
4B 41 4D 7F 1E 0A 24 45 50 49 20 18 0D 3F 03 25
4E 52 54 1A 19 5F 04 26 47 4F 58 3E 2A 3D 27 5B
4C 42 08 5C 48 20 28 5D 44 40 3C 56 5A 29 39 38
00 00 00 34 35 36 1B 09 00 0E 0F 2B 2D 0D 2B 6A
66 71 00 30 2E 2C 00 21 63 79 7E 31 32 33 01 22
75 77 73 37 0C 1F 02 23 6B 61 6D 7F 1E 0A 24 65
70 69 20 18 0D 3F 03 25 6E 72 74 1A 19 5F 04 26
67 6F 78 3E 2A 3D 27 7B 6C 62 08 7C 68 20 28 7D
64 60 3C 76 7A 29 39 38 00 00 00 34 35 36 1B 09
00 0E 0F 2B 2D 0D 2B 89 94 9F 00 30 2E 2C 00 21
96 9B 97 31 32 33 01 22 93 82 91 37 0C 1F 02 23
8A 80 8C 7F 1E 0A 24 85 8F 88 20 18 0D 3F 03 25
8D 90 92 1A 19 9A 04 26 83 8E 9C 3E 2A 3D 27 98
8B 81 08 9D 95 20 28 99 84 9E 3C 86 87 29 39 38
00 00 00 34 35 36 1B 09 00 0E 0F 2B 2D 0D 2B A9
E4 EF 00 30 2E 2C 00 21 E6 EB E7 31 32 33 01 22
E3 A2 E1 37 0C 1F 02 23 AA A0 AC 7F 1E 0A 24 A5
AF A8 20 18 0D 3F 03 25 AD E0 E2 1A 19 EA 04 26
A3 AE EC 3E 2A 3D 27 E8 AB A1 08 ED E5 20 28 E9
A4 EE 3C A6 A7 29 39 38 00 00 00 34 35 36 1B 09
00 0E 0F 2B 2D 0D 2B C9 CC C8 00 30 2E 2C 00 21
CB CE CA 31 32 33 01 22 BB B9 BC 37 0C 1F 02 23
D6 C7 D3 7F 1E 0A 24 D2 D7 D0 20 18 0D 3F 03 25
B7 B6 BD 1A 19 F0 04 26 B0 DD B2 3E 2A 3D 27 DF
FE DC 08 BA CD 20 28 B1 DE DB 3C FD FB 29 39 38
00 00 00 34 35 36 1B 09 00 0E 0F 2B 2D 0D 2B DA
C3 C0 00 30 2E 2C 00 21 C2 C5 C1 31 32 33 01 22
BF B4 D9 37 0C 1F 02 23 D5 C6 D4 7F 1E 0A 24 D1
D8 CF 20 18 0D 3F 03 25 B8 B5 BE 1A 19 F1 04 26
F5 F7 F2 3E 2A 3D 27 F8 FF F9 08 B3 C4 20 28 F4
F6 F3 3C FC FA 29 E1 E2 F7 E7 E4 E5 F6 FA E9 EA
EB EC ED EE EF F0 F2 F3 F4 F5 E6 E8 E3 FE FB FD
FF F9 F8 FC E0 F1 C1 C2 D7 C7 C4 C5 D6 DA C9 CA
CB CC CD CE CF D0 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9
BA BB BC BD BE BF 80 81 82 83 84 85 86 87 88 89
8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99
9A 9B 9C 9D 9E 9F D2 D3 D4 D5 C6 C8 C3 DE DB DD
DF D9 D8 DC C0 D1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
AA AB AC AD AE AF 21 67 FF 3E E0 A6 77 AF 2A 69
FF 77 23 EB 21 FE FF DB 00 E6 04 20 73 0E 00 7D
D3 19 7C D3 1A DB 18 FE FF 28 49 47 3A 6D FF 3D
20 FD DB 18 B8 20 3D 06 09 0D 0C 05 28 3A 0F 38
F9 EB 71 23 F6 80 77 EB E5 F5 21 67 FF 79 FE 04
20 02 CB CE FE 0A 20 02 CB C6 FE 14 20 02 CB D6
FE 0B 20 02 CB E6 FE 0C 20 02 CB DE 2A 69 FF 34
F1 E1 18 C6 79 C6 08 4F CB 35 CB 14 7C FE F7 20
9E 2A 69 FF EB 1A A7 0E FF 28 02 2B 4E EB 23 C9
21 7F 09 0E 00 DB 1A F6 1F FE FF 28 51 18 15 7D
D3 18 DB 19 FE FF 28 46 47 3A 6D FF 3D 20 FD DB
19 B8 20 3A 06 09 0D 0C 05 28 37 0F 38 F9 EB F5
C5 E5 21 67 FF 79 FE 05 20 02 CB CE FE 06 20 02
CB C6 FE 07 20 02 CB D6 2A 69 FF 34 21 34 17 06
00 09 7E E1 77 C1 F1 23 F6 80 77 EB 18 C9 79 C6
08 4F CB 05 25 20 A8 18 88 04 0A 14 26 27 08 18
20 28 38 40 09 2F 36 2D 4C 3E 35 3D 4F 19 21 29
30 39 41 48 50 57 46 10 54 47 45 37 53 2B 4B 1A
52 31 12 42 4E 33 11 2A 4A 2C 3A 43 32 13 3B 24
3C 22 55 23 44 1B 56 49 4D 51 1C 34 DD 7D B7 C2
09 19 CD B4 18 2A 57 FF E5 26 00 22 AF FF 7D 25
ED 44 6F 22 B1 FF E1 6C 26 00 22 AB FF 7D 25 ED
44 6F 22 AD FF ED 4B A9 FF ED 5B A7 FF 3E 02 CD
0F F8 30 08 3E 03 CD 0F F8 37 18 63 CD 4E F8 CB
67 28 F9 CB 6F 28 F5 CD 15 10 20 FB CD 6E 18 30
FB ED 43 A9 FF ED 53 A7 FF 6F 3E 03 CD 0F F8 7D
E6 30 FE 30 20 2B 7D CB 47 CC 54 18 CB 4F CC 5A
18 CB 57 CC 60 18 CB 5F CC 67 18 3E 02 CD 0F F8
30 CA ED 4B A9 FF ED 5B A7 FF 3E 02 CD 0F F8 18
BB AF CB 65 20 02 CB FF CB 6D 20 02 CB F7 B7 F5
ED 4B BD FF ED 5B BF FF 2A C1 FF 3E 14 CD 0F F8
ED 4B B9 FF 2A BB FF 3E 12 CD 0F F8 ED 4B B3 FF
ED 5B B5 FF 2A B7 FF 3E 10 CD 0F F8 4C 3E 0E CD
0F F8 F1 C9 2A AD FF 19 EB C9 2A AB FF 19 EB C9
2A AF FF 09 44 4D C9 2A B1 FF 09 44 4D C9 CD 4E
F8 E6 3F FE 3F 37 C0 21 00 02 2B 7C B5 20 FB CD
27 F8 E6 F0 20 11 CD 84 12 2E 1F FE 0D 28 22 2E
2F FE 1B 28 1C AF C9 2E 3F CB 67 28 02 CB 85 CB
6F 28 02 CB 9D CB 77 28 02 CB 8D CB 7F 28 02 CB
95 7D 37 C9 3E 0F CD 0F F8 61 3E 11 CD 0F F8 ED
43 B3 FF ED 53 B5 FF 22 B7 FF 3E 13 CD 0F F8 ED
43 B9 FF 22 BB FF 3E 15 CD 0F F8 ED 43 BD FF ED
53 BF FF 22 C1 FF CD 14 19 3E 0E CD 0F F8 CD 2C
19 01 00 00 3E 10 CD 0F F8 CD 47 19 3E 12 CD 0F
F8 CD 61 19 3E 14 C3 0F F8 3D 20 05 79 32 50 FF
C9 3D 20 05 3A 50 FF 4F C9 3D 20 0D ED 53 54 FF
ED 43 57 FF 7D 32 56 FF C9 3D 20 0D ED 5B 54 FF
ED 4B 57 FF 3A 56 FF 6F C9 3D 20 08 22 51 FF 79
32 53 FF C9 3D 20 08 2A 51 FF 3A 53 FF 4F C9 3D
20 0C 22 5D FF ED 43 59 FF ED 53 5B FF C9 3D 20
0C 2A 5D FF ED 4B 59 FF ED 5B 5B FF C9 3D C0 C5
E5 CD B4 18 3E 16 CD 0F F8 D5 CD 1F 18 D1 E1 C1
C9 F7 9A 8E 91 93 E0 9A 94 91 90 90 87 E0 9C 97
8D 95 F3 F6 00 F7 E0 9A 8E 91 93 E0 B7 BC BB 00
00 00 3E 80 D3 FB AF C9 B2 91 92 D3 8D 87 8D 8C
9B 93 E0 9C 97 8D 95 DF 00 BC 97 8D 95 E0 9E 91
91 8C E0 9A 9F 97 94 8B 8E 9B DF 00 F3 F6 F6 E0
BB AE AE B1 AE C6 E0 00 E0 A5 BF B0 CE D3 AF 8B
97 8C A3 00 E1 F3 F6 E0 B1 8E 97 91 92 D3 B0 8E
91 E0 8D 87 8D 8C 9B 93 F7 F7 F7 D8 BD D7 E0 CF
C7 C7 CD D3 CE D0 D0 D0 E0 B1 8E 97 91 92 8D 91
9A 8C F3 F6 00 F3 F6 E0 B4 91 9F 9C 97 92 99 E0
BC 97 8D 95 E0 B1 90 9B 8E 9F 8C 97 92 99 E0 AD
87 8D 8C 9B 93 F3 F6 00 CD 03 20 F1 4F 3E 01 CD
30 F8 C7 C3 66 F8 C3 32 FB C3 37 FB C3 58 FA C3
4B FA C3 4B FA C3 28 FB C3 23 FC C3 3B FA C3 2D
FB C3 4C FA C3 25 FD C3 01 FC C3 A9 FC C3 4B FA
C3 4B FA C3 52 FD C3 6F FD C3 6B FA C3 5F FA C3
44 FA C3 3E FC C3 7A FA C3 93 FA C3 AC FA C3 D9
FA C3 F6 FB C3 43 FB C3 01 FA C3 0C FA C3 1C FB
C3 21 FD C3 72 FC C3 4B FA 31 C0 F7 DB 0A F6 18
D3 0A 21 E4 19 CD 90 FC 01 C4 40 CD 09 F8 10 FB
21 15 1A CD 90 FC DB 0A E6 E0 D3 0A DB 00 0F DA
5D F9 3E 10 D3 14 3E D0 CD E6 F9 3E 4B CD E6 F9
3E 08 CD E6 F9 06 0A C5 01 01 00 11 00 00 CD 3F
F8 C1 DB 10 CB 4F 28 05 10 ED C3 5D F9 11 00 00
DB 10 07 D2 FE F8 3E 0A 3D 20 FD 1B 7A B3 20 F0
C3 5D F9 21 A8 19 18 03 21 B9 19 E5 21 CC 19 CD
90 FC E1 CD 90 FC 21 D8 19 CD 90 FC CD 32 FB FE
03 28 05 FE 1B C2 66 F8 DB 0A F6 10 D3 0A C3 1C
02 21 81 19 CD 90 FC 3E 01 D3 12 21 00 B0 CD 01
FA 20 C5 7E FE C3 20 BB 21 00 B0 11 00 00 01 00
02 3A 2F B0 3C CA 00 B0 FE 05 D2 D0 F8 3D 20 02
06 04 F5 CD 6F FD F1 D3 08 FE 02 D2 00 00 31 C0
F3 F5 DB 0A F6 18 D3 0A AF D3 09 3A 03 20 FE C3
20 F9 21 38 1A 11 A0 F3 01 0B 00 ED B0 C3 A0 F3
DB 00 CB 4F 28 1E CD E1 F9 DB 0A F6 18 D3 0A 21
08 20 0E 04 CD 8D 00 28 08 2A 00 20 7D BC C2 00
20 C3 1C 02 CD E1 F9 21 95 19 CD 90 FC 3E 02 D3
56 11 FF 06 1B 7A B3 CA D5 F8 06 FF E3 E3 E3 E3
E3 10 F9 DB 5F B7 FA 91 F9 00 00 00 00 E6 01 C2
D5 F8 21 00 B0 3E 21 D3 5F DB 5F CB 7F 20 FA CB
5F 28 0C 00 00 DB 58 77 23 DB 57 77 23 10 F6 DB
5F E6 21 C2 D5 F8 21 00 B0 C3 10 F9 D3 10 3E 2F
3D 20 FD C9 DB 00 0F D8 AF CD D9 F9 DB 10 0F 38
FB C9 3E 80 CD D9 F9 DB 10 1F D0 1F 30 F9 DB 13
77 23 18 F3 E5 CD EF F9 EB E1 DB 10 E6 DD C9 3E
A0 CD D9 F9 E5 ED 73 37 FA F9 0E 13 E1 DB 10 EE
01 28 FA ED 69 1F 38 0D 1F 30 F2 DB 10 EE 01 28
FA ED 61 18 E7 21 FE FF 39 31 00 00 18 CA 7E A7
C8 CD 37 FC 23 18 F7 F5 3E 05 CD 0F F8 F1 C9 F5
C5 D5 3E 06 CD 0F F8 D1 C1 F1 C9 F5 AF CD 0F F8
F1 C9 F5 DB 08 32 76 FA F1 D3 08 71 18 0A F5 DB
08 32 76 FA F1 D3 08 4E 3E 00 D3 08 C9 E5 C5 01
04 03 ED 78 77 23 0C 10 F9 0C 06 03 ED 78 77 23
0C 10 F9 C1 E1 C9 E5 C5 01 04 03 7E ED 79 23 0C
10 F9 0C 06 03 7E ED 79 23 0C 10 F9 C1 E1 C9 3C
20 04 22 BC FA C9 C5 3D 87 87 87 4F 06 00 21 00
00 09 01 04 03 7E 23 ED 79 0C 10 F9 0C 06 03 7E
23 ED 79 0C 10 F9 7E 23 66 6F C1 E9 E5 32 ED FA
79 E6 07 6F 4F 3E 01 2C 2D 28 03 07 18 FA 6F 3E
00 A7 20 08 7D 2F 6F DB 0A A5 18 1F 78 0C 0D 20
04 D3 04 18 13 0D 20 04 D3 05 18 0C 0D 20 04 D3
06 18 05 0D 20 02 D3 09 DB 0A B5 D3 0A E1 C9 DD
E5 DD 6F 3E 15 CD 03 FC DD E1 C9 3E 0C C3 03 FC
3E 0F C3 03 FC 3E 09 C3 03 FC DD E5 DD 6F 3E 06
CD 03 FC DD E1 C9 B7 28 11 FE 0A D2 98 FB DD E5
DD 6F 3E 18 CD 03 FC DD E1 C9 ED 43 A9 FF ED 53
A7 FF E5 CD 1E F8 E5 3E 11 CD 0C F8 C5 D5 E5 3E
05 CD 0C F8 3A 50 FF 07 3E 04 DC 0C F8 AF CD 4B
FB E1 D1 C1 F5 3E 10 CD 0C F8 F1 E1 F5 CD 3C F8
F1 E1 ED 4B A9 FF ED 5B A7 FF C9 C0 AF B8 D8 7E
B7 23 37 C8 DD E5 E5 DD E1 F5 F5 C5 CD CA FB 30
12 01 06 00 DD 09 C1 F1 3D 20 EF F1 37 DD E5 E1
DD E1 C9 C1 79 C1 4F F1 90 06 00 18 F0 DD 6E 00
DD 66 01 E5 37 ED 52 E1 3F D8 79 DD 4E 03 DD 46
04 0B 09 4F B7 ED 52 D8 DD 7E 02 37 99 3F D8 DD
46 05 DD 7E 02 05 80 B9 C9 C5 DB 1E 4F DB 1E B9
20 F8 C1 C9 3E 12 ED 73 20 FC 31 FD FF 32 17 FC
DB 0A 32 1B FC F6 10 D3 0A CD 00 00 F5 3E 00 D3
0A F1 31 00 00 C9 F5 0F 0F 0F 0F CD 2C FC F1 E6
0F FE 0A FA 35 FC C6 07 C6 30 C5 4F CD 09 F8 C1
C9 DB 0A 32 68 FC CB EF D3 0A C5 D5 E5 21 00 00
78 B1 28 16 0B C5 06 20 7C 19 19 AC 07 30 02 D3
FF 00 00 3E 00 10 F1 C1 18 E6 3E 40 D3 0A 22 4B
FC E1 D1 C1 C9 7B E6 03 FE 03 7A 01 14 00 11 00
04 20 06 EE 20 CB 6F 18 02 CB 77 28 03 11 00 08
C3 3F F8 DB 0A F5 C5 CB E7 D3 0A 7E A7 28 08 ED
44 CD 37 FC 23 18 F4 C1 F1 D3 0A C9 E5 2E 00 DB
00 E6 04 C2 0A FD 3E FF D3 1A 3E FC D3 19 DB 18
CB 57 20 02 CB C5 E6 10 20 02 CB CD 3E FB D3 19
DB 18 E6 10 20 02 CB D5 3E BF D3 19 DB 18 E6 20
F6 DF 67 3E 7F D3 19 DB 18 CB 6F 20 02 CB B4 CB
77 20 02 CB A4 3E FF D3 19 3E FD D3 1A DB 18 E6
10 20 02 CB 9C 7C 2F 07 E6 F0 B5 E1 C9 DB 1A 2F
17 CB 15 17 F5 17 CB 15 F1 CB 15 3E FD D3 18 DB
19 2F 18 E4 21 00 21 C9 A7 28 0E C5 06 05 00 DB
02 07 07 07 A8 E6 07 C1 C9 C5 D5 E5 CD 28 FD 20
10 79 2F D3 01 3E 01 D3 02 00 00 AF D3 02 CD 28
FD E1 D1 C1 C9 F5 DB 08 32 6B FD F1 E6 0F D3 08
71 42 4B 54 5D 13 0B 79 B0 28 02 ED B0 3E 00 D3
08 C9 F5 E6 0F 32 90 FD F1 0F 0F 0F 0F E6 0F 32
8B FD DB 08 32 A2 FD ED 73 A6 FD F9 EB 3E 00 D3
08 D1 3E 00 D3 08 73 23 0B 78 B1 28 07 72 23 0B
78 B1 20 E9 3E 00 D3 08 31 00 00 C9 FB ED 4D 00
FF FF FF FF FF FF FF FF FF FF 00 B0 00 00 00 00

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@ -0,0 +1,969 @@
.org 0
_p00_config = 0x0000
_p03_set = 0x0003
_p04_RAM0 = 0x0004
_p05_RAM1 = 0x0005
_p06_RAM2 = 0x0006
_p07_set = 0x0007
_p0a_mem_man = 0x000a
_p0b_set = 0x000b
_p1d_set = 0x001d
_p3b_set = 0x003b
_pfa_vbank = 0x00fa
_pfc_color_reg = 0x00fc
_pf8_vmode = 0xf8
CONFIG_TURBO_BIT = 3
CONFIG_WIDE_BIT = 4
CONFIG_MEM_TEST_BIT = 5
MEMM_RAM0EN_BIT = 0
MEMM_RAM1EN_BIT = 1
MEMM_RAM2EN_BIT = 2
MEMM_TURBO_BIT = 5
VB_WIDE_BIT = 7
VBANK_START = 0xc000
RAM1_WINDOW = 0x4000
TEST_16C_PALLETE = 0x5f
TEST_VBANK_IDX = 0x00
; registers global:
; B - configuration switches
; C - phase (0x00/0xFF)
init:
ld sp, 0x3fff
ld a, 0x98
out (_p03_set), a
ld a, 0x80
out (_p07_set), a
ld a, 0x80
out (_p0b_set), a
ld a, 0x92
out (_p1d_set), a
ld a, 0x16
out (_p3b_set), a
ld a, 0x56
out (_p3b_set), a
ld a, 0x96
out (_p3b_set), a
ld a, 0x10
out (_p0a_mem_man), a
ld a, 0x00
out (_pf8_vmode), a
jp fill_vmem
main:
in a, (_p00_config)
ld b, a ; save configuration to B
jp set_turbo
main_turbo:
ld a, TEST_VBANK_IDX
jp set_vbank ; set video bank to 0 (0xC000-0xFFFF)
main_vbank:
bit CONFIG_MEM_TEST_BIT, b
jr NZ, mem_test
main_memt:
ld a, b ; load configuretion to A
and 0x07 ; extract video test number
ld h, 0
ld l, a
add hl, hl
ld de, video_tests
add hl, de
ld a, (hl)
inc hl
ld h, (hl)
ld l, a
jp (hl)
main_video_end:
ld de, TEST_TITLE
ld iyh, 0
ld iyl, 28
ld hl, main_title_end
jp print_str
main_title_end:
; wait loop
ld d, 0
wait_loop0:
inc d
ld hl, 0x0000
wait_loop1:
inc hl
ld a, h
sub a, 0x80
jr C, wait_loop1
ld a, d
sub a, 4
jr C, wait_loop0
jr main
TEST_TITLE:
.db "ORION-128 NG tests (andreil, 2020)", 0x00
mem_test:
; monochrome video mode
ld a, VMODE_2COLOR_1PALLETE
out (_pf8_vmode), a
; disable widescreen
ld a, TEST_VBANK_IDX
out (_pfa_vbank), a
; enable turbo mode
in a, (_p0a_mem_man)
set MEMM_TURBO_BIT, a
out (_p0a_mem_man), a
mem_test_main_loop:
; draw screen
ld de, TEST_TITLE
ld iyh, 0
ld iyl, 31
ld hl, main_title_end
jp print_str
jr mem_test_main_loop
video_tests:
.DW test_2colors_pallet1
.DW test_2colors_pallet2
.DW test_4colors_pallet1
.DW test_4colors_pallet2
.DW test_16colors_group
.DW test_16colors_pallet
.DW test_3bit
.DW test_4bit
fill_vmem:
; enable window on RAM1
in a, (_p0a_mem_man)
set MEMM_RAM1EN_BIT, a
out (_p0a_mem_man), a
ld c, 0
; set RAM 1 segment
loop_seg:
ld a, c
out (_p05_RAM1), a
; screen pointer
ld hl, RAM1_WINDOW
ld d, 00
loop_vm:
ld (hl), d
inc hl
; check end
ld a, h
cp 0x80
jr NZ, loop_vm
ld a, c
inc c
cp 16
jr NZ, loop_seg
; disable window on RAM1
in a, (_p0a_mem_man)
res MEMM_RAM1EN_BIT, a
nop
out (_p0a_mem_man), a
jp main
set_turbo:
in a, (_p0a_mem_man)
res MEMM_TURBO_BIT, a
bit CONFIG_TURBO_BIT, b
jr Z, turbo_not_set
set MEMM_TURBO_BIT, a
turbo_not_set:
out (_p0a_mem_man), a
jp main_turbo
set_vbank:
bit CONFIG_WIDE_BIT, b
jr NZ, wide_not_set
set VB_WIDE_BIT, a
wide_not_set:
out (_pfa_vbank), a
jp main_vbank
VMODE_2COLOR_1PALLETE = 0x00
VMODE_2COLOR_2PALLETE = 0x01
VMODE_4COLOR_1PALLETE = 0x04
VMODE_4COLOR_2PALLETE = 0x05
VMODE_16COLOR_GROUP = 0x06
VMODE_16COLOR_PALLET = 0x0e
VMODE_3BIT = 0x10
VMODE_4BIT = 0x14
VIDEO_TEST_0_TITLE:
.db "TEST: 2 colors, pallete 1 ", 0x00
VIDEO_TEST_1_TITLE:
.db "TEST: 2 colors, pallete 2 ", 0x00
VIDEO_TEST_2_TITLE:
.db "TEST: 4 colors, pallete 1 ", 0x00
VIDEO_TEST_3_TITLE:
.db "TEST: 4 colors, pallete 2 ", 0x00
VIDEO_TEST_4_TITLE:
.db "TEST: 16 colors, group ", 0x00
VIDEO_TEST_5_TITLE:
.db "TEST: 16 colors, pallete (port 0xFC)", 0x00
VIDEO_TEST_6_TITLE:
.db "TEST: 3bit colors ", 0x00
VIDEO_TEST_7_TITLE:
.db "TEST: 4bit colors ", 0x00
test_2colors_pallet1:
ld a, VMODE_2COLOR_1PALLETE
out (_pf8_vmode), a
jp fill_scr_1
test_2colors_pallet1_end:
ld de, VIDEO_TEST_0_TITLE
ld iyh, 0
ld iyl, 29
ld hl, main_video_end
jp print_str
test_2colors_pallet2:
ld a, VMODE_2COLOR_2PALLETE
out (_pf8_vmode), a
jp fill_scr_1
test_2colors_pallet2_end:
ld de, VIDEO_TEST_1_TITLE
ld iyh, 0
ld iyl, 29
ld hl, main_video_end
jp print_str
test_4colors_pallet1:
ld a, VMODE_4COLOR_1PALLETE
out (_pf8_vmode), a
jp fill_scr_1
test_4colors_pallet1_end:
jp fill_scr_2_4c
test_4colors_pallet1_end2:
ld de, VIDEO_TEST_2_TITLE
ld iyh, 0
ld iyl, 29
ld hl, main_video_end
jp print_str
test_4colors_pallet2:
ld a, VMODE_4COLOR_2PALLETE
out (_pf8_vmode), a
jp fill_scr_1
test_4colors_pallet2_end:
jp fill_scr_2_4c
test_4colors_pallet2_end2:
ld de, VIDEO_TEST_3_TITLE
ld iyh, 0
ld iyl, 29
ld hl, main_video_end
jp print_str
test_16colors_group:
ld a, VMODE_16COLOR_GROUP
out (_pf8_vmode), a
jp fill_scr_1
test_16colors_group_end:
jp fill_scr_2_16c
test_16colors_group_end2:
ld de, VIDEO_TEST_4_TITLE
ld iyh, 0
ld iyl, 29
ld hl, main_video_end
jp print_str
test_16colors_pallet:
ld a, VMODE_16COLOR_PALLET
out (_pf8_vmode), a
jp fill_scr_1
test_16colors_pallet_end:
ld a, TEST_16C_PALLETE
out (_pfc_color_reg), a
test_16colors_pallet_end2:
ld de, VIDEO_TEST_5_TITLE
ld iyh, 0
ld iyl, 29
ld hl, main_video_end
jp print_str
test_3bit:
ld a, VMODE_3BIT
out (_pf8_vmode), a
jp fill_scr_1
test_3bit_end:
jp fill_scr_blue
test_3bit_end3:
jp fill_scr_red
test_3bit_end4:
ld de, VIDEO_TEST_6_TITLE
ld iyh, 0
ld iyl, 29
ld hl, main_video_end
jp print_str
test_4bit:
ld a, VMODE_4BIT
out (_pf8_vmode), a
jp fill_scr_1
test_4bit_end:
; fill I
jp fill_scr_2_4c
test_4bit_end2:
jp fill_scr_blue
test_4bit_end3:
jp fill_scr_red
test_4bit_end4:
ld de, VIDEO_TEST_7_TITLE
ld iyh, 0
ld iyl, 29
ld hl, main_video_end
jp print_str
test_ret_table:
.DW test_2colors_pallet1_end
.DW test_2colors_pallet2_end
.DW test_4colors_pallet1_end
.DW test_4colors_pallet2_end
.DW test_16colors_group_end
.DW test_16colors_pallet_end
.DW test_3bit_end
.DW test_4bit_end
fill_scr_1:
; usage:
; hl - screen pointer
; de - temp
ld hl, VBANK_START
loop_f1_col:
ld l, 0
loop_f1_row:
ld (hl), 0xff
inc hl
ld (hl), 0x81
inc hl
ld (hl), 0x81
inc hl
ld (hl), 0x81
inc hl
ld (hl), 0x81
inc hl
ld (hl), 0x81
inc hl
ld (hl), 0x81
inc hl
ld (hl), 0xff
inc hl
; check column end
ld a, l
cp 0xe0
jr C, loop_f1_row
ld de, 0x0020
ld a, h
add hl, de
; check row end
cp 0xff
jr NZ, loop_f1_col
; print column numbers
ld d, 0
ld hl, 0 ; h=*10 , l=*1
fill1_nbrs:
ld a, l
add a, '0'
ld iyh, d
ld iyl, 31
ld ix, fill1_enbrs1
jp print_chr
fill1_enbrs1:
ld a, h
add a, '0'
ld iyh, d
ld iyl, 30
ld ix, fill1_enbrs2
jp print_chr
fill1_enbrs2:
inc l
ld a, l
cp 10
jr C, fill1_nnbrs
inc h
ld l, 0
fill1_nnbrs:
inc d
ld a, d
cp 64
jr C, fill1_nbrs
fill1_end:
; return to test
ld a, b ; load configuration to A
and 0x07 ; extract video test number
ld h, 0
ld l, a
add hl, hl
ld de, test_ret_table
add hl, de
ld a, (hl)
inc hl
ld h, (hl)
ld l, a
jp (hl)
test_ret_table_2:
.DW 0
.DW 0
.DW test_4colors_pallet1_end2
.DW test_4colors_pallet2_end2
.DW test_16colors_group_end2
.DW 0
.DW 0
.DW test_4bit_end2
fill_scr_2_4c:
; enable window on RAM1
in a, (_p0a_mem_man)
set MEMM_RAM1EN_BIT, a
out (_p0a_mem_man), a
; set RAM 1 to segment #7
ld a, 7
out (_p05_RAM1), a
; screen pointer
ld hl, RAM1_WINDOW
ld d, 0 ; columns
fill2_row:
; col N
ld a, 0
fill2_sr1:
ld (hl), 0xff
inc hl
inc a
cp 0xe0
jr C, fill2_sr1
; skip 4 rows
ld a, d
ld de, 0x0020
add hl, de
ld d, a
; col N+1
ld a, 0
fill2_sr2:
ld (hl), 0x00
inc hl
inc a
cp 0xe0
jr C, fill2_sr2
; skip 4 rows
ld a, d
ld de, 0x0020
add hl, de
ld d, a
; decrease columns counter
inc d
ld a, d
cp 32
jr C, fill2_row
fill2_end:
; disable window on RAM1
in a, (_p0a_mem_man)
res MEMM_RAM1EN_BIT, a
out (_p0a_mem_man), a
; return to test
ld a, b ; load configuration to A
and 0x07 ; extract video test number
ld h, 0
ld l, a
add hl, hl
ld de, test_ret_table_2
add hl, de
ld a, (hl)
inc hl
ld h, (hl)
ld l, a
jp (hl)
fill_scr_2_16c:
; enable window on RAM1
in a, (_p0a_mem_man)
set MEMM_RAM1EN_BIT, a
out (_p0a_mem_man), a
; set RAM 1 to segment #7
ld a, 7
out (_p05_RAM1), a
; screen pointer
ld hl, RAM1_WINDOW
ld d, 0 ; columns
fill3_row:
; calculate fill value
ld a, d
and 0x0f
sla a
sla a
sla a
sla a
ld e, a
ld c, 0
; rows main
fill3_sr1:
ld a, c
and 0x0f
add a, e
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
inc c
ld a, c
cp 0x1c
jr C, fill3_sr1
; rows titles
;ld a, d
;and 0x0f
;jr NZ, fill3_nz
ld a, 1
fill3_nz:
ld e, a
ld a, 0
fill3_sr2:
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
inc a
cp 0x4
jr C, fill3_sr2
; decrease columns counter
inc d
ld a, d
cp 64
jr C, fill3_row
fill3_end:
; disable window on RAM1
in a, (_p0a_mem_man)
res MEMM_RAM1EN_BIT, a
out (_p0a_mem_man), a
; return to test
ld a, b ; load configuration to A
and 0x07 ; extract video test number
ld h, 0
ld l, a
add hl, hl
ld de, test_ret_table_2
add hl, de
ld a, (hl)
inc hl
ld h, (hl)
ld l, a
jp (hl)
test_ret_table_3:
.DW 0
.DW 0
.DW 0
.DW 0
.DW 0
.DW 0
.DW test_3bit_end3
.DW test_4bit_end3
fill_scr_blue:
; enable window on RAM1
in a, (_p0a_mem_man)
set MEMM_RAM1EN_BIT, a
out (_p0a_mem_man), a
; set RAM 1 to segment #6
ld a, 6
out (_p05_RAM1), a
; screen pointer
ld hl, RAM1_WINDOW
ld d, 0 ; columns
fill4_row:
ld c, 0
; rows main
fill4_sr1:
ld a, l
and 0x08
cp 0x08
jr C, fill4_ff
ld a, 0x00
jp fill4_st
fill4_ff:
ld a, 0xff
fill4_st:
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
inc c
ld a, c
cp 0x1c
jr C, fill4_sr1
; rows titles
;ld a, d
;and 0x0f
;jr NZ, fill3_nz
ld a, 1
fill4_nz:
ld e, 0
ld a, 0
fill4_sr2:
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
inc a
cp 0x4
jr C, fill4_sr2
; decrease columns counter
inc d
ld a, d
cp 64
jr C, fill4_row
fill4_end:
; disable window on RAM1
in a, (_p0a_mem_man)
res MEMM_RAM1EN_BIT, a
out (_p0a_mem_man), a
; return to test
ld a, b ; load configuration to A
and 0x07 ; extract video test number
ld h, 0
ld l, a
add hl, hl
ld de, test_ret_table_3
add hl, de
ld a, (hl)
inc hl
ld h, (hl)
ld l, a
jp (hl)
test_ret_table_4:
.DW 0
.DW 0
.DW 0
.DW 0
.DW 0
.DW 0
.DW test_3bit_end4
.DW test_4bit_end4
fill_scr_red:
; enable window on RAM1
in a, (_p0a_mem_man)
set MEMM_RAM1EN_BIT, a
out (_p0a_mem_man), a
; set RAM 1 to segment #2
ld a, 2
out (_p05_RAM1), a
; screen pointer
ld hl, RAM1_WINDOW
ld d, 0 ; columns
fill5_row:
ld c, 0
; rows main
fill5_sr1:
ld a, l
and 0x10
cp 0x10
jr C, fill5_ff
ld a, 0x00
jp fill5_st
fill5_ff:
ld a, 0xff
fill5_st:
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
ld (hl), a
inc hl
inc c
ld a, c
cp 0x1c
jr C, fill5_sr1
; rows titles
;ld a, d
;and 0x0f
;jr NZ, fill3_nz
ld a, 1
fill5_nz:
ld e, 0
ld a, 0
fill5_sr2:
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
ld (hl), e
inc hl
inc a
cp 0x4
jr C, fill5_sr2
; decrease columns counter
inc d
ld a, d
cp 64
jr C, fill5_row
fill5_end:
; disable window on RAM1
in a, (_p0a_mem_man)
res MEMM_RAM1EN_BIT, a
out (_p0a_mem_man), a
; return to test
ld a, b ; load configuration to A
and 0x07 ; extract video test number
ld h, 0
ld l, a
add hl, hl
ld de, test_ret_table_4
add hl, de
ld a, (hl)
inc hl
ld h, (hl)
ld l, a
jp (hl)
print_chr:
; parameters:
; A - char
; iyh - column
; iyl - row
; ix - return address
; usage:
; shadow registers
exx
; get character start
ld de, font
ld h, 0
ld l, a
add hl, hl ; *2
add hl, hl ; *2
add hl, hl ; *2
add hl, de
; calculate screen start
ld a, iyl ;28
add a, a ; *2
add a, a ; *2
add a, a ; *2
ld e, a
ld a, iyh ;0
add a, 0xc0
ld d, a
; set count
ld bc, 0x0008
ldir
exx
jp ix
print_str:
; parameters:
; de - string start (ZERO-ended)
; iyh - column
; iyl - row
; hl - return address
ld ix, print_str_add
print_str_loop:
ld a, (de)
cp 0
jr Z, print_str_exit
inc de
jp print_chr
print_str_add:
inc iyh
jr print_str_loop
print_str_exit:
jp hl
font:
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 0
.db 0x00, 0x3E, 0x41, 0x55, 0x41, 0x55, 0x49, 0x3E // 1
.db 0x00, 0x3E, 0x7F, 0x6B, 0x7F, 0x6B, 0x77, 0x3E // 2
.db 0x00, 0x22, 0x77, 0x7F, 0x7F, 0x3E, 0x1C, 0x08 // 3
.db 0x00, 0x08, 0x1C, 0x3E, 0x7F, 0x3E, 0x1C, 0x08 // 4
.db 0x00, 0x08, 0x1C, 0x2A, 0x7F, 0x2A, 0x08, 0x1C // 5
.db 0x00, 0x08, 0x1C, 0x3E, 0x7F, 0x3E, 0x08, 0x1C // 6
.db 0x00, 0x00, 0x1C, 0x3E, 0x3E, 0x3E, 0x1C, 0x00 // 7
.db 0xFF, 0xFF, 0xE3, 0xC1, 0xC1, 0xC1, 0xE3, 0xFF // 8
.db 0x00, 0x00, 0x1C, 0x22, 0x22, 0x22, 0x1C, 0x00 // 9
.db 0xFF, 0xFF, 0xE3, 0xDD, 0xDD, 0xDD, 0xE3, 0xFF // a
.db 0x00, 0x0F, 0x03, 0x05, 0x39, 0x48, 0x48, 0x30 // b
.db 0x00, 0x08, 0x3E, 0x08, 0x1C, 0x22, 0x22, 0x1C // c
.db 0x00, 0x18, 0x14, 0x10, 0x10, 0x30, 0x70, 0x60 // d
.db 0x00, 0x0F, 0x19, 0x11, 0x13, 0x37, 0x76, 0x60 // e
.db 0x00, 0x08, 0x2A, 0x1C, 0x77, 0x1C, 0x2A, 0x08 // f
.db 0x00, 0x60, 0x78, 0x7E, 0x7F, 0x7E, 0x78, 0x60 // 10
.db 0x00, 0x03, 0x0F, 0x3F, 0x7F, 0x3F, 0x0F, 0x03 // 11
.db 0x00, 0x08, 0x1C, 0x2A, 0x08, 0x2A, 0x1C, 0x08 // 12
.db 0x00, 0x66, 0x66, 0x66, 0x66, 0x00, 0x66, 0x66 // 13
.db 0x00, 0x3F, 0x65, 0x65, 0x3D, 0x05, 0x05, 0x05 // 14
.db 0x00, 0x0C, 0x32, 0x48, 0x24, 0x12, 0x4C, 0x30 // 15
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x7F, 0x7F // 16
.db 0x00, 0x08, 0x1C, 0x2A, 0x08, 0x2A, 0x1C, 0x3E // 17
.db 0x00, 0x08, 0x1C, 0x3E, 0x7F, 0x1C, 0x1C, 0x1C // 18
.db 0x00, 0x1C, 0x1C, 0x1C, 0x7F, 0x3E, 0x1C, 0x08 // 19
.db 0x00, 0x08, 0x0C, 0x7E, 0x7F, 0x7E, 0x0C, 0x08 // 1a
.db 0x00, 0x08, 0x18, 0x3F, 0x7F, 0x3F, 0x18, 0x08 // 1b
.db 0x00, 0x00, 0x00, 0x70, 0x70, 0x70, 0x7F, 0x7F // 1c
.db 0x00, 0x00, 0x14, 0x22, 0x7F, 0x22, 0x14, 0x00 // 1d
.db 0x00, 0x08, 0x1C, 0x1C, 0x3E, 0x3E, 0x7F, 0x7F // 1e
.db 0x00, 0x7F, 0x7F, 0x3E, 0x3E, 0x1C, 0x1C, 0x08 // 1f
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 20
.db 0x00, 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18 // 21
.db 0x00, 0x36, 0x36, 0x14, 0x00, 0x00, 0x00, 0x00 // 22
.db 0x00, 0x36, 0x36, 0x7F, 0x36, 0x7F, 0x36, 0x36 // 23
.db 0x00, 0x08, 0x1E, 0x20, 0x1C, 0x02, 0x3C, 0x08 // 24
.db 0x00, 0x60, 0x66, 0x0C, 0x18, 0x30, 0x66, 0x06 // 25
.db 0x00, 0x3C, 0x66, 0x3C, 0x28, 0x65, 0x66, 0x3F // 26
.db 0x00, 0x18, 0x18, 0x18, 0x30, 0x00, 0x00, 0x00 // 27
.db 0x00, 0x06, 0x0C, 0x18, 0x18, 0x18, 0x0C, 0x06 //
.db 0x00, 0x60, 0x30, 0x18, 0x18, 0x18, 0x30, 0x60 //
.db 0x00, 0x00, 0x36, 0x1C, 0x7F, 0x1C, 0x36, 0x00
.db 0x00, 0x00, 0x08, 0x08, 0x3E, 0x08, 0x08, 0x00
.db 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x60
.db 0x00, 0x00, 0x00, 0x00, 0x3C, 0x00, 0x00, 0x00
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x60
.db 0x00, 0x00, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x00
.db 0x00, 0x3C, 0x66, 0x6E, 0x76, 0x66, 0x66, 0x3C
.db 0x00, 0x18, 0x18, 0x38, 0x18, 0x18, 0x18, 0x7E
.db 0x00, 0x3C, 0x66, 0x06, 0x0C, 0x30, 0x60, 0x7E
.db 0x00, 0x3C, 0x66, 0x06, 0x1C, 0x06, 0x66, 0x3C
.db 0x00, 0x0C, 0x1C, 0x2C, 0x4C, 0x7E, 0x0C, 0x0C
.db 0x00, 0x7E, 0x60, 0x7C, 0x06, 0x06, 0x66, 0x3C
.db 0x00, 0x3C, 0x66, 0x60, 0x7C, 0x66, 0x66, 0x3C
.db 0x00, 0x7E, 0x66, 0x0C, 0x0C, 0x18, 0x18, 0x18
.db 0x00, 0x3C, 0x66, 0x66, 0x3C, 0x66, 0x66, 0x3C
.db 0x00, 0x3C, 0x66, 0x66, 0x3E, 0x06, 0x66, 0x3C
.db 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00
.db 0x00, 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x30
.db 0x00, 0x06, 0x0C, 0x18, 0x30, 0x18, 0x0C, 0x06
.db 0x00, 0x00, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x00
.db 0x00, 0x60, 0x30, 0x18, 0x0C, 0x18, 0x30, 0x60
.db 0x00, 0x3C, 0x66, 0x06, 0x1C, 0x18, 0x00, 0x18
.db 0x00, 0x38, 0x44, 0x5C, 0x58, 0x42, 0x3C, 0x00
.db 0x00, 0x3C, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66
.db 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x66, 0x66, 0x7C
.db 0x00, 0x3C, 0x66, 0x60, 0x60, 0x60, 0x66, 0x3C
.db 0x00, 0x7C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x7C
.db 0x00, 0x7E, 0x60, 0x60, 0x7C, 0x60, 0x60, 0x7E
.db 0x00, 0x7E, 0x60, 0x60, 0x7C, 0x60, 0x60, 0x60
.db 0x00, 0x3C, 0x66, 0x60, 0x60, 0x6E, 0x66, 0x3C
.db 0x00, 0x66, 0x66, 0x66, 0x7E, 0x66, 0x66, 0x66
.db 0x00, 0x3C, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3C
.db 0x00, 0x1E, 0x0C, 0x0C, 0x0C, 0x6C, 0x6C, 0x38
.db 0x00, 0x66, 0x6C, 0x78, 0x70, 0x78, 0x6C, 0x66
.db 0x00, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x7E
.db 0x00, 0x63, 0x77, 0x7F, 0x6B, 0x63, 0x63, 0x63
.db 0x00, 0x63, 0x73, 0x7B, 0x6F, 0x67, 0x63, 0x63
.db 0x00, 0x3C, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C
.db 0x00, 0x7C, 0x66, 0x66, 0x66, 0x7C, 0x60, 0x60
.db 0x00, 0x3C, 0x66, 0x66, 0x66, 0x6E, 0x3C, 0x06
.db 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x78, 0x6C, 0x66
.db 0x00, 0x3C, 0x66, 0x60, 0x3C, 0x06, 0x66, 0x3C
.db 0x00, 0x7E, 0x5A, 0x18, 0x18, 0x18, 0x18, 0x18
.db 0x00, 0x66, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3E
.db 0x00, 0x66, 0x66, 0x66, 0x66, 0x66, 0x3C, 0x18
.db 0x00, 0x63, 0x63, 0x63, 0x6B, 0x7F, 0x77, 0x63
.db 0x00, 0x63, 0x63, 0x36, 0x1C, 0x36, 0x63, 0x63
.db 0x00, 0x66, 0x66, 0x66, 0x3C, 0x18, 0x18, 0x18
.db 0x00, 0x7E, 0x06, 0x0C, 0x18, 0x30, 0x60, 0x7E
.db 0x00, 0x1E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x1E
.db 0x00, 0x00, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x00
.db 0x00, 0x78, 0x18, 0x18, 0x18, 0x18, 0x18, 0x78
.db 0x00, 0x08, 0x14, 0x22, 0x41, 0x00, 0x00, 0x00
.db 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F
.db 0x00, 0x0C, 0x0C, 0x06, 0x00, 0x00, 0x00, 0x00
.db 0x00, 0x00, 0x00, 0x3C, 0x06, 0x3E, 0x66, 0x3E
.db 0x00, 0x60, 0x60, 0x60, 0x7C, 0x66, 0x66, 0x7C
.db 0x00, 0x00, 0x00, 0x3C, 0x66, 0x60, 0x66, 0x3C
.db 0x00, 0x06, 0x06, 0x06, 0x3E, 0x66, 0x66, 0x3E
.db 0x00, 0x00, 0x00, 0x3C, 0x66, 0x7E, 0x60, 0x3C
.db 0x00, 0x1C, 0x36, 0x30, 0x30, 0x7C, 0x30, 0x30
.db 0x00, 0x00, 0x3E, 0x66, 0x66, 0x3E, 0x06, 0x3C
.db 0x00, 0x60, 0x60, 0x60, 0x7C, 0x66, 0x66, 0x66
.db 0x00, 0x00, 0x18, 0x00, 0x18, 0x18, 0x18, 0x3C
.db 0x00, 0x0C, 0x00, 0x0C, 0x0C, 0x6C, 0x6C, 0x38
.db 0x00, 0x60, 0x60, 0x66, 0x6C, 0x78, 0x6C, 0x66
.db 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18
.db 0x00, 0x00, 0x00, 0x63, 0x77, 0x7F, 0x6B, 0x6B
.db 0x00, 0x00, 0x00, 0x7C, 0x7E, 0x66, 0x66, 0x66
.db 0x00, 0x00, 0x00, 0x3C, 0x66, 0x66, 0x66, 0x3C
.db 0x00, 0x00, 0x7C, 0x66, 0x66, 0x7C, 0x60, 0x60
.db 0x00, 0x00, 0x3C, 0x6C, 0x6C, 0x3C, 0x0D, 0x0F
.db 0x00, 0x00, 0x00, 0x7C, 0x66, 0x66, 0x60, 0x60
.db 0x00, 0x00, 0x00, 0x3E, 0x40, 0x3C, 0x02, 0x7C
.db 0x00, 0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x18
.db 0x00, 0x00, 0x00, 0x66, 0x66, 0x66, 0x66, 0x3E
.db 0x00, 0x00, 0x00, 0x00, 0x66, 0x66, 0x3C, 0x18
.db 0x00, 0x00, 0x00, 0x63, 0x6B, 0x6B, 0x6B, 0x3E
.db 0x00, 0x00, 0x00, 0x66, 0x3C, 0x18, 0x3C, 0x66
.db 0x00, 0x00, 0x00, 0x66, 0x66, 0x3E, 0x06, 0x3C
.db 0x00, 0x00, 0x00, 0x3C, 0x0C, 0x18, 0x30, 0x3C
.db 0x00, 0x0E, 0x18, 0x18, 0x30, 0x18, 0x18, 0x0E
.db 0x00, 0x18, 0x18, 0x18, 0x00, 0x18, 0x18, 0x18
.db 0x00, 0x70, 0x18, 0x18, 0x0C, 0x18, 0x18, 0x70
.db 0x00, 0x00, 0x00, 0x3A, 0x6C, 0x00, 0x00, 0x00
.db 0x00, 0x08, 0x1C, 0x36, 0x63, 0x41, 0x41, 0x7F

BIN
work_dir/ROMs/test.bin Normal file
View File

Binary file not shown.

151
work_dir/ROMs/test.hex Normal file
View File

@ -0,0 +1,151 @@
@00000000
31 FF 3F 3E 98 D3 03 3E 80 D3 07 3E 80 D3 0B 3E
92 D3 1D 3E 16 D3 3B 3E 56 D3 3B 3E 96 D3 3B 3E
10 D3 0A 3E 00 D3 F8 C3 BD 00 DB 00 47 C3 E4 00
3E 00 C3 F3 00 CB 68 20 55 78 E6 07 26 00 6F 29
11 AD 00 19 7E 23 66 6F E9 11 6B 00 FD 26 00 FD
2E 1C 21 58 00 C3 4D 05 16 00 14 21 00 00 23 7C
D6 80 38 FA 7A D6 04 38 F1 18 BF 4F 52 49 4F 4E
2D 31 32 38 20 4E 47 20 74 65 73 74 73 20 28 61
6E 64 72 65 69 6C 2C 20 32 30 32 30 29 00 3E 00
D3 F8 3E 00 D3 FA DB 0A CB EF D3 0A 11 6B 00 FD
26 00 FD 2E 1F 21 58 00 C3 4D 05 18 EF 26 02 3C
02 52 02 6B 02 84 02 9D 02 B7 02 D3 02 DB 0A CB
CF D3 0A 0E 00 79 D3 05 21 00 40 16 00 72 23 7C
FE 80 20 F9 79 0C FE 10 20 EB DB 0A CB 8F 00 D3
0A C3 2A 00 DB 0A CB AF CB 58 28 02 CB EF D3 0A
C3 30 00 CB 60 20 02 CB FF D3 FA C3 35 00 54 45
53 54 3A 20 32 20 63 6F 6C 6F 72 73 2C 20 70 61
6C 6C 65 74 65 20 31 20 20 20 20 20 20 20 20 20
20 20 00 54 45 53 54 3A 20 32 20 63 6F 6C 6F 72
73 2C 20 70 61 6C 6C 65 74 65 20 32 20 20 20 20
20 20 20 20 20 20 20 00 54 45 53 54 3A 20 34 20
63 6F 6C 6F 72 73 2C 20 70 61 6C 6C 65 74 65 20
31 20 20 20 20 20 20 20 20 20 20 20 00 54 45 53
54 3A 20 34 20 63 6F 6C 6F 72 73 2C 20 70 61 6C
6C 65 74 65 20 32 20 20 20 20 20 20 20 20 20 20
20 00 54 45 53 54 3A 20 31 36 20 63 6F 6C 6F 72
73 2C 20 67 72 6F 75 70 20 20 20 20 20 20 20 20
20 20 20 20 20 20 00 54 45 53 54 3A 20 31 36 20
63 6F 6C 6F 72 73 2C 20 70 61 6C 6C 65 74 65 20
28 70 6F 72 74 20 30 78 46 43 29 00 54 45 53 54
3A 20 33 62 69 74 20 63 6F 6C 6F 72 73 20 20 20
20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
00 54 45 53 54 3A 20 34 62 69 74 20 63 6F 6C 6F
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1115
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21 4F F9 FD 21 C9 FD 18 EA D9 7A D9 06 30 0E 08
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