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https://github.com/andreili/klipper.git
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b1361d9e5b
Implement the usbfs fast buffer switching mechanism on the "bulk out" endpoint. This can improve the overall USB throughput and bus utilization. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
404 lines
12 KiB
C
404 lines
12 KiB
C
// Hardware interface to "fullspeed USB controller"
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//
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// Copyright (C) 2018-2023 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <string.h> // NULL
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#include "board/armcm_boot.h" // armcm_enable_irq
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#include "board/armcm_timer.h" // udelay
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#include "board/gpio.h" // gpio_out_setup
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#include "board/io.h" // writeb
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#include "board/usb_cdc.h" // usb_notify_ep0
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#include "board/usb_cdc_ep.h" // USB_CDC_EP_BULK_IN
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // GPIO
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#include "sched.h" // DECL_INIT
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#if CONFIG_MACH_STM32F1 || CONFIG_MACH_STM32G4
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// Transfer memory is accessed with 32bits, but contains only 16bits of data
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typedef volatile uint32_t epmword_t;
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#define WSIZE 2
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#define USBx_IRQn USB_LP_IRQn
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#elif CONFIG_MACH_STM32F0 || CONFIG_MACH_STM32L4
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// Transfer memory is accessed with 16bits and contains 16bits of data
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typedef volatile uint16_t epmword_t;
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#define WSIZE 2
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#define USBx_IRQn USB_IRQn
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#elif CONFIG_MACH_STM32G0
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// Transfer memory is accessed with 32bits and contains 32bits of data
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typedef volatile uint32_t epmword_t;
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#define WSIZE 4
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#define USBx_IRQn USB_IRQn
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#endif
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// The stm32g0 has slightly different register names
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#if CONFIG_MACH_STM32G0
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#if CONFIG_MACH_STM32G0B1
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#define USB_IRQn USB_UCPD1_2_IRQn
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#endif
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#define USB USB_DRD_FS
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#define USB_PMAADDR USB_DRD_PMAADDR
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#define USB_EPADDR_FIELD USB_CHEP_ADDR
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#define USB_EP_CTR_RX USB_EP_VTRX
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#define USB_EP_CTR_TX USB_EP_VTTX
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#define USB_EPRX_STAT USB_EP_RX_STRX
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#define USB_EPTX_STAT USB_EP_TX_STTX
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#define USB_ISTR_EP_ID USB_ISTR_IDN
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#define USB_CNTR_FRES USB_CNTR_USBRST
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#endif
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// Some chip variants do not define these fields
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#ifndef USB_EP_DTOG_TX_Pos
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#define USB_EP_DTOG_TX_Pos 6
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#define USB_EP_DTOG_RX_Pos 14
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#endif
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/****************************************************************
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* USB transfer memory
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****************************************************************/
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// Layout of the USB transfer memory
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#define EPM ((epmword_t*)USB_PMAADDR)
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#define EPM_EP_DESC(ep, bufnum) (&EPM[((ep)*2 + (bufnum)) * (4 / WSIZE)])
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#define EPM_BUF_OFFSET 0x10
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#define EPM_EP_BUF_SIZE (64 / WSIZE + 1)
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#define EPM_EP_BUF(ep, bufnum) \
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(&EPM[EPM_BUF_OFFSET + ((ep)*2 + (bufnum)) * EPM_EP_BUF_SIZE])
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#define BUFTX 0
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#define BUFRX 1
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// Configure the usb descriptor for an endpoint
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static void
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epm_ep_desc_setup(int ep, int bufnum, int rx_size)
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{
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uint32_t addr = (EPM_EP_BUF(ep, bufnum) - EPM) * WSIZE;
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uint32_t count_rx = (rx_size <= 30 ? DIV_ROUND_UP(rx_size, 2) << 10
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: ((DIV_ROUND_UP(rx_size, 32) - 1) << 10) | 0x8000);
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epmword_t *desc = EPM_EP_DESC(ep, bufnum);
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if (WSIZE == 2) {
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desc[0] = addr;
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desc[1] = count_rx;
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} else {
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*desc = addr | (count_rx << 16);
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}
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}
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// Return number of read bytes on an rx endpoint
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static uint32_t
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epm_get_ep_count_rx(int ep, int bufnum)
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{
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epmword_t *desc = EPM_EP_DESC(ep, bufnum);
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if (WSIZE == 2)
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return desc[1] & 0x3ff;
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return (*desc >> 16) & 0x3ff;
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}
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// Set number of bytes ready to be transmitted on a tx endpoint
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static void
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epm_set_ep_count_tx(int ep, int bufnum, uint32_t count)
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{
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epmword_t *desc = EPM_EP_DESC(ep, bufnum);
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if (WSIZE == 2) {
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desc[1] = count;
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} else {
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uint32_t addr_tx = (EPM_EP_BUF(ep, bufnum) - EPM) * WSIZE;
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*desc = addr_tx | (count << 16);
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}
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}
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// Setup the transfer descriptors in dedicated usb memory
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static void
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btable_configure(void)
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{
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epm_ep_desc_setup(0, BUFTX, 0);
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epm_ep_desc_setup(0, BUFRX, USB_CDC_EP0_SIZE);
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epm_ep_desc_setup(USB_CDC_EP_ACM, BUFTX, 0);
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epm_ep_desc_setup(USB_CDC_EP_ACM, BUFRX, 0);
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epm_ep_desc_setup(USB_CDC_EP_BULK_OUT, 0, USB_CDC_EP_BULK_OUT_SIZE);
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epm_ep_desc_setup(USB_CDC_EP_BULK_OUT, 1, USB_CDC_EP_BULK_OUT_SIZE);
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epm_ep_desc_setup(USB_CDC_EP_BULK_IN, BUFTX, 0);
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epm_ep_desc_setup(USB_CDC_EP_BULK_IN, BUFRX, 0);
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}
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// Read a packet stored in dedicated usb memory
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static uint32_t
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btable_read_packet(int ep, int bufnum, uint8_t *dest, int max_len)
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{
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epmword_t *src = EPM_EP_BUF(ep, bufnum);
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uint32_t count = epm_get_ep_count_rx(ep, bufnum);
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if (count > max_len)
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count = max_len;
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int i;
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for (i=0; i<count/WSIZE; i++) {
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uint32_t d = *src++;
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*dest++ = d;
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*dest++ = d >> 8;
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if (WSIZE == 4) {
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*dest++ = d >> 16;
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*dest++ = d >> 24;
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}
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}
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if (count & (WSIZE-1)) {
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uint32_t d = *src;
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*dest++ = d;
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if ((count & (WSIZE-1)) > 1)
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*dest++ = d >> 8;
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if ((count & (WSIZE-1)) > 2)
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*dest++ = d >> 16;
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}
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return count;
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}
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// Write a packet to dedicated usb memory
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static void
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btable_write_packet(int ep, int bufnum, const uint8_t *src, int count)
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{
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epmword_t *dest = EPM_EP_BUF(ep, bufnum);
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int i;
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for (i=0; i<count/WSIZE; i++) {
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uint8_t b1 = *src++, b2 = *src++, b3 = 0, b4 = 0;
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if (WSIZE == 4) {
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b3 = *src++;
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b4 = *src++;
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}
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*dest++ = b1 | (b2 << 8) | (b3 << 16) | (b4 << 24);
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}
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if (count & (WSIZE-1)) {
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uint32_t d = *src++;
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if ((count & (WSIZE-1)) > 1)
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d |= *src++ << 8;
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if ((count & (WSIZE-1)) > 2)
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d |= *src++ << 16;
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*dest = d;
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}
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epm_set_ep_count_tx(ep, bufnum, count);
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}
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/****************************************************************
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* USB endpoint register
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****************************************************************/
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#define USB_EPR ((volatile uint32_t *)USB_BASE)
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#define EPR_TBITS (USB_EP_DTOG_RX | USB_EPRX_STAT \
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| USB_EP_DTOG_TX | USB_EPTX_STAT)
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#define EPR_RWBITS (USB_EPADDR_FIELD | USB_EP_KIND | USB_EP_TYPE_MASK)
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#define EPR_RWCBITS (USB_EP_CTR_RX | USB_EP_CTR_TX)
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// Calculate the memory update needed to set the epr register
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static uint32_t
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calc_epr_bits(uint32_t epr, uint32_t mask, uint32_t value)
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{
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uint32_t tmask = mask & EPR_TBITS, tvalue = value & tmask;
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uint32_t rwmask = mask & EPR_RWBITS, rwbits = value & rwmask;
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uint32_t cbits = EPR_RWCBITS & ~mask;
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return (((epr & (EPR_RWBITS | tmask)) ^ tvalue) & ~rwmask) | rwbits | cbits;
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}
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// Check if double buffering endpoint hardware can no longer send/receive
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static int
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epr_is_dbuf_blocking(uint32_t epr)
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{
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return !(((epr >> (USB_EP_DTOG_RX_Pos - USB_EP_DTOG_TX_Pos)) ^ epr)
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& USB_EP_DTOG_TX);
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}
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/****************************************************************
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* USB interface
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****************************************************************/
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static uint32_t bulk_out_pop_count, bulk_out_push_flag;
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int_fast8_t
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usb_read_bulk_out(void *data, uint_fast8_t max_len)
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{
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if (readl(&bulk_out_push_flag))
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// No data ready
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return -1;
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uint32_t ep = USB_CDC_EP_BULK_OUT;
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int bufnum = bulk_out_pop_count & 1;
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bulk_out_pop_count++;
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uint32_t count = btable_read_packet(ep, bufnum, data, max_len);
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writel(&bulk_out_push_flag, USB_EP_DTOG_TX);
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// Check if irq handler pulled another packet before push flag update
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uint32_t epr = USB_EPR[ep];
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if (epr_is_dbuf_blocking(epr) && readl(&bulk_out_push_flag)) {
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// Second packet was already read - must notify hardware
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writel(&bulk_out_push_flag, 0);
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USB_EPR[ep] = calc_epr_bits(epr, 0, 0) | USB_EP_DTOG_TX;
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}
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return count;
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}
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int_fast8_t
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usb_send_bulk_in(void *data, uint_fast8_t len)
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{
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uint32_t ep = USB_CDC_EP_BULK_IN, epr = USB_EPR[ep];
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if ((epr & USB_EPTX_STAT) != USB_EP_TX_NAK)
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// No buffer space available
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return -1;
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btable_write_packet(ep, BUFTX, data, len);
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USB_EPR[ep] = calc_epr_bits(epr, USB_EPTX_STAT, USB_EP_TX_VALID);
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return len;
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}
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int_fast8_t
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usb_read_ep0(void *data, uint_fast8_t max_len)
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{
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uint32_t ep = 0, epr = USB_EPR[ep];
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if ((epr & USB_EPRX_STAT) != USB_EP_RX_NAK)
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// No data ready
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return -1;
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uint32_t count = btable_read_packet(ep, BUFRX, data, max_len);
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USB_EPR[ep] = calc_epr_bits(epr, USB_EPRX_STAT | USB_EPTX_STAT
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, USB_EP_RX_VALID | USB_EP_TX_NAK);
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return count;
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}
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int_fast8_t
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usb_read_ep0_setup(void *data, uint_fast8_t max_len)
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{
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return usb_read_ep0(data, max_len);
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}
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int_fast8_t
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usb_send_ep0(const void *data, uint_fast8_t len)
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{
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uint32_t ep = 0, epr = USB_EPR[ep];
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if ((epr & USB_EPRX_STAT) != USB_EP_RX_VALID)
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// Transfer interrupted
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return -2;
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if ((epr & USB_EPTX_STAT) != USB_EP_TX_NAK)
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// No buffer space available
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return -1;
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btable_write_packet(ep, BUFTX, data, len);
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USB_EPR[ep] = calc_epr_bits(epr, USB_EPTX_STAT, USB_EP_TX_VALID);
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return len;
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}
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void
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usb_stall_ep0(void)
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{
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uint32_t ep = 0, epr = USB_EPR[ep];
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USB_EPR[ep] = calc_epr_bits(epr, USB_EPRX_STAT | USB_EPTX_STAT
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, USB_EP_RX_STALL | USB_EP_TX_STALL);
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}
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static uint8_t set_address;
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void
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usb_set_address(uint_fast8_t addr)
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{
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writeb(&set_address, addr | USB_DADDR_EF);
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usb_send_ep0(NULL, 0);
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}
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void
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usb_set_configure(void)
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{
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uint32_t ep = USB_CDC_EP_BULK_OUT;
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bulk_out_pop_count = 0;
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USB_EPR[ep] = calc_epr_bits(USB_EPR[ep], USB_EPRX_STAT, USB_EP_RX_VALID);
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}
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/****************************************************************
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* Setup and interrupts
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****************************************************************/
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// Configure interface after a USB reset event
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static void
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usb_reset(void)
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{
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uint32_t ep = 0;
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USB_EPR[ep] = 0 | USB_EP_CONTROL | USB_EP_RX_VALID | USB_EP_TX_NAK;
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ep = USB_CDC_EP_ACM;
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USB_EPR[ep] = (USB_CDC_EP_ACM | USB_EP_INTERRUPT
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| USB_EP_RX_NAK | USB_EP_TX_NAK);
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ep = USB_CDC_EP_BULK_OUT;
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USB_EPR[ep] = (USB_CDC_EP_BULK_OUT | USB_EP_BULK | USB_EP_KIND
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| USB_EP_RX_VALID | USB_EP_TX_NAK | USB_EP_DTOG_TX);
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bulk_out_push_flag = USB_EP_DTOG_TX;
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ep = USB_CDC_EP_BULK_IN;
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USB_EPR[ep] = (USB_CDC_EP_BULK_IN | USB_EP_BULK
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| USB_EP_RX_NAK | USB_EP_TX_NAK);
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USB->CNTR = USB_CNTR_CTRM | USB_CNTR_RESETM;
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USB->DADDR = USB_DADDR_EF;
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}
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// Main irq handler
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void
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USB_IRQHandler(void)
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{
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uint32_t istr = USB->ISTR;
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if (istr & USB_ISTR_CTR) {
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// Endpoint activity
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uint32_t ep = istr & USB_ISTR_EP_ID, epr = USB_EPR[ep];
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if (ep == USB_CDC_EP_BULK_OUT) {
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USB_EPR[ep] = (calc_epr_bits(epr, USB_EP_CTR_RX | USB_EP_CTR_TX, 0)
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| bulk_out_push_flag);
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bulk_out_push_flag = 0;
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usb_notify_bulk_out();
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} else if (ep == USB_CDC_EP_BULK_IN) {
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USB_EPR[ep] = calc_epr_bits(epr, USB_EP_CTR_RX | USB_EP_CTR_TX, 0);
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usb_notify_bulk_in();
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} else if (ep == 0) {
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USB_EPR[ep] = calc_epr_bits(epr, USB_EP_CTR_RX | USB_EP_CTR_TX, 0);
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usb_notify_ep0();
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if (epr & USB_EP_CTR_TX && set_address) {
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// Apply address after last "in" message transmitted
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USB->DADDR = set_address;
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set_address = 0;
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}
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}
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}
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if (istr & USB_ISTR_RESET) {
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// USB Reset
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USB->ISTR = (uint16_t)~USB_ISTR_RESET;
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usb_reset();
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}
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}
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DECL_CONSTANT_STR("RESERVE_PINS_USB", "PA11,PA12");
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// Initialize the usb controller
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void
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usb_init(void)
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{
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if (CONFIG_MACH_STM32F1) {
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// Pull the D+ pin low briefly to signal a new connection
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gpio_out_setup(GPIO('A', 12), 0);
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udelay(5000);
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gpio_in_setup(GPIO('A', 12), 0);
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}
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// Enable USB clock
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enable_pclock(USB_BASE);
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// Setup USB packet memory
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btable_configure();
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// Enable USB pullup
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#ifdef USB_BCDR_DPPU
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USB->BCDR = USB_BCDR_DPPU;
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#endif
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// Reset usb controller and enable interrupts
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USB->CNTR = USB_CNTR_FRES;
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USB->DADDR = 0;
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USB->CNTR = USB_CNTR_RESETM;
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USB->ISTR = 0;
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armcm_enable_irq(USB_IRQHandler, USBx_IRQn, 1);
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}
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DECL_INIT(usb_init);
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