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94c86d6c6c
Most of the peripherals on the sam4e8e are similar to the ones on the sam3x8e mcu. Merge the code together and use just one code directory. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
125 lines
3.7 KiB
C
125 lines
3.7 KiB
C
// SAM4e8e SPI port
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//
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// Copyright (C) 2018 Florian Heilmann <Florian.Heilmann@gmx.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_FREQ
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#include "command.h" // shutdown
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#include "gpio.h" // spi_setup
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#include "internal.h" // gpio_peripheral
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#include "sam4e.h" // USART0
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#include "sched.h" // sched_shutdown
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#define SSPI_USART0 0
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#define SSPI_USART1 1
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#define SSPI_SPI 2
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struct spi_config
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spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
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{
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Usart *p_usart = USART0;
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if (bus > 2) {
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shutdown("Invalid spi_setup parameters");
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}
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if (bus == SSPI_USART0) {
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// DUET_USART0_SCK as per dc42 CoreNG
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gpio_peripheral(GPIO('B', 13), 'C', 0);
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// DUET_USART0_MOSI as per dc42 CoreNG
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gpio_peripheral(GPIO('B', 1), 'C', 0);
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// DUET_USART0_MISO as per dc42 CoreNG
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gpio_peripheral(GPIO('B', 0), 'C', 1);
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if ((PMC->PMC_PCSR0 & (1u << ID_USART0)) == 0) {
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PMC->PMC_PCER0 = 1 << ID_USART0;
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}
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p_usart = USART0;
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} else if (bus == SSPI_USART1) {
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// DUET_USART1_SCK as per dc42 CoreNG
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gpio_peripheral(GPIO('A', 23), 'A', 0);
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// DUET_USART1_MOSI as per dc42 CoreNG
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gpio_peripheral(GPIO('A', 22), 'A', 0);
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// DUET_USART1_MISO as per dc42 CoreNG
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gpio_peripheral(GPIO('A', 21), 'A', 1);
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if ((PMC->PMC_PCSR0 & (1u << ID_USART1)) == 0) {
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PMC->PMC_PCER0 = 1 << ID_USART1;
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}
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p_usart = USART1;
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}
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if (bus < 2) {
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p_usart->US_MR = 0;
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p_usart->US_RTOR = 0;
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p_usart->US_TTGR = 0;
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p_usart->US_CR = US_CR_RSTTX | US_CR_RSTRX | US_CR_TXDIS | US_CR_RXDIS;
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uint32_t br = (CONFIG_CLOCK_FREQ + rate / 2) / rate;
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p_usart-> US_BRGR = br << US_BRGR_CD_Pos;
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uint32_t reg = US_MR_CHRL_8_BIT |
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US_MR_USART_MODE_SPI_MASTER |
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US_MR_CLKO |
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US_MR_CHMODE_NORMAL;
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switch (mode) {
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case 0:
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reg |= US_MR_CPHA;
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reg &= ~US_MR_CPOL;
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break;
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case 1:
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reg &= ~US_MR_CPHA;
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reg &= ~US_MR_CPOL;
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break;
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case 2:
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reg |= US_MR_CPHA;
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reg |= US_MR_CPOL;
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break;
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case 3:
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reg &= ~US_MR_CPHA;
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reg |= US_MR_CPOL;
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break;
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}
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p_usart->US_MR |= reg;
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p_usart->US_CR = US_CR_RXEN | US_CR_TXEN;
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return (struct spi_config){ .sspi=p_usart, .cfg=p_usart->US_MR };
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}
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// True SPI implementation still ToDo
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return (struct spi_config){ .sspi = 0, .cfg=0};
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}
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void
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spi_transfer(struct spi_config config, uint8_t receive_data
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, uint8_t len, uint8_t *data)
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{
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if ((config.sspi == USART0) || (config.sspi == USART1)) {
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Usart *p_usart = config.sspi;
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if (receive_data) {
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for (uint32_t i = 0; i < len; ++i) {
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uint32_t co = (uint32_t)*data & 0x000000FF;
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while(!(p_usart->US_CSR & US_CSR_TXRDY)) {}
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p_usart->US_THR = US_THR_TXCHR(co);
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uint32_t ci = 0;
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while(!(p_usart->US_CSR & US_CSR_RXRDY)) {}
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ci = p_usart->US_RHR & US_RHR_RXCHR_Msk;
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*data++ = (uint8_t)ci;
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}
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} else {
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for (uint32_t i = 0; i < len; ++i) {
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uint32_t co = (uint32_t)*data & 0x000000FF;
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while(!(p_usart->US_CSR & US_CSR_TXRDY)) {}
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p_usart->US_THR = US_THR_TXCHR(co);
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while(!(p_usart->US_CSR & US_CSR_RXRDY)) {}
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(void)(p_usart->US_RHR & US_RHR_RXCHR_Msk);
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(void)*data++;
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}
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}
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}
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}
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void
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spi_prepare(struct spi_config config) {}
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