andreil/klipper
1
0
Fork 0
mirror of https://github.com/andreili/klipper.git synced 2025-08-24 03:44:06 +02:00
Code Issues Packages Projects Releases Wiki Activity

stm32: Support over 400Mhz main clock in stm32h7_adc.c

Browse Source 
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2025-04-28 20:14:14 -04:00
parent 7b697105b3
commit ee79d0e307
1 changed files with 7 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
src/stm32/stm32h7_adc.c
View File

@ -160,10 +160,10 @@ static const uint8_t adc_pins[] = {
#define ADC_CKMODE 0b11 #define ADC_CKMODE 0b11
#define ADC_ATICKS 0b110 #define ADC_ATICKS 0b110
#define ADC_ATICKS_H723_ADC3 0b111 #define ADC_ATICKS_H723_ADC3 0b111
// stm32h7: clock=25Mhz, Tsamp=387.5, Tconv=394, total=15.76us // 400Mhz stm32h7: clock=25Mhz, Tsamp=387.5, Tconv=394, total=15.76us
// stm32h723 adc3: clock=50Mhz, Tsamp=640.5, Tconv=653, total=13.06us // 400Mhz stm32h723 adc3: clock=50Mhz, Tsamp=640.5, Tconv=653, total=13.06us
// stm32l4: clock=20Mhz, Tsamp=247.5, Tconv=260, total=13.0us // 80Mhz stm32l4: clock=20Mhz, Tsamp=247.5, Tconv=260, total=13.0us
// stm32g4: clock=37.5Mhz, Tsamp=247.5, Tconv=260, total=6.933us // 150Mhz stm32g4: clock=37.5Mhz, Tsamp=247.5, Tconv=260, total=6.933us
// Handle register name differences between chips // Handle register name differences between chips
#if CONFIG_MACH_STM32H723 #if CONFIG_MACH_STM32H723
@ -231,8 +231,9 @@ gpio_adc_setup(uint32_t pin)
} else { } else {
// Use linear calibration on stm32h7 // Use linear calibration on stm32h7
cr |= ADC_CR_ADCALLIN; cr |= ADC_CR_ADCALLIN;
// Set boost mode on stm32h7 (adc clock is at 25Mhz) // Set boost mode on stm32h7
cr |= 0b10 << ADC_CR_BOOST_Pos; uint32_t boost = CONFIG_CLOCK_FREQ > 400000000 ? 0b11 : 0b10;
cr |= boost << ADC_CR_BOOST_Pos;
// Set 12bit samples on the stm32h7 // Set 12bit samples on the stm32h7
adc->CFGR = ADC_CFGR_JQDIS | (0b110 << ADC_CFGR_RES_Pos); adc->CFGR = ADC_CFGR_JQDIS | (0b110 << ADC_CFGR_RES_Pos);
} }