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stm32: Run stm32g431 at 170Mhz

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The chip supports 170Mhz, so no need to run at 150Mhz.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2025-05-31 02:01:39 -04:00
parent 2dd73d0431
commit cfa48fe39f
3 changed files with 8 additions and 5 deletions
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2
src/stm32/Kconfig
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@ -206,7 +206,7 @@ config CLOCK_FREQ
default 180000000 if MACH_STM32F446
default 216000000 if MACH_STM32F765
default 64000000 if MACH_STM32G0
default 150000000 if MACH_STM32G431
default 170000000 if MACH_STM32G431
default 170000000 if MACH_STM32G474
default 520000000 if MACH_STM32H723
default 400000000 if MACH_STM32H743 || MACH_STM32H750

9
src/stm32/stm32g4.c
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@ -1,6 +1,6 @@
// Code to setup clocks and gpio on stm32g4
//
// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
// Copyright (C) 2019-2025 Kevin O'Connor <kevin@koconnor.net>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
@ -85,14 +85,14 @@ enable_clock_stm32g4(void)
{
uint32_t pll_base = 4000000, pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr;
if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
// Configure 150Mhz PLL from external crystal (HSE)
// Configure PLL from external crystal (HSE)
uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base - 1;
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY))
;
pllcfgr = RCC_PLLCFGR_PLLSRC_HSE | (div << RCC_PLLCFGR_PLLM_Pos);
} else {
// Configure 150Mhz PLL from internal 16Mhz oscillator (HSI)
// Configure PLL from internal 16Mhz oscillator (HSI)
uint32_t div = 16000000 / pll_base - 1;
pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos);
RCC->CR |= RCC_CR_HSION;
@ -134,6 +134,9 @@ clock_setup(void)
enable_pclock(PWR_BASE);
PWR->CR3 |= PWR_CR3_APC; // allow gpio pullup/down
if (CONFIG_CLOCK_FREQ > 150000000)
// Enable "range 1 boost" mode
PWR->CR5 = 0;
// Wait for PLL lock
while (!(RCC->CR & RCC_CR_PLLRDY))

2
src/stm32/stm32h7_adc.c
View File

@ -164,7 +164,7 @@ static const uint8_t adc_pins[] = {
// 520Mhz stm32h723: clock=32.5Mhz, Tsamp=387.5, Tconv=394, total=12.12us
// 520Mhz stm32h723 adc3: clock=65Mhz, Tsamp=640.5, Tconv=653, total=10.05us
// 80Mhz stm32l4: clock=20Mhz, Tsamp=247.5, Tconv=260, total=13.0us
// 150Mhz stm32g4: clock=37.5Mhz, Tsamp=247.5, Tconv=260, total=6.933us
// 170Mhz stm32g4: clock=42.5Mhz, Tsamp=247.5, Tconv=260, total=6.118us
// Handle register name differences between chips
#if CONFIG_MACH_STM32H723