From 9c37a918db03eb456dd0a6c4c072f2b544d8f569 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Mon, 21 Apr 2025 20:55:56 -0400 Subject: [PATCH] stm32: Set the PLL frequency equal to CONFIG_CLOCK_FREQ on stm32h723 There is no reason to use a higher internal PLL frequency. This change also makes it possible to enable higher clock frequencies on the stm32h723. Signed-off-by: Kevin O'Connor --- src/stm32/stm32h7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stm32/stm32h7.c b/src/stm32/stm32h7.c index 737f6668..79d4ab99 100644 --- a/src/stm32/stm32h7.c +++ b/src/stm32/stm32h7.c @@ -93,7 +93,7 @@ clock_setup(void) // Setup pll1 frequency uint32_t pll_base = CONFIG_STM32_CLOCK_REF_25M ? 5000000 : 4000000; - uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2; + uint32_t pll_freq = CONFIG_CLOCK_FREQ * (CONFIG_MACH_STM32H723 ? 1 : 2); uint32_t rcc_cr = RCC_CR_HSION; if (!CONFIG_STM32_CLOCK_REF_INTERNAL) { // Configure PLL from external crystal (HSE)