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stm32: Fix broken clock setup on stm32f1

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Commit bd6c25c9 introduced a typo that caused the clock divisors to
not be set correctly on stm32f1.

Reported by @brianrjones69.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2020-02-29 13:07:32 -05:00
parent 1c06ea8afe
commit 31b2c3ea7a
1 changed files with 2 additions and 2 deletions
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4
src/stm32/stm32f1.c
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@ -140,8 +140,8 @@ clock_setup(void)
cfgr = ((0 << RCC_CFGR_PLLSRC_Pos) cfgr = ((0 << RCC_CFGR_PLLSRC_Pos)
| ((div2 - 2) << RCC_CFGR_PLLMULL_Pos)); | ((div2 - 2) << RCC_CFGR_PLLMULL_Pos));
} }
RCC->CFGR = (cfgr | RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 cfgr |= RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV4;
| RCC_CFGR_ADCPRE_DIV4); RCC->CFGR = cfgr;
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
// Set flash latency // Set flash latency