mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
106 lines
4.9 KiB
C
106 lines
4.9 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_SPI_H
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#define _HARDWARE_STRUCTS_SPI_H
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/**
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* \file rp2040/spi.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/spi.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/spi.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0
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// Control register 0, SSPCR0 on page 3-4
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// 0x0000ff00 [15:8] SCR (0x00) Serial clock rate
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// 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only
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// 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only
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// 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format
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// 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation
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io_rw_32 cr0;
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_REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1
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// Control register 1, SSPCR1 on page 3-5
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// 0x00000008 [3] SOD (0) Slave-mode output disable
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// 0x00000004 [2] MS (0) Master or slave mode select
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// 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled
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// 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled
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io_rw_32 cr1;
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_REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR
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// Data register, SSPDR on page 3-6
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// 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO
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io_rw_32 dr;
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_REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR
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// Status register, SSPSR on page 3-7
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// 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle
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// 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full
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// 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty
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// 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full
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// 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty
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io_ro_32 sr;
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_REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR
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// Clock prescale register, SSPCPSR on page 3-8
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// 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor
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io_rw_32 cpsr;
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_REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC
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// Interrupt mask set or clear register, SSPIMSC on page 3-9
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// 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty...
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// 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or...
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// 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty...
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// 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written...
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io_rw_32 imsc;
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_REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS
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// Raw interrupt status register, SSPRIS on page 3-10
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// 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the...
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// 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the...
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// 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the...
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// 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the...
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io_ro_32 ris;
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_REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS
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// Masked interrupt status register, SSPMIS on page 3-11
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// 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after...
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// 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after...
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// 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after...
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// 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,...
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io_ro_32 mis;
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_REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR
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// Interrupt clear register, SSPICR on page 3-11
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// 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt
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// 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt
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io_rw_32 icr;
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_REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR
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// DMA control register, SSPDMACR on page 3-12
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// 0x00000002 [1] TXDMAE (0) Transmit DMA Enable
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// 0x00000001 [0] RXDMAE (0) Receive DMA Enable
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io_rw_32 dmacr;
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} spi_hw_t;
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#define spi0_hw ((spi_hw_t *)SPI0_BASE)
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#define spi1_hw ((spi_hw_t *)SPI1_BASE)
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static_assert(sizeof (spi_hw_t) == 0x0028, "");
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#endif // _HARDWARE_STRUCTS_SPI_H
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