mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
280 lines
15 KiB
C
280 lines
15 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : SYSCFG
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// Version : 1
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// Bus type : apb
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// Description : Register block for various chip control signals
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// =============================================================================
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#ifndef _HARDWARE_REGS_SYSCFG_H
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#define _HARDWARE_REGS_SYSCFG_H
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// =============================================================================
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// Register : SYSCFG_PROC_CONFIG
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// Description : Configuration for processors
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#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000000)
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#define SYSCFG_PROC_CONFIG_BITS _u(0x00000003)
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#define SYSCFG_PROC_CONFIG_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
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// Description : Indication that proc1 has halted
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0)
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002)
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1)
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1)
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
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// Description : Indication that proc0 has halted
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0)
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001)
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0)
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0)
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
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// =============================================================================
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// Register : SYSCFG_PROC_IN_SYNC_BYPASS
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// Description : For each bit, if 1, bypass the input synchronizer between that
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// GPIO
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// and the GPIO input register in the SIO. The input synchronizers
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// should
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// generally be unbypassed, to avoid injecting metastabilities
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// into processors.
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// If you're feeling brave, you can bypass to save two cycles of
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// input
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// latency. This register applies to GPIO 0...31.
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#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x00000004)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0xffffffff)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_IN_SYNC_BYPASS_GPIO
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#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_RESET _u(0x00000000)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_BITS _u(0xffffffff)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_MSB _u(31)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_LSB _u(0)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_ACCESS "RW"
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// =============================================================================
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// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
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// Description : For each bit, if 1, bypass the input synchronizer between that
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// GPIO
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// and the GPIO input register in the SIO. The input synchronizers
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// should
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// generally be unbypassed, to avoid injecting metastabilities
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// into processors.
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// If you're feeling brave, you can bypass to save two cycles of
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// input
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// latency. This register applies to GPIO 32...47. USB GPIO 56..57
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// QSPI GPIO 58..63
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000008)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0xff00ffff)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_RESET _u(0x0)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_BITS _u(0xf0000000)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_MSB _u(31)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_LSB _u(28)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_RESET _u(0x0)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_BITS _u(0x08000000)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_MSB _u(27)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_LSB _u(27)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_RESET _u(0x0)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_BITS _u(0x04000000)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_MSB _u(26)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_LSB _u(26)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_RESET _u(0x0)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_BITS _u(0x02000000)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_MSB _u(25)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_LSB _u(25)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_RESET _u(0x0)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_BITS _u(0x01000000)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_MSB _u(24)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_LSB _u(24)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_RESET _u(0x0000)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_BITS _u(0x0000ffff)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_MSB _u(15)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_LSB _u(0)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_ACCESS "RW"
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// =============================================================================
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// Register : SYSCFG_DBGFORCE
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// Description : Directly control the chip SWD debug port
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#define SYSCFG_DBGFORCE_OFFSET _u(0x0000000c)
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#define SYSCFG_DBGFORCE_BITS _u(0x0000000f)
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#define SYSCFG_DBGFORCE_RESET _u(0x00000006)
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_ATTACH
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// Description : Attach chip debug port to syscfg controls, and disconnect it
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// from external SWD pads.
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#define SYSCFG_DBGFORCE_ATTACH_RESET _u(0x0)
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#define SYSCFG_DBGFORCE_ATTACH_BITS _u(0x00000008)
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#define SYSCFG_DBGFORCE_ATTACH_MSB _u(3)
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#define SYSCFG_DBGFORCE_ATTACH_LSB _u(3)
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#define SYSCFG_DBGFORCE_ATTACH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_SWCLK
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// Description : Directly drive SWCLK, if ATTACH is set
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#define SYSCFG_DBGFORCE_SWCLK_RESET _u(0x1)
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#define SYSCFG_DBGFORCE_SWCLK_BITS _u(0x00000004)
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#define SYSCFG_DBGFORCE_SWCLK_MSB _u(2)
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#define SYSCFG_DBGFORCE_SWCLK_LSB _u(2)
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#define SYSCFG_DBGFORCE_SWCLK_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_SWDI
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// Description : Directly drive SWDIO input, if ATTACH is set
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#define SYSCFG_DBGFORCE_SWDI_RESET _u(0x1)
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#define SYSCFG_DBGFORCE_SWDI_BITS _u(0x00000002)
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#define SYSCFG_DBGFORCE_SWDI_MSB _u(1)
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#define SYSCFG_DBGFORCE_SWDI_LSB _u(1)
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#define SYSCFG_DBGFORCE_SWDI_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_SWDO
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// Description : Observe the value of SWDIO output.
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#define SYSCFG_DBGFORCE_SWDO_RESET "-"
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#define SYSCFG_DBGFORCE_SWDO_BITS _u(0x00000001)
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#define SYSCFG_DBGFORCE_SWDO_MSB _u(0)
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#define SYSCFG_DBGFORCE_SWDO_LSB _u(0)
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#define SYSCFG_DBGFORCE_SWDO_ACCESS "RO"
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// =============================================================================
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// Register : SYSCFG_MEMPOWERDOWN
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// Description : Control PD pins to memories.
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// Set high to put memories to a low power state. In this state
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// the memories will retain contents but not be accessible
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// Use with caution
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#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000010)
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#define SYSCFG_MEMPOWERDOWN_BITS _u(0x00001fff)
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#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_BOOTRAM
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#define SYSCFG_MEMPOWERDOWN_BOOTRAM_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_BOOTRAM_BITS _u(0x00001000)
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#define SYSCFG_MEMPOWERDOWN_BOOTRAM_MSB _u(12)
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#define SYSCFG_MEMPOWERDOWN_BOOTRAM_LSB _u(12)
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#define SYSCFG_MEMPOWERDOWN_BOOTRAM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_ROM
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#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000800)
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#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(11)
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#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(11)
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#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_USB
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#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000400)
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#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(10)
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#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(10)
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#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM9
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#define SYSCFG_MEMPOWERDOWN_SRAM9_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM9_BITS _u(0x00000200)
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#define SYSCFG_MEMPOWERDOWN_SRAM9_MSB _u(9)
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#define SYSCFG_MEMPOWERDOWN_SRAM9_LSB _u(9)
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#define SYSCFG_MEMPOWERDOWN_SRAM9_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM8
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#define SYSCFG_MEMPOWERDOWN_SRAM8_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM8_BITS _u(0x00000100)
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#define SYSCFG_MEMPOWERDOWN_SRAM8_MSB _u(8)
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#define SYSCFG_MEMPOWERDOWN_SRAM8_LSB _u(8)
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#define SYSCFG_MEMPOWERDOWN_SRAM8_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM7
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#define SYSCFG_MEMPOWERDOWN_SRAM7_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM7_BITS _u(0x00000080)
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#define SYSCFG_MEMPOWERDOWN_SRAM7_MSB _u(7)
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#define SYSCFG_MEMPOWERDOWN_SRAM7_LSB _u(7)
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#define SYSCFG_MEMPOWERDOWN_SRAM7_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM6
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#define SYSCFG_MEMPOWERDOWN_SRAM6_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM6_BITS _u(0x00000040)
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#define SYSCFG_MEMPOWERDOWN_SRAM6_MSB _u(6)
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#define SYSCFG_MEMPOWERDOWN_SRAM6_LSB _u(6)
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#define SYSCFG_MEMPOWERDOWN_SRAM6_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM5
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#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
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#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
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#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5)
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#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM4
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#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
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#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
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#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4)
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#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM3
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#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
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#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
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#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3)
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#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM2
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#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
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#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
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#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2)
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#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM1
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#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
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#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
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#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1)
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#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM0
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#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
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#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
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#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
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#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
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// =============================================================================
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// Register : SYSCFG_AUXCTRL
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// Description : Auxiliary system control register
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// * Bits 7:2: Reserved
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//
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// * Bit 1: When clear, the LPOSC output is XORed into the TRNG
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// ROSC output as an additional, uncorrelated entropy source. When
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// set, this behaviour is disabled.
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//
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// * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting
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// its WDRESET input. This must be set before initiating a
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// watchdog reset of the RSM from a stage that includes CLOCKS, if
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// POWMAN is running from clk_ref at the point that the watchdog
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// reset takes place. Otherwise, the short pulse generated on
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// clk_ref by the reset of the CLOCKS block may affect POWMAN
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// register state.
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#define SYSCFG_AUXCTRL_OFFSET _u(0x00000014)
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#define SYSCFG_AUXCTRL_BITS _u(0x000000ff)
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#define SYSCFG_AUXCTRL_RESET _u(0x00000000)
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#define SYSCFG_AUXCTRL_MSB _u(7)
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#define SYSCFG_AUXCTRL_LSB _u(0)
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#define SYSCFG_AUXCTRL_ACCESS "RW"
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// =============================================================================
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#endif // _HARDWARE_REGS_SYSCFG_H
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