mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
229 lines
11 KiB
C
229 lines
11 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : SHA256
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// Version : 1
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// Bus type : apb
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// Description : SHA-256 hash function implementation
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// =============================================================================
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#ifndef _HARDWARE_REGS_SHA256_H
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#define _HARDWARE_REGS_SHA256_H
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// =============================================================================
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// Register : SHA256_CSR
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// Description : Control and status register
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#define SHA256_CSR_OFFSET _u(0x00000000)
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#define SHA256_CSR_BITS _u(0x00001317)
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#define SHA256_CSR_RESET _u(0x00001206)
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// -----------------------------------------------------------------------------
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// Field : SHA256_CSR_BSWAP
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// Description : Enable byte swapping of 32-bit values at the point they are
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// committed to the SHA message scheduler.
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//
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// This block's bus interface assembles byte/halfword data into
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// message words in little-endian order, so that DMAing the same
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// buffer with different transfer sizes always gives the same
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// result on a little-endian system like RP2350.
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//
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// However, when marshalling bytes into blocks, SHA expects that
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// the first byte is the *most significant* in each message word.
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// To resolve this, once the bus interface has accumulated 32 bits
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// of data (either a word write, two halfword writes in little-
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// endian order, or four byte writes in little-endian order) the
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// final value can be byte-swapped before passing to the actual
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// SHA core.
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//
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// This feature is enabled by default because using the SHA core
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// to checksum byte buffers is expected to be more common than
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// having preformatted SHA message words lying around.
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#define SHA256_CSR_BSWAP_RESET _u(0x1)
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#define SHA256_CSR_BSWAP_BITS _u(0x00001000)
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#define SHA256_CSR_BSWAP_MSB _u(12)
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#define SHA256_CSR_BSWAP_LSB _u(12)
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#define SHA256_CSR_BSWAP_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SHA256_CSR_DMA_SIZE
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// Description : Configure DREQ logic for the correct DMA data size. Must be
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// configured before the DMA channel is triggered.
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//
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// The SHA-256 core's DREQ logic requests one entire block of data
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// at once, since there is no FIFO, and data goes straight into
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// the core's message schedule and digest hardware. Therefore,
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// when transferring data with DMA, CSR_DMA_SIZE must be
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// configured in advance so that the correct number of transfers
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// can be requested per block.
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// 0x0 -> 8bit
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// 0x1 -> 16bit
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// 0x2 -> 32bit
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#define SHA256_CSR_DMA_SIZE_RESET _u(0x2)
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#define SHA256_CSR_DMA_SIZE_BITS _u(0x00000300)
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#define SHA256_CSR_DMA_SIZE_MSB _u(9)
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#define SHA256_CSR_DMA_SIZE_LSB _u(8)
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#define SHA256_CSR_DMA_SIZE_ACCESS "RW"
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#define SHA256_CSR_DMA_SIZE_VALUE_8BIT _u(0x0)
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#define SHA256_CSR_DMA_SIZE_VALUE_16BIT _u(0x1)
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#define SHA256_CSR_DMA_SIZE_VALUE_32BIT _u(0x2)
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// -----------------------------------------------------------------------------
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// Field : SHA256_CSR_ERR_WDATA_NOT_RDY
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// Description : Set when a write occurs whilst the SHA-256 core is not ready
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// for data (WDATA_RDY is low). Write one to clear.
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#define SHA256_CSR_ERR_WDATA_NOT_RDY_RESET _u(0x0)
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#define SHA256_CSR_ERR_WDATA_NOT_RDY_BITS _u(0x00000010)
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#define SHA256_CSR_ERR_WDATA_NOT_RDY_MSB _u(4)
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#define SHA256_CSR_ERR_WDATA_NOT_RDY_LSB _u(4)
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#define SHA256_CSR_ERR_WDATA_NOT_RDY_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : SHA256_CSR_SUM_VLD
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// Description : If 1, the SHA-256 checksum presented in registers SUM0 through
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// SUM7 is currently valid.
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//
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// Goes low when WDATA is first written, then returns high once 16
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// words have been written and the digest of the current 512-bit
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// block has subsequently completed.
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#define SHA256_CSR_SUM_VLD_RESET _u(0x1)
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#define SHA256_CSR_SUM_VLD_BITS _u(0x00000004)
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#define SHA256_CSR_SUM_VLD_MSB _u(2)
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#define SHA256_CSR_SUM_VLD_LSB _u(2)
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#define SHA256_CSR_SUM_VLD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SHA256_CSR_WDATA_RDY
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// Description : If 1, the SHA-256 core is ready to accept more data through the
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// WDATA register.
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//
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// After writing 16 words, this flag will go low for 57 cycles
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// whilst the core completes its digest.
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#define SHA256_CSR_WDATA_RDY_RESET _u(0x1)
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#define SHA256_CSR_WDATA_RDY_BITS _u(0x00000002)
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#define SHA256_CSR_WDATA_RDY_MSB _u(1)
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#define SHA256_CSR_WDATA_RDY_LSB _u(1)
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#define SHA256_CSR_WDATA_RDY_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SHA256_CSR_START
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// Description : Write 1 to prepare the SHA-256 core for a new checksum.
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//
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// The SUMx registers are initialised to the proper values
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// (fractional bits of square roots of first 8 primes) and
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// internal counters are cleared. This immediately forces
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// WDATA_RDY and SUM_VLD high.
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//
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// START must be written before initiating a DMA transfer to the
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// SHA-256 core, because the core will always request 16 transfers
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// at a time (1 512-bit block). Additionally, the DMA channel
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// should be configured for a multiple of 16 32-bit transfers.
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#define SHA256_CSR_START_RESET _u(0x0)
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#define SHA256_CSR_START_BITS _u(0x00000001)
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#define SHA256_CSR_START_MSB _u(0)
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#define SHA256_CSR_START_LSB _u(0)
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#define SHA256_CSR_START_ACCESS "SC"
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// =============================================================================
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// Register : SHA256_WDATA
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// Description : Write data register
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// After pulsing START and writing 16 words of data to this
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// register, WDATA_RDY will go low and the SHA-256 core will
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// complete the digest of the current 512-bit block.
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//
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// Software is responsible for ensuring the data is correctly
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// padded and terminated to a whole number of 512-bit blocks.
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//
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// After this, WDATA_RDY will return high, and more data can be
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// written (if any).
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//
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// This register supports word, halfword and byte writes, so that
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// DMA from non-word-aligned buffers can be supported. The total
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// amount of data per block remains the same (16 words, 32
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// halfwords or 64 bytes) and byte/halfword transfers must not be
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// mixed within a block.
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#define SHA256_WDATA_OFFSET _u(0x00000004)
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#define SHA256_WDATA_BITS _u(0xffffffff)
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#define SHA256_WDATA_RESET _u(0x00000000)
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#define SHA256_WDATA_MSB _u(31)
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#define SHA256_WDATA_LSB _u(0)
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#define SHA256_WDATA_ACCESS "WF"
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// =============================================================================
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// Register : SHA256_SUM0
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// Description : 256-bit checksum result. Contents are undefined when
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// CSR_SUM_VLD is 0.
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#define SHA256_SUM0_OFFSET _u(0x00000008)
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#define SHA256_SUM0_BITS _u(0xffffffff)
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#define SHA256_SUM0_RESET _u(0x00000000)
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#define SHA256_SUM0_MSB _u(31)
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#define SHA256_SUM0_LSB _u(0)
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#define SHA256_SUM0_ACCESS "RO"
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// =============================================================================
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// Register : SHA256_SUM1
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// Description : 256-bit checksum result. Contents are undefined when
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// CSR_SUM_VLD is 0.
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#define SHA256_SUM1_OFFSET _u(0x0000000c)
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#define SHA256_SUM1_BITS _u(0xffffffff)
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#define SHA256_SUM1_RESET _u(0x00000000)
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#define SHA256_SUM1_MSB _u(31)
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#define SHA256_SUM1_LSB _u(0)
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#define SHA256_SUM1_ACCESS "RO"
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// =============================================================================
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// Register : SHA256_SUM2
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// Description : 256-bit checksum result. Contents are undefined when
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// CSR_SUM_VLD is 0.
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#define SHA256_SUM2_OFFSET _u(0x00000010)
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#define SHA256_SUM2_BITS _u(0xffffffff)
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#define SHA256_SUM2_RESET _u(0x00000000)
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#define SHA256_SUM2_MSB _u(31)
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#define SHA256_SUM2_LSB _u(0)
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#define SHA256_SUM2_ACCESS "RO"
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// =============================================================================
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// Register : SHA256_SUM3
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// Description : 256-bit checksum result. Contents are undefined when
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// CSR_SUM_VLD is 0.
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#define SHA256_SUM3_OFFSET _u(0x00000014)
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#define SHA256_SUM3_BITS _u(0xffffffff)
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#define SHA256_SUM3_RESET _u(0x00000000)
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#define SHA256_SUM3_MSB _u(31)
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#define SHA256_SUM3_LSB _u(0)
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#define SHA256_SUM3_ACCESS "RO"
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// =============================================================================
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// Register : SHA256_SUM4
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// Description : 256-bit checksum result. Contents are undefined when
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// CSR_SUM_VLD is 0.
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#define SHA256_SUM4_OFFSET _u(0x00000018)
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#define SHA256_SUM4_BITS _u(0xffffffff)
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#define SHA256_SUM4_RESET _u(0x00000000)
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#define SHA256_SUM4_MSB _u(31)
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#define SHA256_SUM4_LSB _u(0)
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#define SHA256_SUM4_ACCESS "RO"
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// =============================================================================
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// Register : SHA256_SUM5
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// Description : 256-bit checksum result. Contents are undefined when
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// CSR_SUM_VLD is 0.
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#define SHA256_SUM5_OFFSET _u(0x0000001c)
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#define SHA256_SUM5_BITS _u(0xffffffff)
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#define SHA256_SUM5_RESET _u(0x00000000)
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#define SHA256_SUM5_MSB _u(31)
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#define SHA256_SUM5_LSB _u(0)
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#define SHA256_SUM5_ACCESS "RO"
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// =============================================================================
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// Register : SHA256_SUM6
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// Description : 256-bit checksum result. Contents are undefined when
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// CSR_SUM_VLD is 0.
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#define SHA256_SUM6_OFFSET _u(0x00000020)
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#define SHA256_SUM6_BITS _u(0xffffffff)
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#define SHA256_SUM6_RESET _u(0x00000000)
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#define SHA256_SUM6_MSB _u(31)
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#define SHA256_SUM6_LSB _u(0)
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#define SHA256_SUM6_ACCESS "RO"
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// =============================================================================
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// Register : SHA256_SUM7
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// Description : 256-bit checksum result. Contents are undefined when
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// CSR_SUM_VLD is 0.
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#define SHA256_SUM7_OFFSET _u(0x00000024)
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#define SHA256_SUM7_BITS _u(0xffffffff)
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#define SHA256_SUM7_RESET _u(0x00000000)
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#define SHA256_SUM7_MSB _u(31)
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#define SHA256_SUM7_LSB _u(0)
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#define SHA256_SUM7_ACCESS "RO"
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// =============================================================================
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#endif // _HARDWARE_REGS_SHA256_H
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