mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
81 lines
4.0 KiB
C
81 lines
4.0 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : M33_EPPB
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// Version : 1
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// Bus type : apb
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// Description : Cortex-M33 EPPB vendor register block for RP2350
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// =============================================================================
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#ifndef _HARDWARE_REGS_M33_EPPB_H
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#define _HARDWARE_REGS_M33_EPPB_H
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// =============================================================================
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// Register : M33_EPPB_NMI_MASK0
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// Description : NMI mask for IRQs 0 through 31. This register is core-local,
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// and is reset by a processor warm reset.
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#define M33_EPPB_NMI_MASK0_OFFSET _u(0x00000000)
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#define M33_EPPB_NMI_MASK0_BITS _u(0xffffffff)
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#define M33_EPPB_NMI_MASK0_RESET _u(0x00000000)
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#define M33_EPPB_NMI_MASK0_MSB _u(31)
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#define M33_EPPB_NMI_MASK0_LSB _u(0)
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#define M33_EPPB_NMI_MASK0_ACCESS "RW"
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// =============================================================================
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// Register : M33_EPPB_NMI_MASK1
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// Description : NMI mask for IRQs 0 though 51. This register is core-local, and
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// is reset by a processor warm reset.
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#define M33_EPPB_NMI_MASK1_OFFSET _u(0x00000004)
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#define M33_EPPB_NMI_MASK1_BITS _u(0x000fffff)
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#define M33_EPPB_NMI_MASK1_RESET _u(0x00000000)
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#define M33_EPPB_NMI_MASK1_MSB _u(19)
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#define M33_EPPB_NMI_MASK1_LSB _u(0)
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#define M33_EPPB_NMI_MASK1_ACCESS "RW"
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// =============================================================================
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// Register : M33_EPPB_SLEEPCTRL
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// Description : Nonstandard sleep control register
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#define M33_EPPB_SLEEPCTRL_OFFSET _u(0x00000008)
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#define M33_EPPB_SLEEPCTRL_BITS _u(0x00000007)
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#define M33_EPPB_SLEEPCTRL_RESET _u(0x00000002)
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// -----------------------------------------------------------------------------
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// Field : M33_EPPB_SLEEPCTRL_WICENACK
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// Description : Status signal from the processor's interrupt controller.
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// Changes to WICENREQ are eventually reflected in WICENACK.
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#define M33_EPPB_SLEEPCTRL_WICENACK_RESET _u(0x0)
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#define M33_EPPB_SLEEPCTRL_WICENACK_BITS _u(0x00000004)
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#define M33_EPPB_SLEEPCTRL_WICENACK_MSB _u(2)
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#define M33_EPPB_SLEEPCTRL_WICENACK_LSB _u(2)
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#define M33_EPPB_SLEEPCTRL_WICENACK_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : M33_EPPB_SLEEPCTRL_WICENREQ
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// Description : Request that the next processor deep sleep is a WIC sleep.
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// After setting this bit, before sleeping, poll WICENACK to
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// ensure the processor interrupt controller has acknowledged the
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// change.
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#define M33_EPPB_SLEEPCTRL_WICENREQ_RESET _u(0x1)
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#define M33_EPPB_SLEEPCTRL_WICENREQ_BITS _u(0x00000002)
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#define M33_EPPB_SLEEPCTRL_WICENREQ_MSB _u(1)
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#define M33_EPPB_SLEEPCTRL_WICENREQ_LSB _u(1)
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#define M33_EPPB_SLEEPCTRL_WICENREQ_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : M33_EPPB_SLEEPCTRL_LIGHT_SLEEP
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// Description : By default, any processor sleep will deassert the system-level
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// clock request. Reenabling the clocks incurs 5 cycles of
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// additional latency on wakeup.
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//
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// Setting LIGHT_SLEEP to 1 keeps the clock request asserted
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// during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster
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// wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not
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// affected, and will always deassert the system-level clock
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// request.
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#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_RESET _u(0x0)
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#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_BITS _u(0x00000001)
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#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_MSB _u(0)
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#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_LSB _u(0)
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#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_ACCESS "RW"
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// =============================================================================
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#endif // _HARDWARE_REGS_M33_EPPB_H
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