mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
22340 lines
1.3 MiB
22340 lines
1.3 MiB
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : IO_BANK0
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// Version : 1
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// Bus type : apb
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// =============================================================================
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#ifndef _HARDWARE_REGS_IO_BANK0_H
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#define _HARDWARE_REGS_IO_BANK0_H
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// =============================================================================
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// Register : IO_BANK0_GPIO0_STATUS
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#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000)
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#define IO_BANK0_GPIO0_STATUS_BITS _u(0x04022200)
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#define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC
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// Description : interrupt to processors, after override is applied
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#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0)
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#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000)
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#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26)
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#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26)
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#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO0_STATUS_INFROMPAD
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// Description : input signal from pad, before filtering and override are
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// applied
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#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000)
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#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17)
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#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17)
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#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO0_STATUS_OETOPAD
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// Description : output enable to pad after register override is applied
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#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000)
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#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13)
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#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13)
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#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD
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// Description : output signal to pad after register override is applied
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#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200)
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#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9)
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#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9)
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#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_GPIO0_CTRL
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#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004)
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#define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003f01f)
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#define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO0_CTRL_IRQOVER
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// 0x0 -> don't invert the interrupt
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// 0x1 -> invert the interrupt
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// 0x2 -> drive interrupt low
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// 0x3 -> drive interrupt high
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#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000)
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#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29)
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#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28)
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#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW"
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#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO0_CTRL_INOVER
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// 0x0 -> don't invert the peri input
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// 0x1 -> invert the peri input
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// 0x2 -> drive peri input low
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// 0x3 -> drive peri input high
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#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000)
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#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17)
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#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16)
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#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW"
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#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO0_CTRL_OEOVER
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// 0x0 -> drive output enable from peripheral signal selected by funcsel
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// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
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// 0x2 -> disable output
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// 0x3 -> enable output
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#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x0000c000)
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#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(15)
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#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(14)
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#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW"
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#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
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#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO0_CTRL_OUTOVER
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// 0x0 -> drive output from peripheral signal selected by funcsel
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// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
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// 0x2 -> drive output low
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// 0x3 -> drive output high
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#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00003000)
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#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(13)
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#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(12)
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#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW"
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#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO0_CTRL_FUNCSEL
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// Description : 0-31 -> selects pin function according to the gpio table
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// 31 == NULL
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// 0x00 -> jtag_tck
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// 0x01 -> spi0_rx
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// 0x02 -> uart0_tx
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// 0x03 -> i2c0_sda
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// 0x04 -> pwm_a_0
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// 0x05 -> siob_proc_0
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// 0x06 -> pio0_0
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// 0x07 -> pio1_0
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// 0x08 -> pio2_0
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// 0x09 -> xip_ss_n_1
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// 0x0a -> usb_muxing_overcurr_detect
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// 0x1f -> null
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW"
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIOB_PROC_0 _u(0x05)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO2_0 _u(0x08)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
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#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
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// =============================================================================
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// Register : IO_BANK0_GPIO1_STATUS
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#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008)
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#define IO_BANK0_GPIO1_STATUS_BITS _u(0x04022200)
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#define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC
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// Description : interrupt to processors, after override is applied
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#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0)
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#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000)
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#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26)
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#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26)
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#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO1_STATUS_INFROMPAD
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// Description : input signal from pad, before filtering and override are
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// applied
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#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000)
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#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17)
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#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17)
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#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO1_STATUS_OETOPAD
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// Description : output enable to pad after register override is applied
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#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000)
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#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13)
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#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13)
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#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD
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// Description : output signal to pad after register override is applied
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#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200)
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#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9)
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#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9)
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#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_GPIO1_CTRL
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#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c)
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#define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003f01f)
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#define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO1_CTRL_IRQOVER
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// 0x0 -> don't invert the interrupt
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// 0x1 -> invert the interrupt
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// 0x2 -> drive interrupt low
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// 0x3 -> drive interrupt high
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#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000)
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#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29)
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#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28)
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#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW"
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#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO1_CTRL_INOVER
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// 0x0 -> don't invert the peri input
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// 0x1 -> invert the peri input
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// 0x2 -> drive peri input low
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// 0x3 -> drive peri input high
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#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000)
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#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17)
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#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16)
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#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW"
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#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO1_CTRL_OEOVER
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// 0x0 -> drive output enable from peripheral signal selected by funcsel
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// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
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// 0x2 -> disable output
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// 0x3 -> enable output
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#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x0000c000)
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#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(15)
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#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(14)
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#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW"
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#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
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#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO1_CTRL_OUTOVER
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// 0x0 -> drive output from peripheral signal selected by funcsel
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// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
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// 0x2 -> drive output low
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// 0x3 -> drive output high
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#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00003000)
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#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(13)
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#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(12)
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#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW"
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#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO1_CTRL_FUNCSEL
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// Description : 0-31 -> selects pin function according to the gpio table
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// 31 == NULL
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// 0x00 -> jtag_tms
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// 0x01 -> spi0_ss_n
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// 0x02 -> uart0_rx
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// 0x03 -> i2c0_scl
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// 0x04 -> pwm_b_0
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// 0x05 -> siob_proc_1
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// 0x06 -> pio0_1
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// 0x07 -> pio1_1
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// 0x08 -> pio2_1
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// 0x09 -> coresight_traceclk
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// 0x0a -> usb_muxing_vbus_detect
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// 0x1f -> null
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW"
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIOB_PROC_1 _u(0x05)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO2_1 _u(0x08)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACECLK _u(0x09)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
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#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
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// =============================================================================
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// Register : IO_BANK0_GPIO2_STATUS
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#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010)
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#define IO_BANK0_GPIO2_STATUS_BITS _u(0x04022200)
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#define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC
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// Description : interrupt to processors, after override is applied
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#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0)
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#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000)
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#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26)
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#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26)
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#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO2_STATUS_INFROMPAD
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// Description : input signal from pad, before filtering and override are
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// applied
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#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000)
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#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17)
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#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17)
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#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO2_STATUS_OETOPAD
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// Description : output enable to pad after register override is applied
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#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000)
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#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13)
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#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13)
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#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD
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// Description : output signal to pad after register override is applied
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#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200)
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#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9)
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#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9)
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#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_GPIO2_CTRL
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#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014)
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#define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003f01f)
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#define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO2_CTRL_IRQOVER
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// 0x0 -> don't invert the interrupt
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// 0x1 -> invert the interrupt
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// 0x2 -> drive interrupt low
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// 0x3 -> drive interrupt high
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#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000)
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#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29)
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#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28)
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#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW"
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#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO2_CTRL_INOVER
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// 0x0 -> don't invert the peri input
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// 0x1 -> invert the peri input
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// 0x2 -> drive peri input low
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// 0x3 -> drive peri input high
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#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000)
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#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17)
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#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16)
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#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW"
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#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO2_CTRL_OEOVER
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// 0x0 -> drive output enable from peripheral signal selected by funcsel
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// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
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// 0x2 -> disable output
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// 0x3 -> enable output
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#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x0000c000)
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#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(15)
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#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(14)
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#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW"
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#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
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#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO2_CTRL_OUTOVER
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// 0x0 -> drive output from peripheral signal selected by funcsel
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// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
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// 0x2 -> drive output low
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// 0x3 -> drive output high
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#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00003000)
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#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(13)
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#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(12)
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#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW"
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#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO2_CTRL_FUNCSEL
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// Description : 0-31 -> selects pin function according to the gpio table
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// 31 == NULL
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// 0x00 -> jtag_tdi
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// 0x01 -> spi0_sclk
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// 0x02 -> uart0_cts
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// 0x03 -> i2c1_sda
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// 0x04 -> pwm_a_1
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// 0x05 -> siob_proc_2
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// 0x06 -> pio0_2
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// 0x07 -> pio1_2
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// 0x08 -> pio2_2
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// 0x09 -> coresight_tracedata_0
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// 0x0a -> usb_muxing_vbus_en
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// 0x0b -> uart0_tx
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// 0x1f -> null
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW"
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIOB_PROC_2 _u(0x05)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO2_2 _u(0x08)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_0 _u(0x09)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b)
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#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
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// =============================================================================
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// Register : IO_BANK0_GPIO3_STATUS
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#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018)
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#define IO_BANK0_GPIO3_STATUS_BITS _u(0x04022200)
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#define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC
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// Description : interrupt to processors, after override is applied
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#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0)
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#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000)
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#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26)
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#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26)
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#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO3_STATUS_INFROMPAD
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// Description : input signal from pad, before filtering and override are
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// applied
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#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000)
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#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17)
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#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17)
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#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO3_STATUS_OETOPAD
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// Description : output enable to pad after register override is applied
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#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000)
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#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13)
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#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13)
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#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD
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// Description : output signal to pad after register override is applied
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#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200)
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#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9)
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#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9)
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#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_GPIO3_CTRL
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#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c)
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#define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003f01f)
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#define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO3_CTRL_IRQOVER
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// 0x0 -> don't invert the interrupt
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// 0x1 -> invert the interrupt
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// 0x2 -> drive interrupt low
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// 0x3 -> drive interrupt high
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#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000)
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#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29)
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#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28)
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#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW"
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#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO3_CTRL_INOVER
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// 0x0 -> don't invert the peri input
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// 0x1 -> invert the peri input
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// 0x2 -> drive peri input low
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// 0x3 -> drive peri input high
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#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000)
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#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17)
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#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16)
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#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW"
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#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO3_CTRL_OEOVER
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// 0x0 -> drive output enable from peripheral signal selected by funcsel
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// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
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// 0x2 -> disable output
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// 0x3 -> enable output
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#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x0000c000)
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#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(15)
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#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(14)
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#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW"
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#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
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#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO3_CTRL_OUTOVER
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// 0x0 -> drive output from peripheral signal selected by funcsel
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// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
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// 0x2 -> drive output low
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// 0x3 -> drive output high
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#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00003000)
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#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(13)
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#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(12)
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#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW"
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#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO3_CTRL_FUNCSEL
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// Description : 0-31 -> selects pin function according to the gpio table
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// 31 == NULL
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// 0x00 -> jtag_tdo
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// 0x01 -> spi0_tx
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// 0x02 -> uart0_rts
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// 0x03 -> i2c1_scl
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// 0x04 -> pwm_b_1
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// 0x05 -> siob_proc_3
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// 0x06 -> pio0_3
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// 0x07 -> pio1_3
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// 0x08 -> pio2_3
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// 0x09 -> coresight_tracedata_1
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// 0x0a -> usb_muxing_overcurr_detect
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// 0x0b -> uart0_rx
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// 0x1f -> null
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW"
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIOB_PROC_3 _u(0x05)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO2_3 _u(0x08)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_1 _u(0x09)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b)
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#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
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// =============================================================================
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// Register : IO_BANK0_GPIO4_STATUS
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#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020)
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#define IO_BANK0_GPIO4_STATUS_BITS _u(0x04022200)
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#define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC
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// Description : interrupt to processors, after override is applied
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#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0)
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#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000)
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#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26)
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#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26)
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#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO4_STATUS_INFROMPAD
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// Description : input signal from pad, before filtering and override are
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// applied
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#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000)
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#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17)
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#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17)
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#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO4_STATUS_OETOPAD
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// Description : output enable to pad after register override is applied
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#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000)
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#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13)
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#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13)
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#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD
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// Description : output signal to pad after register override is applied
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#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200)
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#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9)
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#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9)
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#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_GPIO4_CTRL
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#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024)
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#define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO4_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29)
|
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#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
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#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
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#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
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#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO4_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0)
|
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#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000)
|
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#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17)
|
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#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16)
|
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#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW"
|
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#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
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#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
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#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2)
|
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#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO4_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
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// 0x2 -> disable output
|
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// 0x3 -> enable output
|
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#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0)
|
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#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x0000c000)
|
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#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(15)
|
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#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(14)
|
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#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW"
|
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#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
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#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
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#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
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#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO4_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
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#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0)
|
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#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(12)
|
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#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
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#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO4_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_rx
|
|
// 0x02 -> uart1_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_2
|
|
// 0x05 -> siob_proc_4
|
|
// 0x06 -> pio0_4
|
|
// 0x07 -> pio1_4
|
|
// 0x08 -> pio2_4
|
|
// 0x09 -> coresight_tracedata_2
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIOB_PROC_4 _u(0x05)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO2_4 _u(0x08)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_2 _u(0x09)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO5_STATUS
|
|
#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028)
|
|
#define IO_BANK0_GPIO5_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO5_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO5_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO5_CTRL
|
|
#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c)
|
|
#define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO5_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO5_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO5_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO5_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO5_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_ss_n
|
|
// 0x02 -> uart1_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_2
|
|
// 0x05 -> siob_proc_5
|
|
// 0x06 -> pio0_5
|
|
// 0x07 -> pio1_5
|
|
// 0x08 -> pio2_5
|
|
// 0x09 -> coresight_tracedata_3
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIOB_PROC_5 _u(0x05)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO2_5 _u(0x08)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_CORESIGHT_TRACEDATA_3 _u(0x09)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO6_STATUS
|
|
#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030)
|
|
#define IO_BANK0_GPIO6_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO6_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO6_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO6_CTRL
|
|
#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034)
|
|
#define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO6_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO6_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO6_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO6_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO6_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_sclk
|
|
// 0x02 -> uart1_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_3
|
|
// 0x05 -> siob_proc_6
|
|
// 0x06 -> pio0_6
|
|
// 0x07 -> pio1_6
|
|
// 0x08 -> pio2_6
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x0b -> uart1_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIOB_PROC_6 _u(0x05)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO2_6 _u(0x08)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b)
|
|
#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO7_STATUS
|
|
#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038)
|
|
#define IO_BANK0_GPIO7_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO7_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO7_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO7_CTRL
|
|
#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c)
|
|
#define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO7_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO7_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO7_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO7_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO7_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_tx
|
|
// 0x02 -> uart1_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_3
|
|
// 0x05 -> siob_proc_7
|
|
// 0x06 -> pio0_7
|
|
// 0x07 -> pio1_7
|
|
// 0x08 -> pio2_7
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x0b -> uart1_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIOB_PROC_7 _u(0x05)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO2_7 _u(0x08)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO8_STATUS
|
|
#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040)
|
|
#define IO_BANK0_GPIO8_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO8_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO8_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO8_CTRL
|
|
#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044)
|
|
#define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO8_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO8_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO8_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO8_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO8_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_rx
|
|
// 0x02 -> uart1_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_4
|
|
// 0x05 -> siob_proc_8
|
|
// 0x06 -> pio0_8
|
|
// 0x07 -> pio1_8
|
|
// 0x08 -> pio2_8
|
|
// 0x09 -> xip_ss_n_1
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIOB_PROC_8 _u(0x05)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO2_8 _u(0x08)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO9_STATUS
|
|
#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048)
|
|
#define IO_BANK0_GPIO9_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO9_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO9_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO9_CTRL
|
|
#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c)
|
|
#define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO9_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO9_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO9_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO9_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO9_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_ss_n
|
|
// 0x02 -> uart1_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_4
|
|
// 0x05 -> siob_proc_9
|
|
// 0x06 -> pio0_9
|
|
// 0x07 -> pio1_9
|
|
// 0x08 -> pio2_9
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIOB_PROC_9 _u(0x05)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO2_9 _u(0x08)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO10_STATUS
|
|
#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050)
|
|
#define IO_BANK0_GPIO10_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO10_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO10_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO10_CTRL
|
|
#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054)
|
|
#define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO10_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO10_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO10_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO10_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO10_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_sclk
|
|
// 0x02 -> uart1_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_5
|
|
// 0x05 -> siob_proc_10
|
|
// 0x06 -> pio0_10
|
|
// 0x07 -> pio1_10
|
|
// 0x08 -> pio2_10
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x0b -> uart1_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIOB_PROC_10 _u(0x05)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO2_10 _u(0x08)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b)
|
|
#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO11_STATUS
|
|
#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058)
|
|
#define IO_BANK0_GPIO11_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO11_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO11_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO11_CTRL
|
|
#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c)
|
|
#define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO11_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO11_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO11_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO11_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO11_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_tx
|
|
// 0x02 -> uart1_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_5
|
|
// 0x05 -> siob_proc_11
|
|
// 0x06 -> pio0_11
|
|
// 0x07 -> pio1_11
|
|
// 0x08 -> pio2_11
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x0b -> uart1_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIOB_PROC_11 _u(0x05)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO2_11 _u(0x08)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO12_STATUS
|
|
#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060)
|
|
#define IO_BANK0_GPIO12_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO12_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO12_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO12_CTRL
|
|
#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064)
|
|
#define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO12_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO12_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO12_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO12_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO12_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x00 -> hstx_0
|
|
// 0x01 -> spi1_rx
|
|
// 0x02 -> uart0_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_6
|
|
// 0x05 -> siob_proc_12
|
|
// 0x06 -> pio0_12
|
|
// 0x07 -> pio1_12
|
|
// 0x08 -> pio2_12
|
|
// 0x09 -> clocks_gpin_0
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_HSTX_0 _u(0x00)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIOB_PROC_12 _u(0x05)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO2_12 _u(0x08)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO13_STATUS
|
|
#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068)
|
|
#define IO_BANK0_GPIO13_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO13_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO13_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO13_CTRL
|
|
#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c)
|
|
#define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO13_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO13_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO13_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO13_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO13_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x00 -> hstx_1
|
|
// 0x01 -> spi1_ss_n
|
|
// 0x02 -> uart0_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_6
|
|
// 0x05 -> siob_proc_13
|
|
// 0x06 -> pio0_13
|
|
// 0x07 -> pio1_13
|
|
// 0x08 -> pio2_13
|
|
// 0x09 -> clocks_gpout_0
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_HSTX_1 _u(0x00)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIOB_PROC_13 _u(0x05)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO2_13 _u(0x08)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO14_STATUS
|
|
#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070)
|
|
#define IO_BANK0_GPIO14_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO14_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO14_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO14_CTRL
|
|
#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074)
|
|
#define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO14_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO14_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO14_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO14_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO14_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x00 -> hstx_2
|
|
// 0x01 -> spi1_sclk
|
|
// 0x02 -> uart0_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_7
|
|
// 0x05 -> siob_proc_14
|
|
// 0x06 -> pio0_14
|
|
// 0x07 -> pio1_14
|
|
// 0x08 -> pio2_14
|
|
// 0x09 -> clocks_gpin_1
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x0b -> uart0_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_HSTX_2 _u(0x00)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIOB_PROC_14 _u(0x05)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO2_14 _u(0x08)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b)
|
|
#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO15_STATUS
|
|
#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078)
|
|
#define IO_BANK0_GPIO15_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO15_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO15_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO15_CTRL
|
|
#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c)
|
|
#define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO15_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO15_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO15_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO15_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO15_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x00 -> hstx_3
|
|
// 0x01 -> spi1_tx
|
|
// 0x02 -> uart0_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_7
|
|
// 0x05 -> siob_proc_15
|
|
// 0x06 -> pio0_15
|
|
// 0x07 -> pio1_15
|
|
// 0x08 -> pio2_15
|
|
// 0x09 -> clocks_gpout_1
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x0b -> uart0_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_HSTX_3 _u(0x00)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIOB_PROC_15 _u(0x05)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO2_15 _u(0x08)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x09)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO16_STATUS
|
|
#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080)
|
|
#define IO_BANK0_GPIO16_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO16_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO16_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO16_CTRL
|
|
#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084)
|
|
#define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO16_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO16_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO16_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO16_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO16_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x00 -> hstx_4
|
|
// 0x01 -> spi0_rx
|
|
// 0x02 -> uart0_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_0
|
|
// 0x05 -> siob_proc_16
|
|
// 0x06 -> pio0_16
|
|
// 0x07 -> pio1_16
|
|
// 0x08 -> pio2_16
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_HSTX_4 _u(0x00)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIOB_PROC_16 _u(0x05)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO2_16 _u(0x08)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO17_STATUS
|
|
#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088)
|
|
#define IO_BANK0_GPIO17_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO17_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO17_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO17_CTRL
|
|
#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c)
|
|
#define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO17_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO17_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO17_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO17_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO17_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x00 -> hstx_5
|
|
// 0x01 -> spi0_ss_n
|
|
// 0x02 -> uart0_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_0
|
|
// 0x05 -> siob_proc_17
|
|
// 0x06 -> pio0_17
|
|
// 0x07 -> pio1_17
|
|
// 0x08 -> pio2_17
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_HSTX_5 _u(0x00)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIOB_PROC_17 _u(0x05)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO2_17 _u(0x08)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO18_STATUS
|
|
#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090)
|
|
#define IO_BANK0_GPIO18_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO18_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO18_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO18_CTRL
|
|
#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094)
|
|
#define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO18_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO18_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO18_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO18_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO18_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x00 -> hstx_6
|
|
// 0x01 -> spi0_sclk
|
|
// 0x02 -> uart0_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_1
|
|
// 0x05 -> siob_proc_18
|
|
// 0x06 -> pio0_18
|
|
// 0x07 -> pio1_18
|
|
// 0x08 -> pio2_18
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x0b -> uart0_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_HSTX_6 _u(0x00)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIOB_PROC_18 _u(0x05)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO2_18 _u(0x08)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b)
|
|
#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO19_STATUS
|
|
#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098)
|
|
#define IO_BANK0_GPIO19_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO19_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO19_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO19_CTRL
|
|
#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c)
|
|
#define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO19_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO19_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO19_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO19_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO19_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x00 -> hstx_7
|
|
// 0x01 -> spi0_tx
|
|
// 0x02 -> uart0_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_1
|
|
// 0x05 -> siob_proc_19
|
|
// 0x06 -> pio0_19
|
|
// 0x07 -> pio1_19
|
|
// 0x08 -> pio2_19
|
|
// 0x09 -> xip_ss_n_1
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x0b -> uart0_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_HSTX_7 _u(0x00)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIOB_PROC_19 _u(0x05)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO2_19 _u(0x08)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO20_STATUS
|
|
#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0)
|
|
#define IO_BANK0_GPIO20_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO20_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO20_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO20_CTRL
|
|
#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4)
|
|
#define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO20_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO20_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO20_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO20_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO20_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_rx
|
|
// 0x02 -> uart1_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_2
|
|
// 0x05 -> siob_proc_20
|
|
// 0x06 -> pio0_20
|
|
// 0x07 -> pio1_20
|
|
// 0x08 -> pio2_20
|
|
// 0x09 -> clocks_gpin_0
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIOB_PROC_20 _u(0x05)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO2_20 _u(0x08)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x09)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO21_STATUS
|
|
#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8)
|
|
#define IO_BANK0_GPIO21_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO21_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO21_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO21_CTRL
|
|
#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac)
|
|
#define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO21_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO21_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO21_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO21_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO21_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_ss_n
|
|
// 0x02 -> uart1_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_2
|
|
// 0x05 -> siob_proc_21
|
|
// 0x06 -> pio0_21
|
|
// 0x07 -> pio1_21
|
|
// 0x08 -> pio2_21
|
|
// 0x09 -> clocks_gpout_0
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIOB_PROC_21 _u(0x05)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO2_21 _u(0x08)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x09)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO22_STATUS
|
|
#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0)
|
|
#define IO_BANK0_GPIO22_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO22_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO22_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
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// Register : IO_BANK0_GPIO22_CTRL
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#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4)
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#define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003f01f)
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#define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO22_CTRL_IRQOVER
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// 0x0 -> don't invert the interrupt
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// 0x1 -> invert the interrupt
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// 0x2 -> drive interrupt low
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// 0x3 -> drive interrupt high
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#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000)
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#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29)
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#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28)
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#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW"
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#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO22_CTRL_INOVER
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// 0x0 -> don't invert the peri input
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// 0x1 -> invert the peri input
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// 0x2 -> drive peri input low
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// 0x3 -> drive peri input high
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#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000)
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#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17)
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#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16)
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#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW"
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#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO22_CTRL_OEOVER
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// 0x0 -> drive output enable from peripheral signal selected by funcsel
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// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
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// 0x2 -> disable output
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// 0x3 -> enable output
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#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x0000c000)
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#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(15)
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#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(14)
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#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW"
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#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
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#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO22_CTRL_OUTOVER
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// 0x0 -> drive output from peripheral signal selected by funcsel
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// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
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// 0x2 -> drive output low
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// 0x3 -> drive output high
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#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00003000)
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#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(13)
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#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(12)
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#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW"
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#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO22_CTRL_FUNCSEL
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// Description : 0-31 -> selects pin function according to the gpio table
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// 31 == NULL
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// 0x01 -> spi0_sclk
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// 0x02 -> uart1_cts
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// 0x03 -> i2c1_sda
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// 0x04 -> pwm_a_3
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// 0x05 -> siob_proc_22
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// 0x06 -> pio0_22
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// 0x07 -> pio1_22
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// 0x08 -> pio2_22
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// 0x09 -> clocks_gpin_1
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// 0x0a -> usb_muxing_vbus_detect
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// 0x0b -> uart1_tx
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// 0x1f -> null
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW"
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIOB_PROC_22 _u(0x05)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO2_22 _u(0x08)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x09)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b)
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#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
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// =============================================================================
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// Register : IO_BANK0_GPIO23_STATUS
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#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8)
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#define IO_BANK0_GPIO23_STATUS_BITS _u(0x04022200)
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#define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC
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// Description : interrupt to processors, after override is applied
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#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0)
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#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000)
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#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26)
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#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26)
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#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO23_STATUS_INFROMPAD
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// Description : input signal from pad, before filtering and override are
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// applied
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#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000)
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#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17)
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#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17)
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#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO23_STATUS_OETOPAD
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// Description : output enable to pad after register override is applied
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#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000)
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#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13)
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#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13)
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#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD
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// Description : output signal to pad after register override is applied
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#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200)
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#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9)
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#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9)
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#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_GPIO23_CTRL
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#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc)
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#define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003f01f)
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#define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO23_CTRL_IRQOVER
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// 0x0 -> don't invert the interrupt
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// 0x1 -> invert the interrupt
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// 0x2 -> drive interrupt low
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// 0x3 -> drive interrupt high
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#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000)
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#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29)
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#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28)
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#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW"
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#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO23_CTRL_INOVER
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// 0x0 -> don't invert the peri input
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// 0x1 -> invert the peri input
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// 0x2 -> drive peri input low
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// 0x3 -> drive peri input high
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#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000)
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#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17)
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#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16)
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#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW"
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#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO23_CTRL_OEOVER
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// 0x0 -> drive output enable from peripheral signal selected by funcsel
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// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
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// 0x2 -> disable output
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// 0x3 -> enable output
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#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x0000c000)
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#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(15)
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#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(14)
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#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW"
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#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
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#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO23_CTRL_OUTOVER
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// 0x0 -> drive output from peripheral signal selected by funcsel
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// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
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// 0x2 -> drive output low
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// 0x3 -> drive output high
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#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00003000)
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#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(13)
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#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(12)
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#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW"
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#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO23_CTRL_FUNCSEL
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// Description : 0-31 -> selects pin function according to the gpio table
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// 31 == NULL
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// 0x01 -> spi0_tx
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// 0x02 -> uart1_rts
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// 0x03 -> i2c1_scl
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// 0x04 -> pwm_b_3
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// 0x05 -> siob_proc_23
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// 0x06 -> pio0_23
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// 0x07 -> pio1_23
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// 0x08 -> pio2_23
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// 0x09 -> clocks_gpout_1
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// 0x0a -> usb_muxing_vbus_en
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// 0x0b -> uart1_rx
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// 0x1f -> null
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW"
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIOB_PROC_23 _u(0x05)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO2_23 _u(0x08)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x09)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b)
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#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
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// =============================================================================
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// Register : IO_BANK0_GPIO24_STATUS
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#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0)
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#define IO_BANK0_GPIO24_STATUS_BITS _u(0x04022200)
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#define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC
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// Description : interrupt to processors, after override is applied
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#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0)
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#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000)
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#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26)
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#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26)
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#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO24_STATUS_INFROMPAD
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// Description : input signal from pad, before filtering and override are
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// applied
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#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000)
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#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17)
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#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17)
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#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO24_STATUS_OETOPAD
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// Description : output enable to pad after register override is applied
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#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000)
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#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13)
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#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13)
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#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD
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// Description : output signal to pad after register override is applied
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#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0)
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#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200)
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#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9)
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#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9)
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#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_GPIO24_CTRL
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#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4)
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#define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003f01f)
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#define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO24_CTRL_IRQOVER
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// 0x0 -> don't invert the interrupt
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// 0x1 -> invert the interrupt
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// 0x2 -> drive interrupt low
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// 0x3 -> drive interrupt high
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#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000)
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#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29)
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#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28)
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#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW"
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#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2)
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#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_GPIO24_CTRL_INOVER
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// 0x0 -> don't invert the peri input
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// 0x1 -> invert the peri input
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// 0x2 -> drive peri input low
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// 0x3 -> drive peri input high
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#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0)
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#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000)
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#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17)
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#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16)
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#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW"
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#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0)
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#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1)
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#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO24_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO24_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO24_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_rx
|
|
// 0x02 -> uart1_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_4
|
|
// 0x05 -> siob_proc_24
|
|
// 0x06 -> pio0_24
|
|
// 0x07 -> pio1_24
|
|
// 0x08 -> pio2_24
|
|
// 0x09 -> clocks_gpout_2
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIOB_PROC_24 _u(0x05)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO2_24 _u(0x08)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x09)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO25_STATUS
|
|
#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8)
|
|
#define IO_BANK0_GPIO25_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO25_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO25_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO25_CTRL
|
|
#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc)
|
|
#define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO25_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO25_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO25_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO25_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO25_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_ss_n
|
|
// 0x02 -> uart1_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_4
|
|
// 0x05 -> siob_proc_25
|
|
// 0x06 -> pio0_25
|
|
// 0x07 -> pio1_25
|
|
// 0x08 -> pio2_25
|
|
// 0x09 -> clocks_gpout_3
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIOB_PROC_25 _u(0x05)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO2_25 _u(0x08)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x09)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO26_STATUS
|
|
#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0)
|
|
#define IO_BANK0_GPIO26_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO26_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO26_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO26_CTRL
|
|
#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4)
|
|
#define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO26_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO26_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO26_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO26_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO26_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_sclk
|
|
// 0x02 -> uart1_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_5
|
|
// 0x05 -> siob_proc_26
|
|
// 0x06 -> pio0_26
|
|
// 0x07 -> pio1_26
|
|
// 0x08 -> pio2_26
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x0b -> uart1_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIOB_PROC_26 _u(0x05)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO2_26 _u(0x08)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b)
|
|
#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO27_STATUS
|
|
#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8)
|
|
#define IO_BANK0_GPIO27_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO27_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO27_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO27_CTRL
|
|
#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc)
|
|
#define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO27_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO27_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO27_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO27_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO27_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_tx
|
|
// 0x02 -> uart1_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_5
|
|
// 0x05 -> siob_proc_27
|
|
// 0x06 -> pio0_27
|
|
// 0x07 -> pio1_27
|
|
// 0x08 -> pio2_27
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x0b -> uart1_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIOB_PROC_27 _u(0x05)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO2_27 _u(0x08)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO28_STATUS
|
|
#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0)
|
|
#define IO_BANK0_GPIO28_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO28_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO28_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO28_CTRL
|
|
#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4)
|
|
#define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO28_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO28_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO28_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO28_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO28_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_rx
|
|
// 0x02 -> uart0_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_6
|
|
// 0x05 -> siob_proc_28
|
|
// 0x06 -> pio0_28
|
|
// 0x07 -> pio1_28
|
|
// 0x08 -> pio2_28
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIOB_PROC_28 _u(0x05)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO2_28 _u(0x08)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO29_STATUS
|
|
#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8)
|
|
#define IO_BANK0_GPIO29_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO29_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO29_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO29_CTRL
|
|
#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec)
|
|
#define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO29_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO29_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO29_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO29_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO29_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_ss_n
|
|
// 0x02 -> uart0_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_6
|
|
// 0x05 -> siob_proc_29
|
|
// 0x06 -> pio0_29
|
|
// 0x07 -> pio1_29
|
|
// 0x08 -> pio2_29
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIOB_PROC_29 _u(0x05)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO2_29 _u(0x08)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO30_STATUS
|
|
#define IO_BANK0_GPIO30_STATUS_OFFSET _u(0x000000f0)
|
|
#define IO_BANK0_GPIO30_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO30_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO30_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO30_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO30_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO30_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO30_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO30_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO30_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO30_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO30_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO30_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO30_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO30_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO30_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO30_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO30_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO30_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO30_CTRL
|
|
#define IO_BANK0_GPIO30_CTRL_OFFSET _u(0x000000f4)
|
|
#define IO_BANK0_GPIO30_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO30_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO30_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO30_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO30_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO30_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO30_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO30_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO30_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO30_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO30_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO30_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO30_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO30_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO30_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO30_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO30_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO30_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO30_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO30_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO30_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO30_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO30_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO30_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO30_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO30_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO30_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO30_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO30_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO30_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO30_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_sclk
|
|
// 0x02 -> uart0_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_7
|
|
// 0x05 -> siob_proc_30
|
|
// 0x06 -> pio0_30
|
|
// 0x07 -> pio1_30
|
|
// 0x08 -> pio2_30
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x0b -> uart0_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_SIOB_PROC_30 _u(0x05)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO0_30 _u(0x06)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO1_30 _u(0x07)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_PIO2_30 _u(0x08)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b)
|
|
#define IO_BANK0_GPIO30_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO31_STATUS
|
|
#define IO_BANK0_GPIO31_STATUS_OFFSET _u(0x000000f8)
|
|
#define IO_BANK0_GPIO31_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO31_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO31_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO31_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO31_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO31_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO31_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO31_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO31_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO31_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO31_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO31_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO31_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO31_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO31_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO31_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO31_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO31_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO31_CTRL
|
|
#define IO_BANK0_GPIO31_CTRL_OFFSET _u(0x000000fc)
|
|
#define IO_BANK0_GPIO31_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO31_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO31_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO31_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO31_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO31_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO31_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO31_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO31_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO31_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO31_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO31_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO31_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO31_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO31_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO31_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO31_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO31_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO31_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO31_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO31_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO31_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO31_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO31_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO31_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO31_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO31_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO31_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO31_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO31_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO31_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_tx
|
|
// 0x02 -> uart0_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_7
|
|
// 0x05 -> siob_proc_31
|
|
// 0x06 -> pio0_31
|
|
// 0x07 -> pio1_31
|
|
// 0x08 -> pio2_31
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x0b -> uart0_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_SIOB_PROC_31 _u(0x05)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO0_31 _u(0x06)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO1_31 _u(0x07)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_PIO2_31 _u(0x08)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO31_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO32_STATUS
|
|
#define IO_BANK0_GPIO32_STATUS_OFFSET _u(0x00000100)
|
|
#define IO_BANK0_GPIO32_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO32_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO32_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO32_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO32_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO32_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO32_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO32_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO32_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO32_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO32_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO32_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO32_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO32_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO32_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO32_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO32_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO32_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO32_CTRL
|
|
#define IO_BANK0_GPIO32_CTRL_OFFSET _u(0x00000104)
|
|
#define IO_BANK0_GPIO32_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO32_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO32_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO32_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO32_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO32_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO32_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO32_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO32_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO32_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO32_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO32_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO32_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO32_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO32_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO32_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO32_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO32_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO32_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO32_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO32_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO32_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO32_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO32_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO32_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO32_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO32_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO32_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO32_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO32_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO32_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_rx
|
|
// 0x02 -> uart0_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_8
|
|
// 0x05 -> siob_proc_32
|
|
// 0x06 -> pio0_32
|
|
// 0x07 -> pio1_32
|
|
// 0x08 -> pio2_32
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_SIOB_PROC_32 _u(0x05)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO0_32 _u(0x06)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO1_32 _u(0x07)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_PIO2_32 _u(0x08)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO32_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO33_STATUS
|
|
#define IO_BANK0_GPIO33_STATUS_OFFSET _u(0x00000108)
|
|
#define IO_BANK0_GPIO33_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO33_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO33_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO33_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO33_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO33_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO33_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO33_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO33_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO33_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO33_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO33_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO33_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO33_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO33_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO33_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO33_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO33_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO33_CTRL
|
|
#define IO_BANK0_GPIO33_CTRL_OFFSET _u(0x0000010c)
|
|
#define IO_BANK0_GPIO33_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO33_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO33_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO33_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO33_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO33_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO33_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO33_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO33_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO33_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO33_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO33_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO33_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO33_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO33_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO33_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO33_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO33_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO33_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO33_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO33_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO33_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO33_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO33_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO33_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO33_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO33_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO33_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO33_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO33_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO33_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_ss_n
|
|
// 0x02 -> uart0_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_8
|
|
// 0x05 -> siob_proc_33
|
|
// 0x06 -> pio0_33
|
|
// 0x07 -> pio1_33
|
|
// 0x08 -> pio2_33
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_SIOB_PROC_33 _u(0x05)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO0_33 _u(0x06)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO1_33 _u(0x07)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_PIO2_33 _u(0x08)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO33_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO34_STATUS
|
|
#define IO_BANK0_GPIO34_STATUS_OFFSET _u(0x00000110)
|
|
#define IO_BANK0_GPIO34_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO34_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO34_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO34_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO34_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO34_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO34_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO34_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO34_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO34_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO34_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO34_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO34_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO34_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO34_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO34_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO34_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO34_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO34_CTRL
|
|
#define IO_BANK0_GPIO34_CTRL_OFFSET _u(0x00000114)
|
|
#define IO_BANK0_GPIO34_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO34_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO34_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO34_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO34_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO34_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO34_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO34_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO34_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO34_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO34_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO34_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO34_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO34_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO34_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO34_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO34_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO34_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO34_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO34_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO34_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO34_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO34_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO34_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO34_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO34_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO34_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO34_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO34_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO34_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO34_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_sclk
|
|
// 0x02 -> uart0_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_9
|
|
// 0x05 -> siob_proc_34
|
|
// 0x06 -> pio0_34
|
|
// 0x07 -> pio1_34
|
|
// 0x08 -> pio2_34
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x0b -> uart0_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_SIOB_PROC_34 _u(0x05)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO0_34 _u(0x06)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO1_34 _u(0x07)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_PIO2_34 _u(0x08)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b)
|
|
#define IO_BANK0_GPIO34_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO35_STATUS
|
|
#define IO_BANK0_GPIO35_STATUS_OFFSET _u(0x00000118)
|
|
#define IO_BANK0_GPIO35_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO35_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO35_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO35_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO35_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO35_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO35_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO35_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO35_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO35_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO35_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO35_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO35_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO35_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO35_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO35_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO35_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO35_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO35_CTRL
|
|
#define IO_BANK0_GPIO35_CTRL_OFFSET _u(0x0000011c)
|
|
#define IO_BANK0_GPIO35_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO35_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO35_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO35_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO35_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO35_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO35_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO35_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO35_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO35_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO35_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO35_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO35_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO35_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO35_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO35_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO35_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO35_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO35_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO35_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO35_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO35_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO35_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO35_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO35_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO35_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO35_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO35_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO35_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO35_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO35_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_tx
|
|
// 0x02 -> uart0_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_9
|
|
// 0x05 -> siob_proc_35
|
|
// 0x06 -> pio0_35
|
|
// 0x07 -> pio1_35
|
|
// 0x08 -> pio2_35
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x0b -> uart0_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_SIOB_PROC_35 _u(0x05)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO0_35 _u(0x06)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO1_35 _u(0x07)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_PIO2_35 _u(0x08)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO35_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO36_STATUS
|
|
#define IO_BANK0_GPIO36_STATUS_OFFSET _u(0x00000120)
|
|
#define IO_BANK0_GPIO36_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO36_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO36_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO36_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO36_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO36_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO36_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO36_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO36_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO36_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO36_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO36_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO36_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO36_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO36_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO36_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO36_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO36_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO36_CTRL
|
|
#define IO_BANK0_GPIO36_CTRL_OFFSET _u(0x00000124)
|
|
#define IO_BANK0_GPIO36_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO36_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO36_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO36_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO36_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO36_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO36_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO36_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO36_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO36_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO36_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO36_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO36_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO36_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO36_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO36_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO36_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO36_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO36_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO36_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO36_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO36_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO36_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO36_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO36_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO36_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO36_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO36_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO36_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO36_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO36_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_rx
|
|
// 0x02 -> uart1_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_10
|
|
// 0x05 -> siob_proc_36
|
|
// 0x06 -> pio0_36
|
|
// 0x07 -> pio1_36
|
|
// 0x08 -> pio2_36
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_SIOB_PROC_36 _u(0x05)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO0_36 _u(0x06)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO1_36 _u(0x07)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_PIO2_36 _u(0x08)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO36_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO37_STATUS
|
|
#define IO_BANK0_GPIO37_STATUS_OFFSET _u(0x00000128)
|
|
#define IO_BANK0_GPIO37_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO37_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO37_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO37_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO37_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO37_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO37_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO37_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO37_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO37_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO37_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO37_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO37_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO37_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO37_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO37_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO37_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO37_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO37_CTRL
|
|
#define IO_BANK0_GPIO37_CTRL_OFFSET _u(0x0000012c)
|
|
#define IO_BANK0_GPIO37_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO37_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO37_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO37_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO37_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO37_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO37_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO37_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO37_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO37_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO37_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO37_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO37_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO37_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO37_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO37_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO37_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO37_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO37_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO37_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO37_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO37_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO37_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO37_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO37_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO37_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO37_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO37_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO37_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO37_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO37_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_ss_n
|
|
// 0x02 -> uart1_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_10
|
|
// 0x05 -> siob_proc_37
|
|
// 0x06 -> pio0_37
|
|
// 0x07 -> pio1_37
|
|
// 0x08 -> pio2_37
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_SIOB_PROC_37 _u(0x05)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO0_37 _u(0x06)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO1_37 _u(0x07)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_PIO2_37 _u(0x08)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO37_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO38_STATUS
|
|
#define IO_BANK0_GPIO38_STATUS_OFFSET _u(0x00000130)
|
|
#define IO_BANK0_GPIO38_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO38_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO38_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO38_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO38_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO38_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO38_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO38_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO38_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO38_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO38_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO38_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO38_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO38_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO38_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO38_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO38_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO38_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO38_CTRL
|
|
#define IO_BANK0_GPIO38_CTRL_OFFSET _u(0x00000134)
|
|
#define IO_BANK0_GPIO38_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO38_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO38_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO38_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO38_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO38_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO38_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO38_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO38_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO38_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO38_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO38_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO38_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO38_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO38_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO38_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO38_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO38_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO38_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO38_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO38_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO38_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO38_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO38_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO38_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO38_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO38_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO38_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO38_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO38_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO38_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_sclk
|
|
// 0x02 -> uart1_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_11
|
|
// 0x05 -> siob_proc_38
|
|
// 0x06 -> pio0_38
|
|
// 0x07 -> pio1_38
|
|
// 0x08 -> pio2_38
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x0b -> uart1_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_SIOB_PROC_38 _u(0x05)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO0_38 _u(0x06)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO1_38 _u(0x07)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_PIO2_38 _u(0x08)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b)
|
|
#define IO_BANK0_GPIO38_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO39_STATUS
|
|
#define IO_BANK0_GPIO39_STATUS_OFFSET _u(0x00000138)
|
|
#define IO_BANK0_GPIO39_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO39_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO39_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO39_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO39_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO39_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO39_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO39_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO39_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO39_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO39_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO39_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO39_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO39_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO39_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO39_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO39_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO39_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO39_CTRL
|
|
#define IO_BANK0_GPIO39_CTRL_OFFSET _u(0x0000013c)
|
|
#define IO_BANK0_GPIO39_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO39_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO39_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO39_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO39_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO39_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO39_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO39_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO39_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO39_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO39_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO39_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO39_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO39_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO39_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO39_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO39_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO39_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO39_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO39_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO39_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO39_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO39_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO39_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO39_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO39_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO39_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO39_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO39_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO39_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO39_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi0_tx
|
|
// 0x02 -> uart1_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_11
|
|
// 0x05 -> siob_proc_39
|
|
// 0x06 -> pio0_39
|
|
// 0x07 -> pio1_39
|
|
// 0x08 -> pio2_39
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x0b -> uart1_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_SIOB_PROC_39 _u(0x05)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO0_39 _u(0x06)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO1_39 _u(0x07)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_PIO2_39 _u(0x08)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO39_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO40_STATUS
|
|
#define IO_BANK0_GPIO40_STATUS_OFFSET _u(0x00000140)
|
|
#define IO_BANK0_GPIO40_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO40_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO40_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO40_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO40_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO40_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO40_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO40_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO40_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO40_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO40_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO40_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO40_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO40_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO40_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO40_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO40_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO40_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO40_CTRL
|
|
#define IO_BANK0_GPIO40_CTRL_OFFSET _u(0x00000144)
|
|
#define IO_BANK0_GPIO40_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO40_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO40_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO40_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO40_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO40_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO40_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO40_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO40_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO40_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO40_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO40_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO40_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO40_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO40_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO40_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO40_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO40_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO40_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO40_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO40_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO40_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO40_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO40_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO40_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO40_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO40_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO40_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO40_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO40_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO40_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_rx
|
|
// 0x02 -> uart1_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_8
|
|
// 0x05 -> siob_proc_40
|
|
// 0x06 -> pio0_40
|
|
// 0x07 -> pio1_40
|
|
// 0x08 -> pio2_40
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PWM_A_8 _u(0x04)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_SIOB_PROC_40 _u(0x05)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO0_40 _u(0x06)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO1_40 _u(0x07)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_PIO2_40 _u(0x08)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO40_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO41_STATUS
|
|
#define IO_BANK0_GPIO41_STATUS_OFFSET _u(0x00000148)
|
|
#define IO_BANK0_GPIO41_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO41_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO41_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO41_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO41_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO41_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO41_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO41_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO41_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO41_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO41_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO41_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO41_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO41_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO41_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO41_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO41_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO41_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO41_CTRL
|
|
#define IO_BANK0_GPIO41_CTRL_OFFSET _u(0x0000014c)
|
|
#define IO_BANK0_GPIO41_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO41_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO41_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO41_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO41_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO41_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO41_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO41_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO41_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO41_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO41_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO41_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO41_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO41_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO41_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO41_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO41_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO41_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO41_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO41_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO41_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO41_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO41_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO41_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO41_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO41_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO41_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO41_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO41_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO41_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO41_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_ss_n
|
|
// 0x02 -> uart1_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_8
|
|
// 0x05 -> siob_proc_41
|
|
// 0x06 -> pio0_41
|
|
// 0x07 -> pio1_41
|
|
// 0x08 -> pio2_41
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PWM_B_8 _u(0x04)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_SIOB_PROC_41 _u(0x05)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO0_41 _u(0x06)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO1_41 _u(0x07)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_PIO2_41 _u(0x08)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO41_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO42_STATUS
|
|
#define IO_BANK0_GPIO42_STATUS_OFFSET _u(0x00000150)
|
|
#define IO_BANK0_GPIO42_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO42_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO42_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO42_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO42_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO42_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO42_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO42_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO42_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO42_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO42_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO42_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO42_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO42_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO42_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO42_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO42_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO42_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO42_CTRL
|
|
#define IO_BANK0_GPIO42_CTRL_OFFSET _u(0x00000154)
|
|
#define IO_BANK0_GPIO42_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO42_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO42_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO42_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO42_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO42_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO42_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO42_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO42_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO42_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO42_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO42_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO42_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO42_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO42_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO42_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO42_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO42_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO42_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO42_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO42_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO42_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO42_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO42_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO42_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO42_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO42_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO42_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO42_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO42_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO42_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_sclk
|
|
// 0x02 -> uart1_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_9
|
|
// 0x05 -> siob_proc_42
|
|
// 0x06 -> pio0_42
|
|
// 0x07 -> pio1_42
|
|
// 0x08 -> pio2_42
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x0b -> uart1_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO42_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO42_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO42_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO42_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
|
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PWM_A_9 _u(0x04)
|
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_SIOB_PROC_42 _u(0x05)
|
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO0_42 _u(0x06)
|
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO1_42 _u(0x07)
|
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_PIO2_42 _u(0x08)
|
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x0b)
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#define IO_BANK0_GPIO42_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
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|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO43_STATUS
|
|
#define IO_BANK0_GPIO43_STATUS_OFFSET _u(0x00000158)
|
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#define IO_BANK0_GPIO43_STATUS_BITS _u(0x04022200)
|
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#define IO_BANK0_GPIO43_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO43_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
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#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_LSB _u(26)
|
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#define IO_BANK0_GPIO43_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO43_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO43_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO43_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO43_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO43_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO43_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO43_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO43_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO43_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO43_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO43_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO43_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO43_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO43_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO43_CTRL
|
|
#define IO_BANK0_GPIO43_CTRL_OFFSET _u(0x0000015c)
|
|
#define IO_BANK0_GPIO43_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO43_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO43_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO43_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO43_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO43_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO43_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO43_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO43_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO43_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO43_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO43_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO43_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO43_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO43_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO43_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO43_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO43_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO43_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO43_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO43_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO43_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO43_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO43_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO43_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO43_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO43_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO43_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO43_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO43_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO43_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_tx
|
|
// 0x02 -> uart1_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_9
|
|
// 0x05 -> siob_proc_43
|
|
// 0x06 -> pio0_43
|
|
// 0x07 -> pio1_43
|
|
// 0x08 -> pio2_43
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x0b -> uart1_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PWM_B_9 _u(0x04)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_SIOB_PROC_43 _u(0x05)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO0_43 _u(0x06)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO1_43 _u(0x07)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_PIO2_43 _u(0x08)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO43_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO44_STATUS
|
|
#define IO_BANK0_GPIO44_STATUS_OFFSET _u(0x00000160)
|
|
#define IO_BANK0_GPIO44_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO44_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO44_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO44_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO44_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO44_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO44_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO44_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO44_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO44_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO44_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO44_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO44_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO44_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO44_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO44_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO44_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO44_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO44_CTRL
|
|
#define IO_BANK0_GPIO44_CTRL_OFFSET _u(0x00000164)
|
|
#define IO_BANK0_GPIO44_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO44_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO44_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO44_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO44_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO44_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO44_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO44_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO44_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO44_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO44_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO44_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO44_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO44_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO44_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO44_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO44_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO44_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO44_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO44_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO44_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO44_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO44_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO44_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO44_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO44_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO44_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO44_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO44_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO44_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO44_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_rx
|
|
// 0x02 -> uart0_tx
|
|
// 0x03 -> i2c0_sda
|
|
// 0x04 -> pwm_a_10
|
|
// 0x05 -> siob_proc_44
|
|
// 0x06 -> pio0_44
|
|
// 0x07 -> pio1_44
|
|
// 0x08 -> pio2_44
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PWM_A_10 _u(0x04)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_SIOB_PROC_44 _u(0x05)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO0_44 _u(0x06)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO1_44 _u(0x07)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_PIO2_44 _u(0x08)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO44_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO45_STATUS
|
|
#define IO_BANK0_GPIO45_STATUS_OFFSET _u(0x00000168)
|
|
#define IO_BANK0_GPIO45_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO45_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO45_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO45_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO45_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO45_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO45_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO45_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO45_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO45_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO45_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO45_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO45_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO45_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO45_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO45_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO45_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO45_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO45_CTRL
|
|
#define IO_BANK0_GPIO45_CTRL_OFFSET _u(0x0000016c)
|
|
#define IO_BANK0_GPIO45_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO45_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO45_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO45_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO45_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO45_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO45_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO45_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO45_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO45_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO45_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO45_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO45_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO45_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO45_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO45_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO45_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO45_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO45_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO45_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO45_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO45_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO45_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO45_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO45_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO45_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO45_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO45_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO45_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO45_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO45_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_ss_n
|
|
// 0x02 -> uart0_rx
|
|
// 0x03 -> i2c0_scl
|
|
// 0x04 -> pwm_b_10
|
|
// 0x05 -> siob_proc_45
|
|
// 0x06 -> pio0_45
|
|
// 0x07 -> pio1_45
|
|
// 0x08 -> pio2_45
|
|
// 0x0a -> usb_muxing_overcurr_detect
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PWM_B_10 _u(0x04)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_SIOB_PROC_45 _u(0x05)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO0_45 _u(0x06)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO1_45 _u(0x07)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_PIO2_45 _u(0x08)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO45_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO46_STATUS
|
|
#define IO_BANK0_GPIO46_STATUS_OFFSET _u(0x00000170)
|
|
#define IO_BANK0_GPIO46_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO46_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO46_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO46_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO46_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO46_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO46_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO46_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO46_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO46_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO46_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO46_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO46_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO46_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO46_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO46_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO46_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO46_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO46_CTRL
|
|
#define IO_BANK0_GPIO46_CTRL_OFFSET _u(0x00000174)
|
|
#define IO_BANK0_GPIO46_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO46_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO46_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO46_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO46_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO46_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO46_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO46_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO46_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO46_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO46_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO46_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO46_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO46_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO46_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO46_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO46_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO46_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO46_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO46_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO46_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO46_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO46_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO46_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO46_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO46_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO46_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO46_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO46_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO46_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO46_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_sclk
|
|
// 0x02 -> uart0_cts
|
|
// 0x03 -> i2c1_sda
|
|
// 0x04 -> pwm_a_11
|
|
// 0x05 -> siob_proc_46
|
|
// 0x06 -> pio0_46
|
|
// 0x07 -> pio1_46
|
|
// 0x08 -> pio2_46
|
|
// 0x0a -> usb_muxing_vbus_detect
|
|
// 0x0b -> uart0_tx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PWM_A_11 _u(0x04)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_SIOB_PROC_46 _u(0x05)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO0_46 _u(0x06)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO1_46 _u(0x07)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_PIO2_46 _u(0x08)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x0a)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x0b)
|
|
#define IO_BANK0_GPIO46_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO47_STATUS
|
|
#define IO_BANK0_GPIO47_STATUS_OFFSET _u(0x00000178)
|
|
#define IO_BANK0_GPIO47_STATUS_BITS _u(0x04022200)
|
|
#define IO_BANK0_GPIO47_STATUS_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO47_STATUS_IRQTOPROC
|
|
// Description : interrupt to processors, after override is applied
|
|
#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_BITS _u(0x04000000)
|
|
#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_MSB _u(26)
|
|
#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_LSB _u(26)
|
|
#define IO_BANK0_GPIO47_STATUS_IRQTOPROC_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO47_STATUS_INFROMPAD
|
|
// Description : input signal from pad, before filtering and override are
|
|
// applied
|
|
#define IO_BANK0_GPIO47_STATUS_INFROMPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO47_STATUS_INFROMPAD_BITS _u(0x00020000)
|
|
#define IO_BANK0_GPIO47_STATUS_INFROMPAD_MSB _u(17)
|
|
#define IO_BANK0_GPIO47_STATUS_INFROMPAD_LSB _u(17)
|
|
#define IO_BANK0_GPIO47_STATUS_INFROMPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO47_STATUS_OETOPAD
|
|
// Description : output enable to pad after register override is applied
|
|
#define IO_BANK0_GPIO47_STATUS_OETOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO47_STATUS_OETOPAD_BITS _u(0x00002000)
|
|
#define IO_BANK0_GPIO47_STATUS_OETOPAD_MSB _u(13)
|
|
#define IO_BANK0_GPIO47_STATUS_OETOPAD_LSB _u(13)
|
|
#define IO_BANK0_GPIO47_STATUS_OETOPAD_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO47_STATUS_OUTTOPAD
|
|
// Description : output signal to pad after register override is applied
|
|
#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_BITS _u(0x00000200)
|
|
#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_MSB _u(9)
|
|
#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_LSB _u(9)
|
|
#define IO_BANK0_GPIO47_STATUS_OUTTOPAD_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_GPIO47_CTRL
|
|
#define IO_BANK0_GPIO47_CTRL_OFFSET _u(0x0000017c)
|
|
#define IO_BANK0_GPIO47_CTRL_BITS _u(0x3003f01f)
|
|
#define IO_BANK0_GPIO47_CTRL_RESET _u(0x0000001f)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO47_CTRL_IRQOVER
|
|
// 0x0 -> don't invert the interrupt
|
|
// 0x1 -> invert the interrupt
|
|
// 0x2 -> drive interrupt low
|
|
// 0x3 -> drive interrupt high
|
|
#define IO_BANK0_GPIO47_CTRL_IRQOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO47_CTRL_IRQOVER_BITS _u(0x30000000)
|
|
#define IO_BANK0_GPIO47_CTRL_IRQOVER_MSB _u(29)
|
|
#define IO_BANK0_GPIO47_CTRL_IRQOVER_LSB _u(28)
|
|
#define IO_BANK0_GPIO47_CTRL_IRQOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO47_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO47_CTRL_INOVER
|
|
// 0x0 -> don't invert the peri input
|
|
// 0x1 -> invert the peri input
|
|
// 0x2 -> drive peri input low
|
|
// 0x3 -> drive peri input high
|
|
#define IO_BANK0_GPIO47_CTRL_INOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO47_CTRL_INOVER_BITS _u(0x00030000)
|
|
#define IO_BANK0_GPIO47_CTRL_INOVER_MSB _u(17)
|
|
#define IO_BANK0_GPIO47_CTRL_INOVER_LSB _u(16)
|
|
#define IO_BANK0_GPIO47_CTRL_INOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO47_CTRL_INOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO47_CTRL_OEOVER
|
|
// 0x0 -> drive output enable from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output enable from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> disable output
|
|
// 0x3 -> enable output
|
|
#define IO_BANK0_GPIO47_CTRL_OEOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO47_CTRL_OEOVER_BITS _u(0x0000c000)
|
|
#define IO_BANK0_GPIO47_CTRL_OEOVER_MSB _u(15)
|
|
#define IO_BANK0_GPIO47_CTRL_OEOVER_LSB _u(14)
|
|
#define IO_BANK0_GPIO47_CTRL_OEOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
|
|
#define IO_BANK0_GPIO47_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO47_CTRL_OUTOVER
|
|
// 0x0 -> drive output from peripheral signal selected by funcsel
|
|
// 0x1 -> drive output from inverse of peripheral signal selected by funcsel
|
|
// 0x2 -> drive output low
|
|
// 0x3 -> drive output high
|
|
#define IO_BANK0_GPIO47_CTRL_OUTOVER_RESET _u(0x0)
|
|
#define IO_BANK0_GPIO47_CTRL_OUTOVER_BITS _u(0x00003000)
|
|
#define IO_BANK0_GPIO47_CTRL_OUTOVER_MSB _u(13)
|
|
#define IO_BANK0_GPIO47_CTRL_OUTOVER_LSB _u(12)
|
|
#define IO_BANK0_GPIO47_CTRL_OUTOVER_ACCESS "RW"
|
|
#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
|
|
#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
|
|
#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_LOW _u(0x2)
|
|
#define IO_BANK0_GPIO47_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_GPIO47_CTRL_FUNCSEL
|
|
// Description : 0-31 -> selects pin function according to the gpio table
|
|
// 31 == NULL
|
|
// 0x01 -> spi1_tx
|
|
// 0x02 -> uart0_rts
|
|
// 0x03 -> i2c1_scl
|
|
// 0x04 -> pwm_b_11
|
|
// 0x05 -> siob_proc_47
|
|
// 0x06 -> pio0_47
|
|
// 0x07 -> pio1_47
|
|
// 0x08 -> pio2_47
|
|
// 0x09 -> xip_ss_n_1
|
|
// 0x0a -> usb_muxing_vbus_en
|
|
// 0x0b -> uart0_rx
|
|
// 0x1f -> null
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_RESET _u(0x1f)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_BITS _u(0x0000001f)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_MSB _u(4)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_LSB _u(0)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_ACCESS "RW"
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PWM_B_11 _u(0x04)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_SIOB_PROC_47 _u(0x05)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO0_47 _u(0x06)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO1_47 _u(0x07)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_PIO2_47 _u(0x08)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_XIP_SS_N_1 _u(0x09)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x0a)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x0b)
|
|
#define IO_BANK0_GPIO47_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_PROC0_SECURE0
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_OFFSET _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_BITS _u(0x80000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_MSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_LSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO31_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_BITS _u(0x40000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_MSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_LSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO30_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_BITS _u(0x20000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_MSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_LSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO29_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_BITS _u(0x10000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_MSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_LSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO28_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_BITS _u(0x08000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_MSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_LSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO27_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_BITS _u(0x04000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_MSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_LSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO26_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_BITS _u(0x02000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_MSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_LSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO25_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_BITS _u(0x01000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_MSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_LSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO24_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_BITS _u(0x00800000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_MSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_LSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO23_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_BITS _u(0x00400000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_MSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_LSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO22_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_BITS _u(0x00200000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_MSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_LSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO21_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_BITS _u(0x00100000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_MSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_LSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO20_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_BITS _u(0x00080000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_MSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_LSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO19_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_BITS _u(0x00040000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_MSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_LSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO18_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_BITS _u(0x00020000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_MSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_LSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO17_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_BITS _u(0x00010000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_MSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_LSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO16_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO15_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO14_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO13_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO12_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO11_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO10_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO9_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO8_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO7_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO6_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO5_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO4_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO3_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO2_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE0_GPIO0_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_PROC0_SECURE1
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_OFFSET _u(0x00000204)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_BITS _u(0x0000ffff)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO47_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO46_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO45_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO44_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO43_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO42_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO41_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO40_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO39_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO38_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO37_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO36_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO35_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO34_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO33_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_SECURE1_GPIO32_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_OFFSET _u(0x00000208)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_BITS _u(0x80000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_MSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_LSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO31_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_BITS _u(0x40000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_MSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_LSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO30_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_BITS _u(0x20000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_MSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_LSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO29_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_BITS _u(0x10000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_MSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_LSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO28_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_BITS _u(0x08000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_MSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_LSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO27_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_BITS _u(0x04000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_MSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_LSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO26_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_BITS _u(0x02000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_MSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_LSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO25_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_BITS _u(0x01000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_MSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_LSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO24_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_BITS _u(0x00800000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_MSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_LSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO23_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_BITS _u(0x00400000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_MSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_LSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO22_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_BITS _u(0x00200000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_MSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_LSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO21_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_BITS _u(0x00100000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_MSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_LSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO20_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_BITS _u(0x00080000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_MSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_LSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO19_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_BITS _u(0x00040000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_MSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_LSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO18_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_BITS _u(0x00020000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_MSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_LSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO17_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_BITS _u(0x00010000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_MSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_LSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO16_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO15_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO14_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO13_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO12_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO11_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO10_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO9_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO8_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO7_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO6_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO5_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO4_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO3_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO2_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_GPIO0_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_OFFSET _u(0x0000020c)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_BITS _u(0x0000ffff)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO47_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO46_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO45_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO44_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO43_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO42_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO41_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO40_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO39_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO38_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO37_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO36_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO35_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_MSB _u(2)
|
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_LSB _u(2)
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO34_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_BITS _u(0x00000002)
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_MSB _u(1)
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_LSB _u(1)
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO33_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_BITS _u(0x00000001)
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_MSB _u(0)
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_LSB _u(0)
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#define IO_BANK0_IRQSUMMARY_PROC0_NONSECURE1_GPIO32_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_IRQSUMMARY_PROC1_SECURE0
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_OFFSET _u(0x00000210)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_BITS _u(0xffffffff)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_BITS _u(0x80000000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_MSB _u(31)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_LSB _u(31)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO31_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_BITS _u(0x40000000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_MSB _u(30)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_LSB _u(30)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO30_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_BITS _u(0x20000000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_MSB _u(29)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_LSB _u(29)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO29_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_BITS _u(0x10000000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_MSB _u(28)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_LSB _u(28)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO28_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_BITS _u(0x08000000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_MSB _u(27)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_LSB _u(27)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO27_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_BITS _u(0x04000000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_MSB _u(26)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_LSB _u(26)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO26_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_BITS _u(0x02000000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_MSB _u(25)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_LSB _u(25)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO25_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_BITS _u(0x01000000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_MSB _u(24)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_LSB _u(24)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO24_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_BITS _u(0x00800000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_MSB _u(23)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_LSB _u(23)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO23_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_BITS _u(0x00400000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_MSB _u(22)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_LSB _u(22)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO22_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_BITS _u(0x00200000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_MSB _u(21)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_LSB _u(21)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO21_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_BITS _u(0x00100000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_MSB _u(20)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_LSB _u(20)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO20_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_BITS _u(0x00080000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_MSB _u(19)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_LSB _u(19)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO19_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_BITS _u(0x00040000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_MSB _u(18)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_LSB _u(18)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO18_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_BITS _u(0x00020000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_MSB _u(17)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_LSB _u(17)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO17_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_BITS _u(0x00010000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_MSB _u(16)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_LSB _u(16)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO16_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_BITS _u(0x00008000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_MSB _u(15)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_LSB _u(15)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO15_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_BITS _u(0x00004000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_MSB _u(14)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_LSB _u(14)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO14_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_BITS _u(0x00002000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_MSB _u(13)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_LSB _u(13)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO13_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_BITS _u(0x00001000)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_MSB _u(12)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_LSB _u(12)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO12_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_BITS _u(0x00000800)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_MSB _u(11)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_LSB _u(11)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO11_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_BITS _u(0x00000400)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_MSB _u(10)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_LSB _u(10)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO10_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_BITS _u(0x00000200)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_MSB _u(9)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_LSB _u(9)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO9_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_BITS _u(0x00000100)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_MSB _u(8)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_LSB _u(8)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO8_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_BITS _u(0x00000080)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_MSB _u(7)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_LSB _u(7)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO7_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_BITS _u(0x00000040)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_MSB _u(6)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_LSB _u(6)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO6_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_BITS _u(0x00000020)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_MSB _u(5)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_LSB _u(5)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO5_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_RESET _u(0x0)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_BITS _u(0x00000010)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_MSB _u(4)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_LSB _u(4)
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO4_ACCESS "RO"
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|
// -----------------------------------------------------------------------------
|
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_RESET _u(0x0)
|
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_BITS _u(0x00000008)
|
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_MSB _u(3)
|
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_LSB _u(3)
|
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO3_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
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// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_RESET _u(0x0)
|
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_BITS _u(0x00000004)
|
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_MSB _u(2)
|
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO2_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_RESET _u(0x0)
|
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_BITS _u(0x00000002)
|
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#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE0_GPIO0_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_PROC1_SECURE1
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_OFFSET _u(0x00000214)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_BITS _u(0x0000ffff)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO47_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO46_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO45_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO44_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO43_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO42_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO41_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO40_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO39_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO38_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO37_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO36_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO35_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO34_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO33_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_SECURE1_GPIO32_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_OFFSET _u(0x00000218)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_BITS _u(0x80000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_MSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_LSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO31_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_BITS _u(0x40000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_MSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_LSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO30_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_BITS _u(0x20000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_MSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_LSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO29_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_BITS _u(0x10000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_MSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_LSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO28_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_BITS _u(0x08000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_MSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_LSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO27_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_BITS _u(0x04000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_MSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_LSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO26_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_BITS _u(0x02000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_MSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_LSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO25_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_BITS _u(0x01000000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_MSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_LSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO24_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_BITS _u(0x00800000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_MSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_LSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO23_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_BITS _u(0x00400000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_MSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_LSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO22_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_BITS _u(0x00200000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_MSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_LSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO21_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_BITS _u(0x00100000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_MSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_LSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO20_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_BITS _u(0x00080000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_MSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_LSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO19_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_BITS _u(0x00040000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_MSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_LSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO18_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_BITS _u(0x00020000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_MSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_LSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO17_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_BITS _u(0x00010000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_MSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_LSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO16_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO15_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO14_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO13_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO12_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO11_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO10_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO9_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO8_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO7_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO6_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO5_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO4_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO3_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO2_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_GPIO0_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_OFFSET _u(0x0000021c)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_BITS _u(0x0000ffff)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO47_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO46_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO45_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO44_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO43_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO42_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO41_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO40_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO39_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO38_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO37_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO36_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO35_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO34_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO33_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_PROC1_NONSECURE1_GPIO32_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_OFFSET _u(0x00000220)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_BITS _u(0x80000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_MSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_LSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO31_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_BITS _u(0x40000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_MSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_LSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO30_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_BITS _u(0x20000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_MSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_LSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO29_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_BITS _u(0x10000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_MSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_LSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO28_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_BITS _u(0x08000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_MSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_LSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO27_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_BITS _u(0x04000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_MSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_LSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO26_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_BITS _u(0x02000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_MSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_LSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO25_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_BITS _u(0x01000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_MSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_LSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO24_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_BITS _u(0x00800000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_MSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_LSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO23_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_BITS _u(0x00400000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_MSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_LSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO22_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_BITS _u(0x00200000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_MSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_LSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO21_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_BITS _u(0x00100000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_MSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_LSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO20_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_BITS _u(0x00080000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_MSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_LSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO19_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_BITS _u(0x00040000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_MSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_LSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO18_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_BITS _u(0x00020000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_MSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_LSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO17_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_BITS _u(0x00010000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_MSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_LSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO16_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO15_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO14_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO13_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO12_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO11_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO10_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO9_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO8_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO7_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO6_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO5_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO4_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO3_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO2_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_GPIO0_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_OFFSET _u(0x00000224)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_BITS _u(0x0000ffff)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO47_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO46_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO45_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO44_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO43_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO42_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO41_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO40_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO39_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO38_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO37_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO36_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO35_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO34_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO33_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE1_GPIO32_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_OFFSET _u(0x00000228)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_BITS _u(0x80000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_MSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_LSB _u(31)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO31_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_BITS _u(0x40000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_MSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_LSB _u(30)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO30_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_BITS _u(0x20000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_MSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_LSB _u(29)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO29_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_BITS _u(0x10000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_MSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_LSB _u(28)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO28_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_BITS _u(0x08000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_MSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_LSB _u(27)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO27_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_BITS _u(0x04000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_MSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_LSB _u(26)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO26_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_BITS _u(0x02000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_MSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_LSB _u(25)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO25_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_BITS _u(0x01000000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_MSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_LSB _u(24)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO24_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_BITS _u(0x00800000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_MSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_LSB _u(23)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO23_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_BITS _u(0x00400000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_MSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_LSB _u(22)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO22_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_BITS _u(0x00200000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_MSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_LSB _u(21)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO21_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_BITS _u(0x00100000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_MSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_LSB _u(20)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO20_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_BITS _u(0x00080000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_MSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_LSB _u(19)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO19_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_BITS _u(0x00040000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_MSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_LSB _u(18)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO18_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_BITS _u(0x00020000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_MSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_LSB _u(17)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO17_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_BITS _u(0x00010000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_MSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_LSB _u(16)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO16_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO15_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO14_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO13_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO12_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO11_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO10_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO9_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO8_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO7_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO6_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO5_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO4_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO3_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO2_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO1_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_GPIO0_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_OFFSET _u(0x0000022c)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_BITS _u(0x0000ffff)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_BITS _u(0x00008000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_MSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_LSB _u(15)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO47_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_BITS _u(0x00004000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_MSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_LSB _u(14)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO46_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_BITS _u(0x00002000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_MSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_LSB _u(13)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO45_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_BITS _u(0x00001000)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_MSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_LSB _u(12)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO44_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_BITS _u(0x00000800)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_MSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_LSB _u(11)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO43_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_BITS _u(0x00000400)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_MSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_LSB _u(10)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO42_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_BITS _u(0x00000200)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_MSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_LSB _u(9)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO41_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_BITS _u(0x00000100)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_MSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_LSB _u(8)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO40_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_BITS _u(0x00000080)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_MSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_LSB _u(7)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO39_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_BITS _u(0x00000040)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_MSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_LSB _u(6)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO38_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_BITS _u(0x00000020)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_MSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_LSB _u(5)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO37_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_BITS _u(0x00000010)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_MSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_LSB _u(4)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO36_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_BITS _u(0x00000008)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_MSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_LSB _u(3)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO35_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_BITS _u(0x00000004)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_MSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_LSB _u(2)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO34_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_BITS _u(0x00000002)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_MSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_LSB _u(1)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO33_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_RESET _u(0x0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_BITS _u(0x00000001)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_MSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_LSB _u(0)
|
|
#define IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE1_GPIO32_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_INTR0
|
|
// Description : Raw Interrupts
|
|
#define IO_BANK0_INTR0_OFFSET _u(0x00000230)
|
|
#define IO_BANK0_INTR0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_INTR0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_INTR1
|
|
// Description : Raw Interrupts
|
|
#define IO_BANK0_INTR1_OFFSET _u(0x00000234)
|
|
#define IO_BANK0_INTR1_BITS _u(0xffffffff)
|
|
#define IO_BANK0_INTR1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_INTR2
|
|
// Description : Raw Interrupts
|
|
#define IO_BANK0_INTR2_OFFSET _u(0x00000238)
|
|
#define IO_BANK0_INTR2_BITS _u(0xffffffff)
|
|
#define IO_BANK0_INTR2_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_INTR3
|
|
// Description : Raw Interrupts
|
|
#define IO_BANK0_INTR3_OFFSET _u(0x0000023c)
|
|
#define IO_BANK0_INTR3_BITS _u(0xffffffff)
|
|
#define IO_BANK0_INTR3_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO31_EDGE_HIGH
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO31_EDGE_LOW
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_INTR3_GPIO31_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO31_LEVEL_HIGH
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO31_LEVEL_LOW
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_INTR3_GPIO31_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO30_EDGE_HIGH
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO30_EDGE_LOW
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_INTR3_GPIO30_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO30_LEVEL_HIGH
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO30_LEVEL_LOW
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_INTR3_GPIO30_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_INTR4
|
|
// Description : Raw Interrupts
|
|
#define IO_BANK0_INTR4_OFFSET _u(0x00000240)
|
|
#define IO_BANK0_INTR4_BITS _u(0xffffffff)
|
|
#define IO_BANK0_INTR4_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO39_EDGE_HIGH
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO39_EDGE_LOW
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_INTR4_GPIO39_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO39_LEVEL_HIGH
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO39_LEVEL_LOW
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_INTR4_GPIO39_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO38_EDGE_HIGH
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO38_EDGE_LOW
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_INTR4_GPIO38_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO38_LEVEL_HIGH
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO38_LEVEL_LOW
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_INTR4_GPIO38_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO37_EDGE_HIGH
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO37_EDGE_LOW
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_INTR4_GPIO37_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO37_LEVEL_HIGH
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO37_LEVEL_LOW
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_INTR4_GPIO37_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO36_EDGE_HIGH
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO36_EDGE_LOW
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_INTR4_GPIO36_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO36_LEVEL_HIGH
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO36_LEVEL_LOW
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_INTR4_GPIO36_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO35_EDGE_HIGH
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO35_EDGE_LOW
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_INTR4_GPIO35_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO35_LEVEL_HIGH
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO35_LEVEL_LOW
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_INTR4_GPIO35_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO34_EDGE_HIGH
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO34_EDGE_LOW
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_INTR4_GPIO34_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO34_LEVEL_HIGH
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO34_LEVEL_LOW
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_INTR4_GPIO34_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO33_EDGE_HIGH
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO33_EDGE_LOW
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_INTR4_GPIO33_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_INTR4_GPIO33_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_INTR4_GPIO32_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_INTR4_GPIO32_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_INTR5
|
|
// Description : Raw Interrupts
|
|
#define IO_BANK0_INTR5_OFFSET _u(0x00000244)
|
|
#define IO_BANK0_INTR5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_INTR5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_INTR5_GPIO47_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_INTR5_GPIO47_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_INTR5_GPIO46_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_INTR5_GPIO46_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_INTR5_GPIO45_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_INTR5_GPIO45_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO44_EDGE_HIGH
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO44_EDGE_LOW
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_INTR5_GPIO44_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO44_LEVEL_HIGH
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO44_LEVEL_LOW
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_INTR5_GPIO44_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO43_EDGE_HIGH
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO43_EDGE_LOW
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_INTR5_GPIO43_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO43_LEVEL_HIGH
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO43_LEVEL_LOW
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_INTR5_GPIO43_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO42_EDGE_HIGH
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO42_EDGE_LOW
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_INTR5_GPIO42_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO42_LEVEL_HIGH
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO42_LEVEL_LOW
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_INTR5_GPIO42_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO41_EDGE_HIGH
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO41_EDGE_LOW
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_INTR5_GPIO41_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO41_LEVEL_HIGH
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO41_LEVEL_LOW
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_INTR5_GPIO41_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO40_EDGE_HIGH
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_HIGH_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO40_EDGE_LOW
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_INTR5_GPIO40_EDGE_LOW_ACCESS "WC"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO40_LEVEL_HIGH
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_INTR5_GPIO40_LEVEL_LOW
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_INTR5_GPIO40_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTE0
|
|
// Description : Interrupt Enable for proc0
|
|
#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000248)
|
|
#define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTE1
|
|
// Description : Interrupt Enable for proc0
|
|
#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x0000024c)
|
|
#define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25)
|
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#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_PROC0_INTE2
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// Description : Interrupt Enable for proc0
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#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000250)
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#define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff)
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#define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH
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|
#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
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|
// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW
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|
#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
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|
// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH
|
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#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
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// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTE3
|
|
// Description : Interrupt Enable for proc0
|
|
#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x00000254)
|
|
#define IO_BANK0_PROC0_INTE3_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTE4
|
|
// Description : Interrupt Enable for proc0
|
|
#define IO_BANK0_PROC0_INTE4_OFFSET _u(0x00000258)
|
|
#define IO_BANK0_PROC0_INTE4_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTE4_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTE5
|
|
// Description : Interrupt Enable for proc0
|
|
#define IO_BANK0_PROC0_INTE5_OFFSET _u(0x0000025c)
|
|
#define IO_BANK0_PROC0_INTE5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTE5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTF0
|
|
// Description : Interrupt Force for proc0
|
|
#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000260)
|
|
#define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12)
|
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#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_PROC0_INTF1
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// Description : Interrupt Force for proc0
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#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000264)
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#define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff)
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#define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTF2
|
|
// Description : Interrupt Force for proc0
|
|
#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000268)
|
|
#define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7)
|
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#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW
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#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_PROC0_INTF3
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// Description : Interrupt Force for proc0
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#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000026c)
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#define IO_BANK0_PROC0_INTF3_BITS _u(0xffffffff)
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#define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_PROC0_INTF3_GPIO31_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_PROC0_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC0_INTF3_GPIO30_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_PROC0_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW
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#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTF4
|
|
// Description : Interrupt Force for proc0
|
|
#define IO_BANK0_PROC0_INTF4_OFFSET _u(0x00000270)
|
|
#define IO_BANK0_PROC0_INTF4_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTF4_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTF5
|
|
// Description : Interrupt Force for proc0
|
|
#define IO_BANK0_PROC0_INTF5_OFFSET _u(0x00000274)
|
|
#define IO_BANK0_PROC0_INTF5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTF5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTS0
|
|
// Description : Interrupt status after masking & forcing for proc0
|
|
#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000278)
|
|
#define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTS1
|
|
// Description : Interrupt status after masking & forcing for proc0
|
|
#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x0000027c)
|
|
#define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTS2
|
|
// Description : Interrupt status after masking & forcing for proc0
|
|
#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000280)
|
|
#define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW
|
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#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_PROC0_INTS3
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// Description : Interrupt status after masking & forcing for proc0
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#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x00000284)
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#define IO_BANK0_PROC0_INTS3_BITS _u(0xffffffff)
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#define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_PROC0_INTS3_GPIO31_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_PROC0_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC0_INTS3_GPIO30_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH
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#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW
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#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTS4
|
|
// Description : Interrupt status after masking & forcing for proc0
|
|
#define IO_BANK0_PROC0_INTS4_OFFSET _u(0x00000288)
|
|
#define IO_BANK0_PROC0_INTS4_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTS4_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC0_INTS5
|
|
// Description : Interrupt status after masking & forcing for proc0
|
|
#define IO_BANK0_PROC0_INTS5_OFFSET _u(0x0000028c)
|
|
#define IO_BANK0_PROC0_INTS5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC0_INTS5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC0_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTE0
|
|
// Description : Interrupt Enable for proc1
|
|
#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000290)
|
|
#define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0)
|
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#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_PROC1_INTE1
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// Description : Interrupt Enable for proc1
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#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000294)
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#define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff)
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#define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW
|
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14)
|
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#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTE2
|
|
// Description : Interrupt Enable for proc1
|
|
#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000298)
|
|
#define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTE3
|
|
// Description : Interrupt Enable for proc1
|
|
#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000029c)
|
|
#define IO_BANK0_PROC1_INTE3_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW
|
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#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_PROC1_INTE4
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// Description : Interrupt Enable for proc1
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#define IO_BANK0_PROC1_INTE4_OFFSET _u(0x000002a0)
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#define IO_BANK0_PROC1_INTE4_BITS _u(0xffffffff)
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#define IO_BANK0_PROC1_INTE4_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_PROC1_INTE4_GPIO39_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_PROC1_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC1_INTE4_GPIO38_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_PROC1_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_PROC1_INTE4_GPIO37_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_PROC1_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_PROC1_INTE4_GPIO36_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_PROC1_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_PROC1_INTE4_GPIO35_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_PROC1_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_PROC1_INTE4_GPIO34_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_PROC1_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH
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#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW
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#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTE5
|
|
// Description : Interrupt Enable for proc1
|
|
#define IO_BANK0_PROC1_INTE5_OFFSET _u(0x000002a4)
|
|
#define IO_BANK0_PROC1_INTE5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTE5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTF0
|
|
// Description : Interrupt Force for proc1
|
|
#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x000002a8)
|
|
#define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTF1
|
|
// Description : Interrupt Force for proc1
|
|
#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x000002ac)
|
|
#define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31)
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|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30)
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|
#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29)
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|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTF2
|
|
// Description : Interrupt Force for proc1
|
|
#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x000002b0)
|
|
#define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTF3
|
|
// Description : Interrupt Force for proc1
|
|
#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x000002b4)
|
|
#define IO_BANK0_PROC1_INTF3_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
|
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#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_PROC1_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC1_INTF3_GPIO30_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_PROC1_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_PROC1_INTF4
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// Description : Interrupt Force for proc1
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#define IO_BANK0_PROC1_INTF4_OFFSET _u(0x000002b8)
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#define IO_BANK0_PROC1_INTF4_BITS _u(0xffffffff)
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#define IO_BANK0_PROC1_INTF4_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_PROC1_INTF4_GPIO39_EDGE_LOW_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
|
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// Field : IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW
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|
#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_PROC1_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
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|
// Field : IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH
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|
#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
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|
#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_MSB _u(26)
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|
#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC1_INTF4_GPIO38_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTF5
|
|
// Description : Interrupt Force for proc1
|
|
#define IO_BANK0_PROC1_INTF5_OFFSET _u(0x000002bc)
|
|
#define IO_BANK0_PROC1_INTF5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTF5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTS0
|
|
// Description : Interrupt status after masking & forcing for proc1
|
|
#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x000002c0)
|
|
#define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTS1
|
|
// Description : Interrupt status after masking & forcing for proc1
|
|
#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x000002c4)
|
|
#define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTS2
|
|
// Description : Interrupt status after masking & forcing for proc1
|
|
#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x000002c8)
|
|
#define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0)
|
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#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW
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#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_PROC1_INTS3
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// Description : Interrupt status after masking & forcing for proc1
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#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x000002cc)
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#define IO_BANK0_PROC1_INTS3_BITS _u(0xffffffff)
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#define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_PROC1_INTS3_GPIO31_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_PROC1_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_PROC1_INTS3_GPIO30_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_PROC1_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
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// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH
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#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13)
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|
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTS4
|
|
// Description : Interrupt status after masking & forcing for proc1
|
|
#define IO_BANK0_PROC1_INTS4_OFFSET _u(0x000002d0)
|
|
#define IO_BANK0_PROC1_INTS4_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTS4_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_PROC1_INTS5
|
|
// Description : Interrupt status after masking & forcing for proc1
|
|
#define IO_BANK0_PROC1_INTS5_OFFSET _u(0x000002d4)
|
|
#define IO_BANK0_PROC1_INTS5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_PROC1_INTS5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_PROC1_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTE0
|
|
// Description : Interrupt Enable for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x000002d8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0)
|
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#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
|
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#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1)
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|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
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|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTE1
|
|
// Description : Interrupt Enable for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x000002dc)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25)
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|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
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|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_DORMANT_WAKE_INTE2
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// Description : Interrupt Enable for dormant_wake
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#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x000002e0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff)
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#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTE3
|
|
// Description : Interrupt Enable for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x000002e4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO31_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO30_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_DORMANT_WAKE_INTE4
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// Description : Interrupt Enable for dormant_wake
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#define IO_BANK0_DORMANT_WAKE_INTE4_OFFSET _u(0x000002e8)
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#define IO_BANK0_DORMANT_WAKE_INTE4_BITS _u(0xffffffff)
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#define IO_BANK0_DORMANT_WAKE_INTE4_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO39_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO38_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO37_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO36_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO35_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW
|
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_RESET _u(0x0)
|
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
|
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_MSB _u(10)
|
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_MSB _u(9)
|
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_MSB _u(8)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO34_LEVEL_LOW_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_MSB _u(7)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_LSB _u(6)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_LSB _u(5)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO33_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_MSB _u(0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE4_GPIO32_LEVEL_LOW_ACCESS "RW"
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|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTE5
|
|
// Description : Interrupt Enable for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_OFFSET _u(0x000002ec)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_LSB _u(30)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_MSB _u(29)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_HIGH_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
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|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO47_LEVEL_LOW_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
|
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// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_HIGH_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_LSB _u(26)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_EDGE_LOW_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
|
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// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_MSB _u(25)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_HIGH_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_MSB _u(24)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_LSB _u(24)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO46_LEVEL_LOW_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_MSB _u(23)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_LSB _u(23)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
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#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_MSB _u(22)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_LSB _u(22)
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|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO45_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO44_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO43_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO42_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO41_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTE5_GPIO40_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTF0
|
|
// Description : Interrupt Force for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x000002f0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTF1
|
|
// Description : Interrupt Force for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x000002f4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTF2
|
|
// Description : Interrupt Force for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x000002f8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_DORMANT_WAKE_INTF3
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// Description : Interrupt Force for dormant_wake
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#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x000002fc)
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#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0xffffffff)
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#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO31_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO30_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH
|
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
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|
// -----------------------------------------------------------------------------
|
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22)
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|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22)
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|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
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// =============================================================================
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// Register : IO_BANK0_DORMANT_WAKE_INTF4
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// Description : Interrupt Force for dormant_wake
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#define IO_BANK0_DORMANT_WAKE_INTF4_OFFSET _u(0x00000300)
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#define IO_BANK0_DORMANT_WAKE_INTF4_BITS _u(0xffffffff)
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#define IO_BANK0_DORMANT_WAKE_INTF4_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO39_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO38_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO37_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_EDGE_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_HIGH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO36_LEVEL_LOW_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO35_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO34_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO33_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF4_GPIO32_LEVEL_LOW_ACCESS "RW"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTF5
|
|
// Description : Interrupt Force for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_OFFSET _u(0x00000304)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO47_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO46_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO45_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO44_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO43_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_LSB _u(11)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO42_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO41_LEVEL_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_MSB _u(2)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_EDGE_LOW_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_MSB _u(1)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_LSB _u(1)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_HIGH_ACCESS "RW"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_RESET _u(0x0)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_LSB _u(0)
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|
#define IO_BANK0_DORMANT_WAKE_INTF5_GPIO40_LEVEL_LOW_ACCESS "RW"
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|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTS0
|
|
// Description : Interrupt status after masking & forcing for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000308)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_DORMANT_WAKE_INTS1
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// Description : Interrupt status after masking & forcing for dormant_wake
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#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x0000030c)
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#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff)
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#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH
|
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19)
|
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW
|
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
|
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18)
|
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH
|
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#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTS2
|
|
// Description : Interrupt status after masking & forcing for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000310)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
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// =============================================================================
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// Register : IO_BANK0_DORMANT_WAKE_INTS3
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// Description : Interrupt status after masking & forcing for dormant_wake
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#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x00000314)
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#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0xffffffff)
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#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_BITS _u(0x80000000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_MSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_LSB _u(31)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_BITS _u(0x40000000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_MSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_LSB _u(30)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_BITS _u(0x20000000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_MSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_LSB _u(29)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_BITS _u(0x10000000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_MSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_LSB _u(28)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO31_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_BITS _u(0x08000000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_MSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_LSB _u(27)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_BITS _u(0x04000000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_MSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_LSB _u(26)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_BITS _u(0x02000000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_MSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_LSB _u(25)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_BITS _u(0x01000000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_MSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_LSB _u(24)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO30_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTS4
|
|
// Description : Interrupt status after masking & forcing for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_OFFSET _u(0x00000318)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO39_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO38_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_BITS _u(0x00100000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_MSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_LSB _u(20)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO37_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_BITS _u(0x00080000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_MSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_LSB _u(19)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_BITS _u(0x00040000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_MSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_LSB _u(18)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_BITS _u(0x00020000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_MSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_LSB _u(17)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_BITS _u(0x00010000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_MSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_LSB _u(16)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO36_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_BITS _u(0x00008000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_MSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_LSB _u(15)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_BITS _u(0x00004000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_MSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_LSB _u(14)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_BITS _u(0x00002000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_MSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_LSB _u(13)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_BITS _u(0x00001000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_MSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_LSB _u(12)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO35_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_BITS _u(0x00000800)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_MSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_LSB _u(11)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_BITS _u(0x00000400)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_MSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_LSB _u(10)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_BITS _u(0x00000200)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_MSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_LSB _u(9)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_BITS _u(0x00000100)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_MSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_LSB _u(8)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO34_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_BITS _u(0x00000080)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_MSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_LSB _u(7)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_BITS _u(0x00000040)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_MSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_LSB _u(6)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_BITS _u(0x00000020)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_MSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_LSB _u(5)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_BITS _u(0x00000010)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_MSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_LSB _u(4)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO33_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_BITS _u(0x00000008)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_MSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_LSB _u(3)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_BITS _u(0x00000004)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_MSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_LSB _u(2)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_BITS _u(0x00000002)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_MSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_LSB _u(1)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_BITS _u(0x00000001)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_MSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_LSB _u(0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS4_GPIO32_LEVEL_LOW_ACCESS "RO"
|
|
// =============================================================================
|
|
// Register : IO_BANK0_DORMANT_WAKE_INTS5
|
|
// Description : Interrupt status after masking & forcing for dormant_wake
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_OFFSET _u(0x0000031c)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_BITS _u(0xffffffff)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_RESET _u(0x00000000)
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_BITS _u(0x80000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_MSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_LSB _u(31)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_BITS _u(0x40000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_MSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_LSB _u(30)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_BITS _u(0x20000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_MSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_LSB _u(29)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_BITS _u(0x10000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_MSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_LSB _u(28)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO47_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_BITS _u(0x08000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_MSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_LSB _u(27)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_BITS _u(0x04000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_MSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_LSB _u(26)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_BITS _u(0x02000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_MSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_LSB _u(25)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_BITS _u(0x01000000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_MSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_LSB _u(24)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO46_LEVEL_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_BITS _u(0x00800000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_MSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_LSB _u(23)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_BITS _u(0x00400000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_MSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_LSB _u(22)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_EDGE_LOW_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_RESET _u(0x0)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_BITS _u(0x00200000)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_MSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_LSB _u(21)
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_HIGH_ACCESS "RO"
|
|
// -----------------------------------------------------------------------------
|
|
// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW
|
|
#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_BITS _u(0x00100000)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_MSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_LSB _u(20)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO45_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_BITS _u(0x00080000)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_MSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_LSB _u(19)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_BITS _u(0x00040000)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_MSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_LSB _u(18)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_BITS _u(0x00020000)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_MSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_LSB _u(17)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_BITS _u(0x00010000)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_MSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_LSB _u(16)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO44_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_BITS _u(0x00008000)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_MSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_LSB _u(15)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_BITS _u(0x00004000)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_MSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_LSB _u(14)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_BITS _u(0x00002000)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_MSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_LSB _u(13)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_BITS _u(0x00001000)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_MSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_LSB _u(12)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO43_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_BITS _u(0x00000800)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_MSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_LSB _u(11)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_BITS _u(0x00000400)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_MSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_LSB _u(10)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_BITS _u(0x00000200)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_MSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_LSB _u(9)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_BITS _u(0x00000100)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_MSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_LSB _u(8)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO42_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_BITS _u(0x00000080)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_MSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_LSB _u(7)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_BITS _u(0x00000040)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_MSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_LSB _u(6)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_BITS _u(0x00000020)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_MSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_LSB _u(5)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_BITS _u(0x00000010)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_MSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_LSB _u(4)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO41_LEVEL_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_BITS _u(0x00000008)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_MSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_LSB _u(3)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_BITS _u(0x00000004)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_MSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_LSB _u(2)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_EDGE_LOW_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_BITS _u(0x00000002)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_MSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_LSB _u(1)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_HIGH_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_RESET _u(0x0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_BITS _u(0x00000001)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_MSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_LSB _u(0)
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#define IO_BANK0_DORMANT_WAKE_INTS5_GPIO40_LEVEL_LOW_ACCESS "RO"
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// =============================================================================
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#endif // _HARDWARE_REGS_IO_BANK0_H
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