mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
214 lines
12 KiB
C
214 lines
12 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : GLITCH_DETECTOR
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// Version : 1
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// Bus type : apb
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// Description : Glitch detector controls
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// =============================================================================
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#ifndef _HARDWARE_REGS_GLITCH_DETECTOR_H
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#define _HARDWARE_REGS_GLITCH_DETECTOR_H
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// =============================================================================
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// Register : GLITCH_DETECTOR_ARM
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// Description : Forcibly arm the glitch detectors, if they are not already
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// armed by OTP. When armed, any individual detector trigger will
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// cause a restart of the switched core power domain's power-on
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// reset state machine.
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//
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// Glitch detector triggers are recorded accumulatively in
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// TRIG_STATUS. If the system is reset by a glitch detector
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// trigger, this is recorded in POWMAN_CHIP_RESET.
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//
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// This register is Secure read/write only.
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// 0x5bad -> Do not force the glitch detectors to be armed
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// 0x0000 -> Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)
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#define GLITCH_DETECTOR_ARM_OFFSET _u(0x00000000)
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#define GLITCH_DETECTOR_ARM_BITS _u(0x0000ffff)
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#define GLITCH_DETECTOR_ARM_RESET _u(0x00005bad)
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#define GLITCH_DETECTOR_ARM_MSB _u(15)
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#define GLITCH_DETECTOR_ARM_LSB _u(0)
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#define GLITCH_DETECTOR_ARM_ACCESS "RW"
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#define GLITCH_DETECTOR_ARM_VALUE_NO _u(0x5bad)
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#define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000)
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// =============================================================================
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// Register : GLITCH_DETECTOR_DISARM
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// Description : None
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// Forcibly disarm the glitch detectors, if they are armed by OTP.
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// Ignored if ARM is YES.
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//
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// This register is Secure read/write only.
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// 0x0000 -> Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)
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// 0xdcaf -> Disarm the glitch detectors
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#define GLITCH_DETECTOR_DISARM_OFFSET _u(0x00000004)
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#define GLITCH_DETECTOR_DISARM_BITS _u(0x0000ffff)
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#define GLITCH_DETECTOR_DISARM_RESET _u(0x00000000)
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#define GLITCH_DETECTOR_DISARM_MSB _u(15)
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#define GLITCH_DETECTOR_DISARM_LSB _u(0)
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#define GLITCH_DETECTOR_DISARM_ACCESS "RW"
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#define GLITCH_DETECTOR_DISARM_VALUE_NO _u(0x0000)
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#define GLITCH_DETECTOR_DISARM_VALUE_YES _u(0xdcaf)
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// =============================================================================
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// Register : GLITCH_DETECTOR_SENSITIVITY
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// Description : Adjust the sensitivity of glitch detectors to values other than
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// their OTP-provided defaults.
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//
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// This register is Secure read/write only.
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#define GLITCH_DETECTOR_SENSITIVITY_OFFSET _u(0x00000008)
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#define GLITCH_DETECTOR_SENSITIVITY_BITS _u(0xff00ffff)
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#define GLITCH_DETECTOR_SENSITIVITY_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_SENSITIVITY_DEFAULT
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// 0x00 -> Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)
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// 0xde -> Do not use the default sensitivity configured in OTP. Instead use the value from this register.
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#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_RESET _u(0x00)
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#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_BITS _u(0xff000000)
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#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MSB _u(31)
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#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_LSB _u(24)
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#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_ACCESS "RW"
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#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_YES _u(0x00)
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#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_NO _u(0xde)
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_SENSITIVITY_DET3_INV
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// Description : Must be the inverse of DET3, else the default value is used.
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_RESET _u(0x0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_BITS _u(0x0000c000)
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MSB _u(15)
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_LSB _u(14)
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_SENSITIVITY_DET2_INV
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// Description : Must be the inverse of DET2, else the default value is used.
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_RESET _u(0x0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_BITS _u(0x00003000)
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MSB _u(13)
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_LSB _u(12)
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_SENSITIVITY_DET1_INV
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// Description : Must be the inverse of DET1, else the default value is used.
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_RESET _u(0x0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_BITS _u(0x00000c00)
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MSB _u(11)
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_LSB _u(10)
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_SENSITIVITY_DET0_INV
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// Description : Must be the inverse of DET0, else the default value is used.
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_RESET _u(0x0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_BITS _u(0x00000300)
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MSB _u(9)
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_LSB _u(8)
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_SENSITIVITY_DET3
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// Description : Set sensitivity for detector 3. Higher values are more
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// sensitive.
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_RESET _u(0x0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_BITS _u(0x000000c0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_MSB _u(7)
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_LSB _u(6)
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#define GLITCH_DETECTOR_SENSITIVITY_DET3_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_SENSITIVITY_DET2
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// Description : Set sensitivity for detector 2. Higher values are more
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// sensitive.
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_RESET _u(0x0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_BITS _u(0x00000030)
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_MSB _u(5)
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_LSB _u(4)
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#define GLITCH_DETECTOR_SENSITIVITY_DET2_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_SENSITIVITY_DET1
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// Description : Set sensitivity for detector 1. Higher values are more
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// sensitive.
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_RESET _u(0x0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_BITS _u(0x0000000c)
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_MSB _u(3)
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_LSB _u(2)
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#define GLITCH_DETECTOR_SENSITIVITY_DET1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_SENSITIVITY_DET0
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// Description : Set sensitivity for detector 0. Higher values are more
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// sensitive.
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_RESET _u(0x0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_BITS _u(0x00000003)
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_MSB _u(1)
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_LSB _u(0)
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#define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW"
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// =============================================================================
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// Register : GLITCH_DETECTOR_LOCK
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// Description : None
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// Write any nonzero value to disable writes to ARM, DISARM,
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// SENSITIVITY and LOCK. This register is Secure read/write only.
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#define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c)
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#define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff)
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#define GLITCH_DETECTOR_LOCK_RESET _u(0x00000000)
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#define GLITCH_DETECTOR_LOCK_MSB _u(7)
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#define GLITCH_DETECTOR_LOCK_LSB _u(0)
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#define GLITCH_DETECTOR_LOCK_ACCESS "RW"
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// =============================================================================
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// Register : GLITCH_DETECTOR_TRIG_STATUS
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// Description : Set when a detector output triggers. Write-1-clear.
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//
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// (May immediately return high if the detector remains in a
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// failed state. Detectors can only be cleared by a full reset of
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// the switched core power domain.)
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//
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// This register is Secure read/write only.
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#define GLITCH_DETECTOR_TRIG_STATUS_OFFSET _u(0x00000010)
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#define GLITCH_DETECTOR_TRIG_STATUS_BITS _u(0x0000000f)
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#define GLITCH_DETECTOR_TRIG_STATUS_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_TRIG_STATUS_DET3
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#define GLITCH_DETECTOR_TRIG_STATUS_DET3_RESET _u(0x0)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET3_BITS _u(0x00000008)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET3_MSB _u(3)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET3_LSB _u(3)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET3_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_TRIG_STATUS_DET2
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#define GLITCH_DETECTOR_TRIG_STATUS_DET2_RESET _u(0x0)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET2_BITS _u(0x00000004)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET2_MSB _u(2)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET2_LSB _u(2)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET2_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_TRIG_STATUS_DET1
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#define GLITCH_DETECTOR_TRIG_STATUS_DET1_RESET _u(0x0)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET1_BITS _u(0x00000002)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET1_MSB _u(1)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET1_LSB _u(1)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET1_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : GLITCH_DETECTOR_TRIG_STATUS_DET0
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#define GLITCH_DETECTOR_TRIG_STATUS_DET0_RESET _u(0x0)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET0_BITS _u(0x00000001)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET0_MSB _u(0)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET0_LSB _u(0)
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#define GLITCH_DETECTOR_TRIG_STATUS_DET0_ACCESS "WC"
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// =============================================================================
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// Register : GLITCH_DETECTOR_TRIG_FORCE
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// Description : Simulate the firing of one or more detectors. Writing ones to
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// this register will set the matching bits in STATUS_TRIG.
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//
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// If the glitch detectors are currently armed, writing ones will
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// also immediately reset the switched core power domain, and set
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// the reset reason latches in POWMAN_CHIP_RESET to indicate a
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// glitch detector resets.
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//
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// This register is Secure read/write only.
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#define GLITCH_DETECTOR_TRIG_FORCE_OFFSET _u(0x00000014)
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#define GLITCH_DETECTOR_TRIG_FORCE_BITS _u(0x0000000f)
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#define GLITCH_DETECTOR_TRIG_FORCE_RESET _u(0x00000000)
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#define GLITCH_DETECTOR_TRIG_FORCE_MSB _u(3)
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#define GLITCH_DETECTOR_TRIG_FORCE_LSB _u(0)
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#define GLITCH_DETECTOR_TRIG_FORCE_ACCESS "SC"
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// =============================================================================
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#endif // _HARDWARE_REGS_GLITCH_DETECTOR_H
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