mirror of
https://github.com/andreili/katapult.git
synced 2025-09-12 00:21:14 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
113 lines
3.8 KiB
C
113 lines
3.8 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _ADDRESSMAP_H
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#define _ADDRESSMAP_H
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/**
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* \file rp2350/addressmap.h
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*/
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#include "hardware/platform_defs.h"
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// Register address offsets for atomic RMW aliases
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#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12))
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#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12))
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#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12))
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#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12))
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#define ROM_BASE _u(0x00000000)
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#define XIP_BASE _u(0x10000000)
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#define XIP_SRAM_BASE _u(0x13ffc000)
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#define XIP_END _u(0x14000000)
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#define XIP_NOCACHE_NOALLOC_BASE _u(0x14000000)
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#define XIP_SRAM_END _u(0x14000000)
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#define XIP_NOCACHE_NOALLOC_END _u(0x18000000)
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#define XIP_MAINTENANCE_BASE _u(0x18000000)
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#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_BASE _u(0x1c000000)
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#define SRAM0_BASE _u(0x20000000)
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#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_END _u(0x20000000)
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#define SRAM_BASE _u(0x20000000)
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#define SRAM_STRIPED_BASE _u(0x20000000)
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#define SRAM4_BASE _u(0x20040000)
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#define SRAM8_BASE _u(0x20080000)
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#define SRAM_STRIPED_END _u(0x20080000)
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#define SRAM_SCRATCH_X_BASE _u(0x20080000)
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#define SRAM9_BASE _u(0x20081000)
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#define SRAM_SCRATCH_Y_BASE _u(0x20081000)
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#define SRAM_END _u(0x20082000)
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#define SYSINFO_BASE _u(0x40000000)
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#define SYSCFG_BASE _u(0x40008000)
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#define CLOCKS_BASE _u(0x40010000)
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#define PSM_BASE _u(0x40018000)
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#define RESETS_BASE _u(0x40020000)
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#define IO_BANK0_BASE _u(0x40028000)
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#define IO_QSPI_BASE _u(0x40030000)
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#define PADS_BANK0_BASE _u(0x40038000)
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#define PADS_QSPI_BASE _u(0x40040000)
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#define XOSC_BASE _u(0x40048000)
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#define PLL_SYS_BASE _u(0x40050000)
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#define PLL_USB_BASE _u(0x40058000)
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#define ACCESSCTRL_BASE _u(0x40060000)
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#define BUSCTRL_BASE _u(0x40068000)
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#define UART0_BASE _u(0x40070000)
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#define UART1_BASE _u(0x40078000)
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#define SPI0_BASE _u(0x40080000)
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#define SPI1_BASE _u(0x40088000)
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#define I2C0_BASE _u(0x40090000)
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#define I2C1_BASE _u(0x40098000)
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#define ADC_BASE _u(0x400a0000)
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#define PWM_BASE _u(0x400a8000)
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#define TIMER0_BASE _u(0x400b0000)
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#define TIMER1_BASE _u(0x400b8000)
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#define HSTX_CTRL_BASE _u(0x400c0000)
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#define XIP_CTRL_BASE _u(0x400c8000)
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#define XIP_QMI_BASE _u(0x400d0000)
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#define WATCHDOG_BASE _u(0x400d8000)
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#define BOOTRAM_BASE _u(0x400e0000)
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#define BOOTRAM_END _u(0x400e0400)
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#define ROSC_BASE _u(0x400e8000)
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#define TRNG_BASE _u(0x400f0000)
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#define SHA256_BASE _u(0x400f8000)
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#define POWMAN_BASE _u(0x40100000)
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#define TICKS_BASE _u(0x40108000)
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#define OTP_BASE _u(0x40120000)
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#define OTP_DATA_BASE _u(0x40130000)
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#define OTP_DATA_RAW_BASE _u(0x40134000)
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#define OTP_DATA_GUARDED_BASE _u(0x40138000)
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#define OTP_DATA_RAW_GUARDED_BASE _u(0x4013c000)
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#define CORESIGHT_PERIPH_BASE _u(0x40140000)
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#define CORESIGHT_ROMTABLE_BASE _u(0x40140000)
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#define CORESIGHT_AHB_AP_CORE0_BASE _u(0x40142000)
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#define CORESIGHT_AHB_AP_CORE1_BASE _u(0x40144000)
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#define CORESIGHT_TIMESTAMP_GEN_BASE _u(0x40146000)
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#define CORESIGHT_ATB_FUNNEL_BASE _u(0x40147000)
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#define CORESIGHT_TPIU_BASE _u(0x40148000)
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#define CORESIGHT_CTI_BASE _u(0x40149000)
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#define CORESIGHT_APB_AP_RISCV_BASE _u(0x4014a000)
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#define DFT_BASE _u(0x40150000)
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#define GLITCH_DETECTOR_BASE _u(0x40158000)
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#define TBMAN_BASE _u(0x40160000)
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#define DMA_BASE _u(0x50000000)
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#define USBCTRL_BASE _u(0x50100000)
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#define USBCTRL_DPRAM_BASE _u(0x50100000)
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#define USBCTRL_REGS_BASE _u(0x50110000)
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#define PIO0_BASE _u(0x50200000)
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#define PIO1_BASE _u(0x50300000)
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#define PIO2_BASE _u(0x50400000)
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#define XIP_AUX_BASE _u(0x50500000)
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#define HSTX_FIFO_BASE _u(0x50600000)
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#define CORESIGHT_TRACE_BASE _u(0x50700000)
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#define SIO_BASE _u(0xd0000000)
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#define SIO_NONSEC_BASE _u(0xd0020000)
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#define PPB_BASE _u(0xe0000000)
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#define PPB_NONSEC_BASE _u(0xe0020000)
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#define EPPB_BASE _u(0xe0080000)
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#endif // _ADDRESSMAP_H
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