mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
276 lines
13 KiB
C
276 lines
13 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : TICKS
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// Version : 1
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// Bus type : apb
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// =============================================================================
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#ifndef _HARDWARE_REGS_TICKS_H
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#define _HARDWARE_REGS_TICKS_H
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// =============================================================================
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// Register : TICKS_PROC0_CTRL
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// Description : Controls the tick generator
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#define TICKS_PROC0_CTRL_OFFSET _u(0x00000000)
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#define TICKS_PROC0_CTRL_BITS _u(0x00000003)
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#define TICKS_PROC0_CTRL_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TICKS_PROC0_CTRL_RUNNING
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// Description : Is the tick generator running?
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#define TICKS_PROC0_CTRL_RUNNING_RESET "-"
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#define TICKS_PROC0_CTRL_RUNNING_BITS _u(0x00000002)
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#define TICKS_PROC0_CTRL_RUNNING_MSB _u(1)
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#define TICKS_PROC0_CTRL_RUNNING_LSB _u(1)
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#define TICKS_PROC0_CTRL_RUNNING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : TICKS_PROC0_CTRL_ENABLE
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// Description : start / stop tick generation
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#define TICKS_PROC0_CTRL_ENABLE_RESET _u(0x0)
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#define TICKS_PROC0_CTRL_ENABLE_BITS _u(0x00000001)
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#define TICKS_PROC0_CTRL_ENABLE_MSB _u(0)
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#define TICKS_PROC0_CTRL_ENABLE_LSB _u(0)
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#define TICKS_PROC0_CTRL_ENABLE_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_PROC0_CYCLES
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// Description : None
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// Total number of clk_tick cycles before the next tick.
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#define TICKS_PROC0_CYCLES_OFFSET _u(0x00000004)
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#define TICKS_PROC0_CYCLES_BITS _u(0x000001ff)
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#define TICKS_PROC0_CYCLES_RESET _u(0x00000000)
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#define TICKS_PROC0_CYCLES_MSB _u(8)
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#define TICKS_PROC0_CYCLES_LSB _u(0)
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#define TICKS_PROC0_CYCLES_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_PROC0_COUNT
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// Description : None
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// Count down timer: the remaining number clk_tick cycles before
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// the next tick is generated.
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#define TICKS_PROC0_COUNT_OFFSET _u(0x00000008)
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#define TICKS_PROC0_COUNT_BITS _u(0x000001ff)
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#define TICKS_PROC0_COUNT_RESET "-"
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#define TICKS_PROC0_COUNT_MSB _u(8)
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#define TICKS_PROC0_COUNT_LSB _u(0)
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#define TICKS_PROC0_COUNT_ACCESS "RO"
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// =============================================================================
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// Register : TICKS_PROC1_CTRL
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// Description : Controls the tick generator
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#define TICKS_PROC1_CTRL_OFFSET _u(0x0000000c)
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#define TICKS_PROC1_CTRL_BITS _u(0x00000003)
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#define TICKS_PROC1_CTRL_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TICKS_PROC1_CTRL_RUNNING
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// Description : Is the tick generator running?
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#define TICKS_PROC1_CTRL_RUNNING_RESET "-"
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#define TICKS_PROC1_CTRL_RUNNING_BITS _u(0x00000002)
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#define TICKS_PROC1_CTRL_RUNNING_MSB _u(1)
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#define TICKS_PROC1_CTRL_RUNNING_LSB _u(1)
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#define TICKS_PROC1_CTRL_RUNNING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : TICKS_PROC1_CTRL_ENABLE
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// Description : start / stop tick generation
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#define TICKS_PROC1_CTRL_ENABLE_RESET _u(0x0)
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#define TICKS_PROC1_CTRL_ENABLE_BITS _u(0x00000001)
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#define TICKS_PROC1_CTRL_ENABLE_MSB _u(0)
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#define TICKS_PROC1_CTRL_ENABLE_LSB _u(0)
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#define TICKS_PROC1_CTRL_ENABLE_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_PROC1_CYCLES
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// Description : None
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// Total number of clk_tick cycles before the next tick.
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#define TICKS_PROC1_CYCLES_OFFSET _u(0x00000010)
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#define TICKS_PROC1_CYCLES_BITS _u(0x000001ff)
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#define TICKS_PROC1_CYCLES_RESET _u(0x00000000)
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#define TICKS_PROC1_CYCLES_MSB _u(8)
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#define TICKS_PROC1_CYCLES_LSB _u(0)
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#define TICKS_PROC1_CYCLES_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_PROC1_COUNT
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// Description : None
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// Count down timer: the remaining number clk_tick cycles before
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// the next tick is generated.
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#define TICKS_PROC1_COUNT_OFFSET _u(0x00000014)
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#define TICKS_PROC1_COUNT_BITS _u(0x000001ff)
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#define TICKS_PROC1_COUNT_RESET "-"
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#define TICKS_PROC1_COUNT_MSB _u(8)
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#define TICKS_PROC1_COUNT_LSB _u(0)
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#define TICKS_PROC1_COUNT_ACCESS "RO"
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// =============================================================================
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// Register : TICKS_TIMER0_CTRL
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// Description : Controls the tick generator
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#define TICKS_TIMER0_CTRL_OFFSET _u(0x00000018)
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#define TICKS_TIMER0_CTRL_BITS _u(0x00000003)
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#define TICKS_TIMER0_CTRL_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TICKS_TIMER0_CTRL_RUNNING
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// Description : Is the tick generator running?
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#define TICKS_TIMER0_CTRL_RUNNING_RESET "-"
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#define TICKS_TIMER0_CTRL_RUNNING_BITS _u(0x00000002)
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#define TICKS_TIMER0_CTRL_RUNNING_MSB _u(1)
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#define TICKS_TIMER0_CTRL_RUNNING_LSB _u(1)
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#define TICKS_TIMER0_CTRL_RUNNING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : TICKS_TIMER0_CTRL_ENABLE
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// Description : start / stop tick generation
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#define TICKS_TIMER0_CTRL_ENABLE_RESET _u(0x0)
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#define TICKS_TIMER0_CTRL_ENABLE_BITS _u(0x00000001)
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#define TICKS_TIMER0_CTRL_ENABLE_MSB _u(0)
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#define TICKS_TIMER0_CTRL_ENABLE_LSB _u(0)
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#define TICKS_TIMER0_CTRL_ENABLE_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_TIMER0_CYCLES
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// Description : None
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// Total number of clk_tick cycles before the next tick.
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#define TICKS_TIMER0_CYCLES_OFFSET _u(0x0000001c)
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#define TICKS_TIMER0_CYCLES_BITS _u(0x000001ff)
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#define TICKS_TIMER0_CYCLES_RESET _u(0x00000000)
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#define TICKS_TIMER0_CYCLES_MSB _u(8)
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#define TICKS_TIMER0_CYCLES_LSB _u(0)
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#define TICKS_TIMER0_CYCLES_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_TIMER0_COUNT
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// Description : None
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// Count down timer: the remaining number clk_tick cycles before
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// the next tick is generated.
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#define TICKS_TIMER0_COUNT_OFFSET _u(0x00000020)
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#define TICKS_TIMER0_COUNT_BITS _u(0x000001ff)
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#define TICKS_TIMER0_COUNT_RESET "-"
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#define TICKS_TIMER0_COUNT_MSB _u(8)
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#define TICKS_TIMER0_COUNT_LSB _u(0)
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#define TICKS_TIMER0_COUNT_ACCESS "RO"
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// =============================================================================
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// Register : TICKS_TIMER1_CTRL
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// Description : Controls the tick generator
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#define TICKS_TIMER1_CTRL_OFFSET _u(0x00000024)
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#define TICKS_TIMER1_CTRL_BITS _u(0x00000003)
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#define TICKS_TIMER1_CTRL_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TICKS_TIMER1_CTRL_RUNNING
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// Description : Is the tick generator running?
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#define TICKS_TIMER1_CTRL_RUNNING_RESET "-"
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#define TICKS_TIMER1_CTRL_RUNNING_BITS _u(0x00000002)
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#define TICKS_TIMER1_CTRL_RUNNING_MSB _u(1)
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#define TICKS_TIMER1_CTRL_RUNNING_LSB _u(1)
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#define TICKS_TIMER1_CTRL_RUNNING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : TICKS_TIMER1_CTRL_ENABLE
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// Description : start / stop tick generation
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#define TICKS_TIMER1_CTRL_ENABLE_RESET _u(0x0)
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#define TICKS_TIMER1_CTRL_ENABLE_BITS _u(0x00000001)
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#define TICKS_TIMER1_CTRL_ENABLE_MSB _u(0)
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#define TICKS_TIMER1_CTRL_ENABLE_LSB _u(0)
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#define TICKS_TIMER1_CTRL_ENABLE_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_TIMER1_CYCLES
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// Description : None
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// Total number of clk_tick cycles before the next tick.
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#define TICKS_TIMER1_CYCLES_OFFSET _u(0x00000028)
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#define TICKS_TIMER1_CYCLES_BITS _u(0x000001ff)
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#define TICKS_TIMER1_CYCLES_RESET _u(0x00000000)
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#define TICKS_TIMER1_CYCLES_MSB _u(8)
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#define TICKS_TIMER1_CYCLES_LSB _u(0)
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#define TICKS_TIMER1_CYCLES_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_TIMER1_COUNT
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// Description : None
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// Count down timer: the remaining number clk_tick cycles before
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// the next tick is generated.
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#define TICKS_TIMER1_COUNT_OFFSET _u(0x0000002c)
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#define TICKS_TIMER1_COUNT_BITS _u(0x000001ff)
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#define TICKS_TIMER1_COUNT_RESET "-"
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#define TICKS_TIMER1_COUNT_MSB _u(8)
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#define TICKS_TIMER1_COUNT_LSB _u(0)
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#define TICKS_TIMER1_COUNT_ACCESS "RO"
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// =============================================================================
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// Register : TICKS_WATCHDOG_CTRL
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// Description : Controls the tick generator
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#define TICKS_WATCHDOG_CTRL_OFFSET _u(0x00000030)
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#define TICKS_WATCHDOG_CTRL_BITS _u(0x00000003)
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#define TICKS_WATCHDOG_CTRL_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TICKS_WATCHDOG_CTRL_RUNNING
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// Description : Is the tick generator running?
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#define TICKS_WATCHDOG_CTRL_RUNNING_RESET "-"
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#define TICKS_WATCHDOG_CTRL_RUNNING_BITS _u(0x00000002)
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#define TICKS_WATCHDOG_CTRL_RUNNING_MSB _u(1)
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#define TICKS_WATCHDOG_CTRL_RUNNING_LSB _u(1)
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#define TICKS_WATCHDOG_CTRL_RUNNING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : TICKS_WATCHDOG_CTRL_ENABLE
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// Description : start / stop tick generation
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#define TICKS_WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
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#define TICKS_WATCHDOG_CTRL_ENABLE_BITS _u(0x00000001)
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#define TICKS_WATCHDOG_CTRL_ENABLE_MSB _u(0)
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#define TICKS_WATCHDOG_CTRL_ENABLE_LSB _u(0)
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#define TICKS_WATCHDOG_CTRL_ENABLE_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_WATCHDOG_CYCLES
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// Description : None
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// Total number of clk_tick cycles before the next tick.
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#define TICKS_WATCHDOG_CYCLES_OFFSET _u(0x00000034)
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#define TICKS_WATCHDOG_CYCLES_BITS _u(0x000001ff)
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#define TICKS_WATCHDOG_CYCLES_RESET _u(0x00000000)
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#define TICKS_WATCHDOG_CYCLES_MSB _u(8)
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#define TICKS_WATCHDOG_CYCLES_LSB _u(0)
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#define TICKS_WATCHDOG_CYCLES_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_WATCHDOG_COUNT
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// Description : None
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// Count down timer: the remaining number clk_tick cycles before
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// the next tick is generated.
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#define TICKS_WATCHDOG_COUNT_OFFSET _u(0x00000038)
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#define TICKS_WATCHDOG_COUNT_BITS _u(0x000001ff)
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#define TICKS_WATCHDOG_COUNT_RESET "-"
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#define TICKS_WATCHDOG_COUNT_MSB _u(8)
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#define TICKS_WATCHDOG_COUNT_LSB _u(0)
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#define TICKS_WATCHDOG_COUNT_ACCESS "RO"
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// =============================================================================
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// Register : TICKS_RISCV_CTRL
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// Description : Controls the tick generator
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#define TICKS_RISCV_CTRL_OFFSET _u(0x0000003c)
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#define TICKS_RISCV_CTRL_BITS _u(0x00000003)
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#define TICKS_RISCV_CTRL_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : TICKS_RISCV_CTRL_RUNNING
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// Description : Is the tick generator running?
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#define TICKS_RISCV_CTRL_RUNNING_RESET "-"
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#define TICKS_RISCV_CTRL_RUNNING_BITS _u(0x00000002)
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#define TICKS_RISCV_CTRL_RUNNING_MSB _u(1)
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#define TICKS_RISCV_CTRL_RUNNING_LSB _u(1)
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#define TICKS_RISCV_CTRL_RUNNING_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : TICKS_RISCV_CTRL_ENABLE
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// Description : start / stop tick generation
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#define TICKS_RISCV_CTRL_ENABLE_RESET _u(0x0)
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#define TICKS_RISCV_CTRL_ENABLE_BITS _u(0x00000001)
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#define TICKS_RISCV_CTRL_ENABLE_MSB _u(0)
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#define TICKS_RISCV_CTRL_ENABLE_LSB _u(0)
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#define TICKS_RISCV_CTRL_ENABLE_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_RISCV_CYCLES
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// Description : None
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// Total number of clk_tick cycles before the next tick.
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#define TICKS_RISCV_CYCLES_OFFSET _u(0x00000040)
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#define TICKS_RISCV_CYCLES_BITS _u(0x000001ff)
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#define TICKS_RISCV_CYCLES_RESET _u(0x00000000)
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#define TICKS_RISCV_CYCLES_MSB _u(8)
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#define TICKS_RISCV_CYCLES_LSB _u(0)
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#define TICKS_RISCV_CYCLES_ACCESS "RW"
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// =============================================================================
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// Register : TICKS_RISCV_COUNT
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// Description : None
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// Count down timer: the remaining number clk_tick cycles before
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// the next tick is generated.
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#define TICKS_RISCV_COUNT_OFFSET _u(0x00000044)
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#define TICKS_RISCV_COUNT_BITS _u(0x000001ff)
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#define TICKS_RISCV_COUNT_RESET "-"
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#define TICKS_RISCV_COUNT_MSB _u(8)
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#define TICKS_RISCV_COUNT_LSB _u(0)
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#define TICKS_RISCV_COUNT_ACCESS "RO"
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// =============================================================================
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#endif // _HARDWARE_REGS_TICKS_H
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