mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
63 lines
2.6 KiB
C
63 lines
2.6 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : HSTX_FIFO
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// Version : 1
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// Bus type : ahbl
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// Description : FIFO status and write access for HSTX
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// =============================================================================
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#ifndef _HARDWARE_REGS_HSTX_FIFO_H
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#define _HARDWARE_REGS_HSTX_FIFO_H
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// =============================================================================
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// Register : HSTX_FIFO_STAT
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// Description : FIFO status
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#define HSTX_FIFO_STAT_OFFSET _u(0x00000000)
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#define HSTX_FIFO_STAT_BITS _u(0x000007ff)
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#define HSTX_FIFO_STAT_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : HSTX_FIFO_STAT_WOF
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// Description : FIFO was written when full. Write 1 to clear.
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#define HSTX_FIFO_STAT_WOF_RESET _u(0x0)
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#define HSTX_FIFO_STAT_WOF_BITS _u(0x00000400)
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#define HSTX_FIFO_STAT_WOF_MSB _u(10)
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#define HSTX_FIFO_STAT_WOF_LSB _u(10)
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#define HSTX_FIFO_STAT_WOF_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : HSTX_FIFO_STAT_EMPTY
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#define HSTX_FIFO_STAT_EMPTY_RESET "-"
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#define HSTX_FIFO_STAT_EMPTY_BITS _u(0x00000200)
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#define HSTX_FIFO_STAT_EMPTY_MSB _u(9)
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#define HSTX_FIFO_STAT_EMPTY_LSB _u(9)
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#define HSTX_FIFO_STAT_EMPTY_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : HSTX_FIFO_STAT_FULL
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#define HSTX_FIFO_STAT_FULL_RESET "-"
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#define HSTX_FIFO_STAT_FULL_BITS _u(0x00000100)
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#define HSTX_FIFO_STAT_FULL_MSB _u(8)
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#define HSTX_FIFO_STAT_FULL_LSB _u(8)
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#define HSTX_FIFO_STAT_FULL_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : HSTX_FIFO_STAT_LEVEL
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#define HSTX_FIFO_STAT_LEVEL_RESET _u(0x00)
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#define HSTX_FIFO_STAT_LEVEL_BITS _u(0x000000ff)
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#define HSTX_FIFO_STAT_LEVEL_MSB _u(7)
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#define HSTX_FIFO_STAT_LEVEL_LSB _u(0)
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#define HSTX_FIFO_STAT_LEVEL_ACCESS "RO"
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// =============================================================================
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// Register : HSTX_FIFO_FIFO
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// Description : Write access to FIFO
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#define HSTX_FIFO_FIFO_OFFSET _u(0x00000004)
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#define HSTX_FIFO_FIFO_BITS _u(0xffffffff)
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#define HSTX_FIFO_FIFO_RESET _u(0x00000000)
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#define HSTX_FIFO_FIFO_MSB _u(31)
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#define HSTX_FIFO_FIFO_LSB _u(0)
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#define HSTX_FIFO_FIFO_ACCESS "WF"
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// =============================================================================
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#endif // _HARDWARE_REGS_HSTX_FIFO_H
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