mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
154 lines
7.0 KiB
C
154 lines
7.0 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_TRNG_H
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#define _HARDWARE_STRUCTS_TRNG_H
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/**
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* \file rp2350/trng.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/trng.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_trng
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/trng.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(TRNG_RNG_IMR_OFFSET) // TRNG_RNG_IMR
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// Interrupt masking
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// 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED
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// 0x00000008 [3] VN_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated
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// 0x00000004 [2] CRNGT_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated
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// 0x00000002 [1] AUTOCORR_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated
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// 0x00000001 [0] EHR_VALID_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated
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io_rw_32 rng_imr;
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_REG_(TRNG_RNG_ISR_OFFSET) // TRNG_RNG_ISR
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// RNG status register
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// 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED
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// 0x00000008 [3] VN_ERR (0) 1'b1 indicates Von Neuman error
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// 0x00000004 [2] CRNGT_ERR (0) 1'b1 indicates CRNGT in the RNG test failed
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// 0x00000002 [1] AUTOCORR_ERR (0) 1'b1 indicates Autocorrelation test failed four times in a row
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// 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that 192 bits have been collected in the...
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io_ro_32 rng_isr;
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_REG_(TRNG_RNG_ICR_OFFSET) // TRNG_RNG_ICR
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// Interrupt/status bit clear Register
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// 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED
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// 0x00000008 [3] VN_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR
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// 0x00000004 [2] CRNGT_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR
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// 0x00000002 [1] AUTOCORR_ERR (0) Cannot be cleared by SW! Only RNG reset clears this bit
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// 0x00000001 [0] EHR_VALID (0) Write 1'b1 - clear corresponding bit in RNG_ISR
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io_rw_32 rng_icr;
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_REG_(TRNG_TRNG_CONFIG_OFFSET) // TRNG_TRNG_CONFIG
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// Selecting the inverter-chain length
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// 0xfffffffc [31:2] RESERVED (0x00000000) RESERVED
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// 0x00000003 [1:0] RND_SRC_SEL (0x0) Selects the number of inverters (out of four possible...
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io_rw_32 trng_config;
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_REG_(TRNG_TRNG_VALID_OFFSET) // TRNG_TRNG_VALID
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// 192 bit collection indication
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// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
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// 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that collection of bits in the RNG is...
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io_ro_32 trng_valid;
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// (Description copied from array index 0 register TRNG_EHR_DATA0 applies similarly to other array indexes)
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_REG_(TRNG_EHR_DATA0_OFFSET) // TRNG_EHR_DATA0
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// RNG collected bits
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// 0xffffffff [31:0] EHR_DATA0 (0x00000000) Bits [31:0] of Entropy Holding Register (EHR) - RNG...
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io_ro_32 ehr_data[6];
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_REG_(TRNG_RND_SOURCE_ENABLE_OFFSET) // TRNG_RND_SOURCE_ENABLE
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// Enable signal for the random source
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// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
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// 0x00000001 [0] RND_SRC_EN (0) * 1'b1 - entropy source is enabled
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io_rw_32 rnd_source_enable;
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_REG_(TRNG_SAMPLE_CNT1_OFFSET) // TRNG_SAMPLE_CNT1
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// Counts clocks between sampling of random bit
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// 0xffffffff [31:0] SAMPLE_CNTR1 (0x0000ffff) Sets the number of rng_clk cycles between two...
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io_rw_32 sample_cnt1;
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_REG_(TRNG_AUTOCORR_STATISTIC_OFFSET) // TRNG_AUTOCORR_STATISTIC
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// Statistic about Autocorrelation test activations
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// 0xffc00000 [31:22] RESERVED (0x000) RESERVED
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// 0x003fc000 [21:14] AUTOCORR_FAILS (0x00) Count each time an autocorrelation test fails
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// 0x00003fff [13:0] AUTOCORR_TRYS (0x0000) Count each time an autocorrelation test starts
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io_rw_32 autocorr_statistic;
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_REG_(TRNG_TRNG_DEBUG_CONTROL_OFFSET) // TRNG_TRNG_DEBUG_CONTROL
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// Debug register
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// 0x00000008 [3] AUTO_CORRELATE_BYPASS (0) When set, the autocorrelation test in the TRNG module is bypassed
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// 0x00000004 [2] TRNG_CRNGT_BYPASS (0) When set, the CRNGT test in the RNG is bypassed
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// 0x00000002 [1] VNC_BYPASS (0) When set, the Von-Neuman balancer is bypassed (including...
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// 0x00000001 [0] RESERVED (0) N/A
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io_rw_32 trng_debug_control;
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uint32_t _pad0;
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_REG_(TRNG_TRNG_SW_RESET_OFFSET) // TRNG_TRNG_SW_RESET
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// Generate internal SW reset within the RNG block
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// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
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// 0x00000001 [0] TRNG_SW_RESET (0) Writing 1'b1 to this register causes an internal RNG reset
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io_rw_32 trng_sw_reset;
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uint32_t _pad1[28];
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_REG_(TRNG_RNG_DEBUG_EN_INPUT_OFFSET) // TRNG_RNG_DEBUG_EN_INPUT
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// Enable the RNG debug mode
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// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
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// 0x00000001 [0] RNG_DEBUG_EN (0) * 1'b1 - debug mode is enabled
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io_rw_32 rng_debug_en_input;
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_REG_(TRNG_TRNG_BUSY_OFFSET) // TRNG_TRNG_BUSY
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// RNG Busy indication
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// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
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// 0x00000001 [0] TRNG_BUSY (0) Reflects rng_busy status
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io_ro_32 trng_busy;
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_REG_(TRNG_RST_BITS_COUNTER_OFFSET) // TRNG_RST_BITS_COUNTER
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// Reset the counter of collected bits in the RNG
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// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
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// 0x00000001 [0] RST_BITS_COUNTER (0) Writing any value to this address will reset the bits...
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io_rw_32 rst_bits_counter;
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_REG_(TRNG_RNG_VERSION_OFFSET) // TRNG_RNG_VERSION
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// Displays the version settings of the TRNG
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// 0xffffff00 [31:8] RESERVED (0x000000) RESERVED
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// 0x00000080 [7] RNG_USE_5_SBOXES (0) * 1'b1 - 5 SBOX AES
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// 0x00000040 [6] RESEEDING_EXISTS (0) * 1'b1 - Exists
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// 0x00000020 [5] KAT_EXISTS (0) * 1'b1 - Exists
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// 0x00000010 [4] PRNG_EXISTS (0) * 1'b1 - Exists
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// 0x00000008 [3] TRNG_TESTS_BYPASS_EN (0) * 1'b1 - Exists
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// 0x00000004 [2] AUTOCORR_EXISTS (0) * 1'b1 - Exists
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// 0x00000002 [1] CRNGT_EXISTS (0) * 1'b1 - Exists
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// 0x00000001 [0] EHR_WIDTH_192 (0) * 1'b1 - 192-bit EHR
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io_ro_32 rng_version;
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uint32_t _pad2[7];
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// (Description copied from array index 0 register TRNG_RNG_BIST_CNTR_0 applies similarly to other array indexes)
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_REG_(TRNG_RNG_BIST_CNTR_0_OFFSET) // TRNG_RNG_BIST_CNTR_0
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// Collected BIST results
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// 0xffc00000 [31:22] RESERVED (0x000) RESERVED
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// 0x003fffff [21:0] ROSC_CNTR_VAL (0x000000) Reflects the results of RNG BIST counter
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io_ro_32 rng_bist_cntr[3];
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} trng_hw_t;
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#define trng_hw ((trng_hw_t *)(TRNG_BASE + TRNG_RNG_IMR_OFFSET))
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static_assert(sizeof (trng_hw_t) == 0x00ec, "");
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#endif // _HARDWARE_STRUCTS_TRNG_H
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