mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
93 lines
4.2 KiB
C
93 lines
4.2 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_TMDS_ENCODE_H
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#define _HARDWARE_STRUCTS_TMDS_ENCODE_H
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/**
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* \file rp2350/tmds_encode.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/sio.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL
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// Control register for TMDS encoder
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// 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders
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// 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle...
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// 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read...
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// 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE
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// 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,...
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// 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,...
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// 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,...
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// 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
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// 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
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// 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
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io_rw_32 tmds_ctrl;
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_REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA
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// Write-only access to the TMDS colour data register
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// 0xffffffff [31:0] TMDS_WDATA (0x00000000)
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io_wo_32 tmds_wdata;
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_REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE
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// Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols)
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// 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000)
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io_ro_32 tmds_peek_single;
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_REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE
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// Get the encoding of one pixel's worth of colour data, packed into a 32-bit value
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// 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000)
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io_ro_32 tmds_pop_single;
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_REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0
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// Get lane 0 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000)
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io_ro_32 tmds_peek_double_l0;
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_REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0
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// Get lane 0 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000)
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io_ro_32 tmds_pop_double_l0;
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_REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1
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// Get lane 1 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000)
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io_ro_32 tmds_peek_double_l1;
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_REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1
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// Get lane 1 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000)
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io_ro_32 tmds_pop_double_l1;
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_REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2
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// Get lane 2 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000)
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io_ro_32 tmds_peek_double_l2;
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_REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2
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// Get lane 2 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000)
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io_ro_32 tmds_pop_double_l2;
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} tmds_encode_hw_t;
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#define tmds_encode_hw ((tmds_encode_hw_t *)(SIO_BASE + SIO_TMDS_CTRL_OFFSET))
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#define tmds_encode_ns_hw ((tmds_encode_hw_t *)(SIO_NONSEC_BASE + SIO_TMDS_CTRL_OFFSET))
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static_assert(sizeof (tmds_encode_hw_t) == 0x0028, "");
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#endif // _HARDWARE_STRUCTS_TMDS_ENCODE_H
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