mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
337 lines
14 KiB
C
337 lines
14 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_SIO_H
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#define _HARDWARE_STRUCTS_SIO_H
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/**
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* \file rp2350/sio.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/sio.h"
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#include "hardware/structs/interp.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(SIO_CPUID_OFFSET) // SIO_CPUID
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// Processor core identifier
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// 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when...
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io_ro_32 cpuid;
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_REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
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// Input value for GPIO0
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// 0xffffffff [31:0] GPIO_IN (0x00000000)
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io_ro_32 gpio_in;
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_REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
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// Input value on GPIO32
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// 0xf0000000 [31:28] QSPI_SD (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins
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// 0x08000000 [27] QSPI_CSN (0) Input value on QSPI CSn pin
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// 0x04000000 [26] QSPI_SCK (0) Input value on QSPI SCK pin
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// 0x02000000 [25] USB_DM (0) Input value on USB D- pin
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// 0x01000000 [24] USB_DP (0) Input value on USB D+ pin
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// 0x0000ffff [15:0] GPIO (0x0000) Input value on GPIO32
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io_ro_32 gpio_hi_in;
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uint32_t _pad0;
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_REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
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// GPIO0
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// 0xffffffff [31:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0
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io_rw_32 gpio_out;
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_REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
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// Output value for GPIO32
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// 0xf0000000 [31:28] QSPI_SD (0x0) Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins
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// 0x08000000 [27] QSPI_CSN (0) Output value for QSPI CSn pin
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// 0x04000000 [26] QSPI_SCK (0) Output value for QSPI SCK pin
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// 0x02000000 [25] USB_DM (0) Output value for USB D- pin
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// 0x01000000 [24] USB_DP (0) Output value for USB D+ pin
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// 0x0000ffff [15:0] GPIO (0x0000) Output value for GPIO32
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io_rw_32 gpio_hi_out;
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_REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
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// GPIO0
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// 0xffffffff [31:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i
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io_wo_32 gpio_set;
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_REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
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// Output value set for GPIO32
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// 0xf0000000 [31:28] QSPI_SD (0x0)
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// 0x08000000 [27] QSPI_CSN (0)
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// 0x04000000 [26] QSPI_SCK (0)
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// 0x02000000 [25] USB_DM (0)
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// 0x01000000 [24] USB_DP (0)
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// 0x0000ffff [15:0] GPIO (0x0000)
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io_wo_32 gpio_hi_set;
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_REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
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// GPIO0
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// 0xffffffff [31:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i
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io_wo_32 gpio_clr;
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_REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
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// Output value clear for GPIO32
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// 0xf0000000 [31:28] QSPI_SD (0x0)
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// 0x08000000 [27] QSPI_CSN (0)
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// 0x04000000 [26] QSPI_SCK (0)
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// 0x02000000 [25] USB_DM (0)
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// 0x01000000 [24] USB_DP (0)
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// 0x0000ffff [15:0] GPIO (0x0000)
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io_wo_32 gpio_hi_clr;
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_REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
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// GPIO0
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// 0xffffffff [31:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i
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io_wo_32 gpio_togl;
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_REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
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// Output value XOR for GPIO32
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// 0xf0000000 [31:28] QSPI_SD (0x0)
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// 0x08000000 [27] QSPI_CSN (0)
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// 0x04000000 [26] QSPI_SCK (0)
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// 0x02000000 [25] USB_DM (0)
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// 0x01000000 [24] USB_DP (0)
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// 0x0000ffff [15:0] GPIO (0x0000)
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io_wo_32 gpio_hi_togl;
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_REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
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// GPIO0
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// 0xffffffff [31:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0
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io_rw_32 gpio_oe;
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_REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
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// Output enable value for GPIO32
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// 0xf0000000 [31:28] QSPI_SD (0x0) Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2...
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// 0x08000000 [27] QSPI_CSN (0) Output enable value for QSPI CSn pin
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// 0x04000000 [26] QSPI_SCK (0) Output enable value for QSPI SCK pin
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// 0x02000000 [25] USB_DM (0) Output enable value for USB D- pin
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// 0x01000000 [24] USB_DP (0) Output enable value for USB D+ pin
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// 0x0000ffff [15:0] GPIO (0x0000) Output enable value for GPIO32
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io_rw_32 gpio_hi_oe;
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_REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
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// GPIO0
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// 0xffffffff [31:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i
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io_wo_32 gpio_oe_set;
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_REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
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// Output enable set for GPIO32
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// 0xf0000000 [31:28] QSPI_SD (0x0)
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// 0x08000000 [27] QSPI_CSN (0)
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// 0x04000000 [26] QSPI_SCK (0)
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// 0x02000000 [25] USB_DM (0)
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// 0x01000000 [24] USB_DP (0)
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// 0x0000ffff [15:0] GPIO (0x0000)
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io_wo_32 gpio_hi_oe_set;
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_REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
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// GPIO0
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// 0xffffffff [31:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i
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io_wo_32 gpio_oe_clr;
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_REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
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// Output enable clear for GPIO32
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// 0xf0000000 [31:28] QSPI_SD (0x0)
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// 0x08000000 [27] QSPI_CSN (0)
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// 0x04000000 [26] QSPI_SCK (0)
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// 0x02000000 [25] USB_DM (0)
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// 0x01000000 [24] USB_DP (0)
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// 0x0000ffff [15:0] GPIO (0x0000)
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io_wo_32 gpio_hi_oe_clr;
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_REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
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// GPIO0
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// 0xffffffff [31:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i
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io_wo_32 gpio_oe_togl;
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_REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
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// Output enable XOR for GPIO32
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// 0xf0000000 [31:28] QSPI_SD (0x0)
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// 0x08000000 [27] QSPI_CSN (0)
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// 0x04000000 [26] QSPI_SCK (0)
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// 0x02000000 [25] USB_DM (0)
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// 0x01000000 [24] USB_DP (0)
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// 0x0000ffff [15:0] GPIO (0x0000)
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io_wo_32 gpio_hi_oe_togl;
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_REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
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// Status register for inter-core FIFOs (mailboxes).
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// 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty
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// 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full
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// 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i
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// 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i
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io_rw_32 fifo_st;
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_REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
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// Write access to this core's TX FIFO
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// 0xffffffff [31:0] FIFO_WR (0x00000000)
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io_wo_32 fifo_wr;
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_REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
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// Read access to this core's RX FIFO
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// 0xffffffff [31:0] FIFO_RD (-)
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io_ro_32 fifo_rd;
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_REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
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// Spinlock state
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// 0xffffffff [31:0] SPINLOCK_ST (0x00000000)
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io_ro_32 spinlock_st;
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uint32_t _pad1[8];
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interp_hw_t interp[2];
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// (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes)
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_REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0
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// Spinlock register 0
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// 0xffffffff [31:0] SPINLOCK0 (0x00000000)
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io_rw_32 spinlock[32];
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_REG_(SIO_DOORBELL_OUT_SET_OFFSET) // SIO_DOORBELL_OUT_SET
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// Trigger a doorbell interrupt on the opposite core
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// 0x000000ff [7:0] DOORBELL_OUT_SET (0x00)
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io_rw_32 doorbell_out_set;
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_REG_(SIO_DOORBELL_OUT_CLR_OFFSET) // SIO_DOORBELL_OUT_CLR
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// Clear doorbells which have been posted to the opposite core
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// 0x000000ff [7:0] DOORBELL_OUT_CLR (0x00)
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io_rw_32 doorbell_out_clr;
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_REG_(SIO_DOORBELL_IN_SET_OFFSET) // SIO_DOORBELL_IN_SET
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// Write 1s to trigger doorbell interrupts on this core
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// 0x000000ff [7:0] DOORBELL_IN_SET (0x00)
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io_rw_32 doorbell_in_set;
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_REG_(SIO_DOORBELL_IN_CLR_OFFSET) // SIO_DOORBELL_IN_CLR
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// Check and acknowledge doorbells posted to this core
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// 0x000000ff [7:0] DOORBELL_IN_CLR (0x00)
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io_rw_32 doorbell_in_clr;
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_REG_(SIO_PERI_NONSEC_OFFSET) // SIO_PERI_NONSEC
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// Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so...
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// 0x00000020 [5] TMDS (0) IF 1, detach TMDS encoder (of this core) from the Secure...
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// 0x00000002 [1] INTERP1 (0) If 1, detach interpolator 1 (of this core) from the...
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// 0x00000001 [0] INTERP0 (0) If 1, detach interpolator 0 (of this core) from the...
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io_rw_32 peri_nonsec;
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uint32_t _pad2[3];
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_REG_(SIO_RISCV_SOFTIRQ_OFFSET) // SIO_RISCV_SOFTIRQ
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// Control the assertion of the standard software interrupt (MIP
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// 0x00000200 [9] CORE1_CLR (0) Write 1 to atomically clear the core 1 software interrupt flag
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// 0x00000100 [8] CORE0_CLR (0) Write 1 to atomically clear the core 0 software interrupt flag
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// 0x00000002 [1] CORE1_SET (0) Write 1 to atomically set the core 1 software interrupt flag
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// 0x00000001 [0] CORE0_SET (0) Write 1 to atomically set the core 0 software interrupt flag
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io_rw_32 riscv_softirq;
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_REG_(SIO_MTIME_CTRL_OFFSET) // SIO_MTIME_CTRL
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// Control register for the RISC-V 64-bit Machine-mode timer
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// 0x00000008 [3] DBGPAUSE_CORE1 (1) If 1, the timer pauses when core 1 is in the debug halt state
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// 0x00000004 [2] DBGPAUSE_CORE0 (1) If 1, the timer pauses when core 0 is in the debug halt state
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// 0x00000002 [1] FULLSPEED (0) If 1, increment the timer every cycle (i
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// 0x00000001 [0] EN (1) Timer enable bit
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io_rw_32 mtime_ctrl;
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uint32_t _pad3[2];
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_REG_(SIO_MTIME_OFFSET) // SIO_MTIME
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// Read/write access to the high half of RISC-V Machine-mode timer
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// 0xffffffff [31:0] MTIME (0x00000000)
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io_rw_32 mtime;
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_REG_(SIO_MTIMEH_OFFSET) // SIO_MTIMEH
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// Read/write access to the high half of RISC-V Machine-mode timer
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// 0xffffffff [31:0] MTIMEH (0x00000000)
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io_rw_32 mtimeh;
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_REG_(SIO_MTIMECMP_OFFSET) // SIO_MTIMECMP
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// Low half of RISC-V Machine-mode timer comparator
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// 0xffffffff [31:0] MTIMECMP (0xffffffff)
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io_rw_32 mtimecmp;
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_REG_(SIO_MTIMECMPH_OFFSET) // SIO_MTIMECMPH
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// High half of RISC-V Machine-mode timer comparator
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// 0xffffffff [31:0] MTIMECMPH (0xffffffff)
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io_rw_32 mtimecmph;
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_REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL
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// Control register for TMDS encoder
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// 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders
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// 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle...
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// 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read...
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// 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE
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// 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,...
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// 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,...
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// 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,...
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// 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
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// 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
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// 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
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io_rw_32 tmds_ctrl;
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_REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA
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// Write-only access to the TMDS colour data register
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// 0xffffffff [31:0] TMDS_WDATA (0x00000000)
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io_wo_32 tmds_wdata;
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_REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE
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// Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols)
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// 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000)
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io_ro_32 tmds_peek_single;
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_REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE
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// Get the encoding of one pixel's worth of colour data, packed into a 32-bit value
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// 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000)
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io_ro_32 tmds_pop_single;
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_REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0
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// Get lane 0 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000)
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io_ro_32 tmds_peek_double_l0;
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_REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0
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// Get lane 0 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000)
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io_ro_32 tmds_pop_double_l0;
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_REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1
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// Get lane 1 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000)
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io_ro_32 tmds_peek_double_l1;
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_REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1
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// Get lane 1 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000)
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io_ro_32 tmds_pop_double_l1;
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_REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2
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// Get lane 2 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000)
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io_ro_32 tmds_peek_double_l2;
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_REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2
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// Get lane 2 of the encoding of two pixels' worth of colour data
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// 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000)
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io_ro_32 tmds_pop_double_l2;
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} sio_hw_t;
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#define sio_hw ((sio_hw_t *)SIO_BASE)
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#define sio_ns_hw ((sio_hw_t *)SIO_NONSEC_BASE)
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static_assert(sizeof (sio_hw_t) == 0x01e8, "");
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#endif // _HARDWARE_STRUCTS_SIO_H
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