mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
54 lines
2.0 KiB
C
54 lines
2.0 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_SHA256_H
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#define _HARDWARE_STRUCTS_SHA256_H
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/**
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* \file rp2350/sha256.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/sha256.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sha256
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/sha256.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(SHA256_CSR_OFFSET) // SHA256_CSR
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// Control and status register
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// 0x00001000 [12] BSWAP (1) Enable byte swapping of 32-bit values at the point they...
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// 0x00000300 [9:8] DMA_SIZE (0x2) Configure DREQ logic for the correct DMA data size
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// 0x00000010 [4] ERR_WDATA_NOT_RDY (0) Set when a write occurs whilst the SHA-256 core is not...
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// 0x00000004 [2] SUM_VLD (1) If 1, the SHA-256 checksum presented in registers SUM0...
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// 0x00000002 [1] WDATA_RDY (1) If 1, the SHA-256 core is ready to accept more data...
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// 0x00000001 [0] START (0) Write 1 to prepare the SHA-256 core for a new checksum
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io_rw_32 csr;
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_REG_(SHA256_WDATA_OFFSET) // SHA256_WDATA
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// Write data register
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// 0xffffffff [31:0] WDATA (0x00000000) After pulsing START and writing 16 words of data to this...
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io_wo_32 wdata;
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// (Description copied from array index 0 register SHA256_SUM0 applies similarly to other array indexes)
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_REG_(SHA256_SUM0_OFFSET) // SHA256_SUM0
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// 256-bit checksum result
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// 0xffffffff [31:0] SUM0 (0x00000000)
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io_ro_32 sum[8];
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} sha256_hw_t;
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#define sha256_hw ((sha256_hw_t *)SHA256_BASE)
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static_assert(sizeof (sha256_hw_t) == 0x0028, "");
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#endif // _HARDWARE_STRUCTS_SHA256_H
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