mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
66 lines
2.6 KiB
C
66 lines
2.6 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_SAU_H
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#define _HARDWARE_STRUCTS_SAU_H
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/**
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* \file rp2350/sau.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/m33.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
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#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
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#endif
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typedef struct {
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_REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL
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// Allows enabling of the Security Attribution Unit
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// 0x00000002 [1] ALLNS (0) When SAU_CTRL
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// 0x00000001 [0] ENABLE (0) Enables the SAU
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io_rw_32 ctrl;
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_REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE
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// Indicates the number of regions implemented by the Security Attribution Unit
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// 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions
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io_ro_32 type;
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_REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR
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// Selects the region currently accessed by SAU_RBAR and SAU_RLAR
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// 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR
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io_rw_32 rnr;
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_REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR
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// Provides indirect read and write access to the base address of the currently selected SAU region
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// 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region
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io_rw_32 rbar;
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_REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR
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// Provides indirect read and write access to the limit address of the currently selected SAU region
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// 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected...
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// 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to...
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// 0x00000001 [0] ENABLE (0) SAU region enable
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io_rw_32 rlar;
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} armv8m_sau_hw_t;
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#define sau_hw ((armv8m_sau_hw_t *)(PPB_BASE + M33_SAU_CTRL_OFFSET))
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#define sau_ns_hw ((armv8m_sau_hw_t *)(PPB_NONSEC_BASE + M33_SAU_CTRL_OFFSET))
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static_assert(sizeof (armv8m_sau_hw_t) == 0x0014, "");
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#endif // _HARDWARE_STRUCTS_SAU_H
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