mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
126 lines
6.9 KiB
C
126 lines
6.9 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_QMI_H
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#define _HARDWARE_STRUCTS_QMI_H
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/**
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* \file rp2350/qmi.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/qmi.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_qmi
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/qmi.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(QMI_M0_TIMING_OFFSET) // QMI_M0_TIMING
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// Timing configuration register for memory address window 0
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// 0xc0000000 [31:30] COOLDOWN (0x1) Chip select cooldown period
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// 0x30000000 [29:28] PAGEBREAK (0x0) When page break is enabled, chip select will...
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// 0x02000000 [25] SELECT_SETUP (0) Add up to one additional system clock cycle of setup...
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// 0x01800000 [24:23] SELECT_HOLD (0x0) Add up to three additional system clock cycles of active...
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// 0x007e0000 [22:17] MAX_SELECT (0x00) Enforce a maximum assertion duration for this window's...
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// 0x0001f000 [16:12] MIN_DESELECT (0x00) After this window's chip select is deasserted, it...
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// 0x00000700 [10:8] RXDELAY (0x0) Delay the read data sample timing, in units of one half...
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// 0x000000ff [7:0] CLKDIV (0x04) Clock divisor
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io_rw_32 timing;
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_REG_(QMI_M0_RFMT_OFFSET) // QMI_M0_RFMT
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// Read transfer format configuration for memory address window 0.
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// 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for read commands:...
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// 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data...
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// 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits
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// 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits
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// 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer
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// 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any
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// 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any
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// 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address
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// 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any
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io_rw_32 rfmt;
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_REG_(QMI_M0_RCMD_OFFSET) // QMI_M0_RCMD
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// Command constants used for reads from memory address window 0.
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// 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if...
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// 0x000000ff [7:0] PREFIX (0x03) The command prefix bits to prepend on each new transfer,...
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io_rw_32 rcmd;
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_REG_(QMI_M0_WFMT_OFFSET) // QMI_M0_WFMT
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// Write transfer format configuration for memory address window 0.
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// 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for write commands:...
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// 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data...
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// 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits
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// 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits
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// 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer
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// 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any
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// 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any
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// 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address
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// 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any
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io_rw_32 wfmt;
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_REG_(QMI_M0_WCMD_OFFSET) // QMI_M0_WCMD
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// Command constants used for writes to memory address window 0.
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// 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if...
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// 0x000000ff [7:0] PREFIX (0x02) The command prefix bits to prepend on each new transfer,...
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io_rw_32 wcmd;
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} qmi_mem_hw_t;
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typedef struct {
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_REG_(QMI_DIRECT_CSR_OFFSET) // QMI_DIRECT_CSR
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// Control and status for direct serial mode
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// 0xc0000000 [31:30] RXDELAY (0x0) Delay the read data sample timing, in units of one half...
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// 0x3fc00000 [29:22] CLKDIV (0x06) Clock divisor for direct serial mode
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// 0x001c0000 [20:18] RXLEVEL (0x0) Current level of DIRECT_RX FIFO
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// 0x00020000 [17] RXFULL (0) When 1, the DIRECT_RX FIFO is currently full
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// 0x00010000 [16] RXEMPTY (0) When 1, the DIRECT_RX FIFO is currently empty
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// 0x00007000 [14:12] TXLEVEL (0x0) Current level of DIRECT_TX FIFO
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// 0x00000800 [11] TXEMPTY (0) When 1, the DIRECT_TX FIFO is currently empty
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// 0x00000400 [10] TXFULL (0) When 1, the DIRECT_TX FIFO is currently full
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// 0x00000080 [7] AUTO_CS1N (0) When 1, automatically assert the CS1n chip select line...
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// 0x00000040 [6] AUTO_CS0N (0) When 1, automatically assert the CS0n chip select line...
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// 0x00000008 [3] ASSERT_CS1N (0) When 1, assert (i
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// 0x00000004 [2] ASSERT_CS0N (0) When 1, assert (i
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// 0x00000002 [1] BUSY (0) Direct mode busy flag
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// 0x00000001 [0] EN (0) Enable direct mode
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io_rw_32 direct_csr;
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_REG_(QMI_DIRECT_TX_OFFSET) // QMI_DIRECT_TX
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// Transmit FIFO for direct mode
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// 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this...
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// 0x00080000 [19] OE (0) Output enable (active-high)
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// 0x00040000 [18] DWIDTH (0) Data width
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// 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with...
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// 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of...
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io_wo_32 direct_tx;
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_REG_(QMI_DIRECT_RX_OFFSET) // QMI_DIRECT_RX
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// Receive FIFO for direct mode
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// 0x0000ffff [15:0] DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one...
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io_ro_32 direct_rx;
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qmi_mem_hw_t m[2];
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// (Description copied from array index 0 register QMI_ATRANS0 applies similarly to other array indexes)
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_REG_(QMI_ATRANS0_OFFSET) // QMI_ATRANS0
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// Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB).
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// 0x07ff0000 [26:16] SIZE (0x400) Translation aperture size for this virtual address...
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// 0x00000fff [11:0] BASE (0x000) Physical address base for this virtual address range, in...
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io_rw_32 atrans[8];
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} qmi_hw_t;
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#define qmi_hw ((qmi_hw_t *)XIP_QMI_BASE)
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static_assert(sizeof (qmi_hw_t) == 0x0054, "");
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#endif // _HARDWARE_STRUCTS_QMI_H
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