mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
95 lines
4.1 KiB
C
95 lines
4.1 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_NVIC_H
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#define _HARDWARE_STRUCTS_NVIC_H
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/**
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* \file rp2350/nvic.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/m33.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
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#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
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#endif
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typedef struct {
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// (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes)
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_REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0
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// Enables or reads the enabled state of each group of 32 interrupts
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// 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether...
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io_rw_32 iser[2];
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uint32_t _pad0[30];
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// (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes)
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_REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0
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// Clears or reads the enabled state of each group of 32 interrupts
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// 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether...
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io_rw_32 icer[2];
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uint32_t _pad1[30];
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// (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes)
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_REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0
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// Enables or reads the pending state of each group of 32 interrupts
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// 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether...
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io_rw_32 ispr[2];
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uint32_t _pad2[30];
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// (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes)
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_REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0
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// Clears or reads the pending state of each group of 32 interrupts
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// 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether...
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io_rw_32 icpr[2];
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uint32_t _pad3[30];
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// (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes)
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_REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0
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// For each group of 32 interrupts, shows the active state of each interrupt
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// 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state...
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io_rw_32 iabr[2];
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uint32_t _pad4[30];
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// (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes)
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_REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0
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// For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state
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// 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security...
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io_rw_32 itns[2];
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uint32_t _pad5[30];
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// (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes)
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_REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0
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// Sets or reads interrupt priorities
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// 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number...
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// 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number...
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// 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number...
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// 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number...
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io_rw_32 ipr[16];
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} nvic_hw_t;
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#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET))
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#define nvic_ns_hw ((nvic_hw_t *)(PPB_NONSEC_BASE + M33_NVIC_ISER0_OFFSET))
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static_assert(sizeof (nvic_hw_t) == 0x0340, "");
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#endif // _HARDWARE_STRUCTS_NVIC_H
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