mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
51 lines
1.8 KiB
C
51 lines
1.8 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_M33_EPPB_H
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#define _HARDWARE_STRUCTS_M33_EPPB_H
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/**
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* \file rp2350/m33_eppb.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/m33_eppb.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33_eppb
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/m33_eppb.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
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#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
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#endif
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typedef struct {
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// (Description copied from array index 0 register M33_EPPB_NMI_MASK0 applies similarly to other array indexes)
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_REG_(M33_EPPB_NMI_MASK0_OFFSET) // M33_EPPB_NMI_MASK0
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// NMI mask for IRQs 0 through 31
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// 0xffffffff [31:0] NMI_MASK0 (0x00000000)
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io_rw_32 nmi_mask[2];
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_REG_(M33_EPPB_SLEEPCTRL_OFFSET) // M33_EPPB_SLEEPCTRL
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// Nonstandard sleep control register
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// 0x00000004 [2] WICENACK (0) Status signal from the processor's interrupt controller
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// 0x00000002 [1] WICENREQ (1) Request that the next processor deep sleep is a WIC sleep
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// 0x00000001 [0] LIGHT_SLEEP (0) By default, any processor sleep will deassert the...
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io_rw_32 sleepctrl;
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} m33_eppb_hw_t;
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#define eppb_hw ((m33_eppb_hw_t *)EPPB_BASE)
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static_assert(sizeof (m33_eppb_hw_t) == 0x000c, "");
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#endif // _HARDWARE_STRUCTS_M33_EPPB_H
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