mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
317 lines
14 KiB
C
317 lines
14 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_IO_QSPI_H
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#define _HARDWARE_STRUCTS_IO_QSPI_H
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/**
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* \file rp2350/io_qspi.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/io_qspi.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_qspi
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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/**
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* \brief QSPI pin function selectors on RP2350 (used as typedef \ref gpio_function1_t)
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*/
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typedef enum gpio_function1_rp2350 {
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GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function
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GPIO_FUNC1_UART = 2, ///< Select UART as QSPI pin function
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GPIO_FUNC1_I2C = 3, ///< Select I2C as QSPI pin function
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GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function
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GPIO_FUNC1_UART_AUX = 11, ///< Select UART_AUX as QSPI pin function
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GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function
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} gpio_function1_t;
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typedef struct {
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_REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
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// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
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// 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
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// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
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// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
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io_ro_32 status;
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_REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
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// 0x30000000 [29:28] IRQOVER (0x0)
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// 0x00030000 [17:16] INOVER (0x0)
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// 0x0000c000 [15:14] OEOVER (0x0)
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// 0x00003000 [13:12] OUTOVER (0x0)
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// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
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io_rw_32 ctrl;
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} io_qspi_status_ctrl_hw_t;
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typedef struct {
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_REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
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// Interrupt Enable for proc0
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// 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
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// 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
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// 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
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// 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
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// 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
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// 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
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// 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
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// 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
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// 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
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// 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
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// 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
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// 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
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// 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
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// 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
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// 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
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// 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
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// 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
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// 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
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// 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
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// 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
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// 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
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// 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
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// 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
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// 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
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// 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
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// 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
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// 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
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// 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
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// 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
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// 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
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// 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
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// 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
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io_rw_32 inte;
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_REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
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// Interrupt Force for proc0
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// 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
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// 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
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// 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
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// 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
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// 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
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// 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
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// 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
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// 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
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// 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
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// 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
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// 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
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// 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
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// 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
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// 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
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// 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
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// 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
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// 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
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// 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
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// 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
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// 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
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// 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
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// 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
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// 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
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// 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
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// 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
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// 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
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// 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
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// 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
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// 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
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// 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
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// 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
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// 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
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io_rw_32 intf;
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_REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
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// Interrupt status after masking & forcing for proc0
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// 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
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// 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
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// 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
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// 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
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// 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
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// 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
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// 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
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// 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
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// 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
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// 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
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// 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
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// 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
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// 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
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// 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
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// 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
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// 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
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// 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
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// 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
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// 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
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// 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
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// 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
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// 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
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// 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
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// 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
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// 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
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// 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
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// 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
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// 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
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// 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
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// 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
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// 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
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// 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
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io_ro_32 ints;
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} io_qspi_irq_ctrl_hw_t;
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typedef struct {
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_REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET) // IO_QSPI_USBPHY_DP_STATUS
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// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
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// 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
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// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
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// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
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io_ro_32 usbphy_dp_status;
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_REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET) // IO_QSPI_USBPHY_DP_CTRL
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// 0x30000000 [29:28] IRQOVER (0x0)
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// 0x00030000 [17:16] INOVER (0x0)
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// 0x0000c000 [15:14] OEOVER (0x0)
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// 0x00003000 [13:12] OUTOVER (0x0)
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// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
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io_rw_32 usbphy_dp_ctrl;
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_REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET) // IO_QSPI_USBPHY_DM_STATUS
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// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
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// 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
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// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
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// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
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io_ro_32 usbphy_dm_status;
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_REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET) // IO_QSPI_USBPHY_DM_CTRL
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// 0x30000000 [29:28] IRQOVER (0x0)
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// 0x00030000 [17:16] INOVER (0x0)
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// 0x0000c000 [15:14] OEOVER (0x0)
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// 0x00003000 [13:12] OUTOVER (0x0)
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// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
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io_rw_32 usbphy_dm_ctrl;
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io_qspi_status_ctrl_hw_t io[6];
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uint32_t _pad0[112];
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_REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_SECURE
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// 0x00000080 [7] GPIO_QSPI_SD3 (0)
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// 0x00000040 [6] GPIO_QSPI_SD2 (0)
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// 0x00000020 [5] GPIO_QSPI_SD1 (0)
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// 0x00000010 [4] GPIO_QSPI_SD0 (0)
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// 0x00000008 [3] GPIO_QSPI_SS (0)
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// 0x00000004 [2] GPIO_QSPI_SCLK (0)
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// 0x00000002 [1] USBPHY_DM (0)
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// 0x00000001 [0] USBPHY_DP (0)
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io_ro_32 irqsummary_proc0_secure;
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_REG_(IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_NONSECURE
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// 0x00000080 [7] GPIO_QSPI_SD3 (0)
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// 0x00000040 [6] GPIO_QSPI_SD2 (0)
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// 0x00000020 [5] GPIO_QSPI_SD1 (0)
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// 0x00000010 [4] GPIO_QSPI_SD0 (0)
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// 0x00000008 [3] GPIO_QSPI_SS (0)
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// 0x00000004 [2] GPIO_QSPI_SCLK (0)
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// 0x00000002 [1] USBPHY_DM (0)
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// 0x00000001 [0] USBPHY_DP (0)
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io_ro_32 irqsummary_proc0_nonsecure;
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_REG_(IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_SECURE
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// 0x00000080 [7] GPIO_QSPI_SD3 (0)
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// 0x00000040 [6] GPIO_QSPI_SD2 (0)
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// 0x00000020 [5] GPIO_QSPI_SD1 (0)
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// 0x00000010 [4] GPIO_QSPI_SD0 (0)
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// 0x00000008 [3] GPIO_QSPI_SS (0)
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// 0x00000004 [2] GPIO_QSPI_SCLK (0)
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// 0x00000002 [1] USBPHY_DM (0)
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// 0x00000001 [0] USBPHY_DP (0)
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io_ro_32 irqsummary_proc1_secure;
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_REG_(IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_NONSECURE
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// 0x00000080 [7] GPIO_QSPI_SD3 (0)
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// 0x00000040 [6] GPIO_QSPI_SD2 (0)
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// 0x00000020 [5] GPIO_QSPI_SD1 (0)
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// 0x00000010 [4] GPIO_QSPI_SD0 (0)
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// 0x00000008 [3] GPIO_QSPI_SS (0)
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// 0x00000004 [2] GPIO_QSPI_SCLK (0)
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// 0x00000002 [1] USBPHY_DM (0)
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// 0x00000001 [0] USBPHY_DP (0)
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io_ro_32 irqsummary_proc1_nonsecure;
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_REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE
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// 0x00000080 [7] GPIO_QSPI_SD3 (0)
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// 0x00000040 [6] GPIO_QSPI_SD2 (0)
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// 0x00000020 [5] GPIO_QSPI_SD1 (0)
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// 0x00000010 [4] GPIO_QSPI_SD0 (0)
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// 0x00000008 [3] GPIO_QSPI_SS (0)
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// 0x00000004 [2] GPIO_QSPI_SCLK (0)
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// 0x00000002 [1] USBPHY_DM (0)
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// 0x00000001 [0] USBPHY_DP (0)
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io_ro_32 irqsummary_dormant_wake_secure;
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_REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE
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// 0x00000080 [7] GPIO_QSPI_SD3 (0)
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// 0x00000040 [6] GPIO_QSPI_SD2 (0)
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// 0x00000020 [5] GPIO_QSPI_SD1 (0)
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// 0x00000010 [4] GPIO_QSPI_SD0 (0)
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// 0x00000008 [3] GPIO_QSPI_SS (0)
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// 0x00000004 [2] GPIO_QSPI_SCLK (0)
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// 0x00000002 [1] USBPHY_DM (0)
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// 0x00000001 [0] USBPHY_DP (0)
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io_ro_32 irqsummary_dormant_wake_nonsecure;
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_REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
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// Raw Interrupts
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// 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
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// 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
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// 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
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// 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
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// 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
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// 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
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// 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
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// 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
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// 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
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// 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
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// 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
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// 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
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// 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
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// 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
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// 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
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// 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
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// 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
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// 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
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// 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
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// 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
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// 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
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// 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
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// 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
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// 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
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// 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
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// 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
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// 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
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// 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
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// 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
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// 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
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// 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
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// 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
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io_rw_32 intr;
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union {
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struct {
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io_qspi_irq_ctrl_hw_t proc0_irq_ctrl;
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io_qspi_irq_ctrl_hw_t proc1_irq_ctrl;
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io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl;
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};
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io_qspi_irq_ctrl_hw_t irq_ctrl[3];
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};
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} io_qspi_hw_t;
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#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE)
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static_assert(sizeof (io_qspi_hw_t) == 0x0240, "");
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#endif // _HARDWARE_STRUCTS_IO_QSPI_H
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