mirror of
https://github.com/andreili/katapult.git
synced 2025-08-24 03:44:06 +02:00
c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
71 lines
3.7 KiB
C
71 lines
3.7 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_HSTX_CTRL_H
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#define _HARDWARE_STRUCTS_HSTX_CTRL_H
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/**
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* \file rp2350/hstx_ctrl.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/hstx_ctrl.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_ctrl
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/hstx_ctrl.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(HSTX_CTRL_CSR_OFFSET) // HSTX_CTRL_CSR
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// 0xf0000000 [31:28] CLKDIV (0x1) Clock period of the generated clock, measured in HSTX...
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// 0x0f000000 [27:24] CLKPHASE (0x0) Set the initial phase of the generated clock
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// 0x001f0000 [20:16] N_SHIFTS (0x05) Number of times to shift the shift register before...
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// 0x00001f00 [12:8] SHIFT (0x06) How many bits to right-rotate the shift register by each cycle
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// 0x00000060 [6:5] COUPLED_SEL (0x0) Select which PIO to use for coupled mode operation
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// 0x00000010 [4] COUPLED_MODE (0) Enable the PIO-to-HSTX 1:1 connection
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// 0x00000002 [1] EXPAND_EN (0) Enable the command expander
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// 0x00000001 [0] EN (0) When EN is 1, the HSTX will shift out data as it appears...
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io_rw_32 csr;
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// (Description copied from array index 0 register HSTX_CTRL_BIT0 applies similarly to other array indexes)
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_REG_(HSTX_CTRL_BIT0_OFFSET) // HSTX_CTRL_BIT0
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// Data control register for output bit 0
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// 0x00020000 [17] CLK (0) Connect this output to the generated clock, rather than...
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// 0x00010000 [16] INV (0) Invert this data output (logical NOT)
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// 0x00001f00 [12:8] SEL_N (0x00) Shift register data bit select for the second half of...
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// 0x0000001f [4:0] SEL_P (0x00) Shift register data bit select for the first half of the...
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io_rw_32 bit[8];
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_REG_(HSTX_CTRL_EXPAND_SHIFT_OFFSET) // HSTX_CTRL_EXPAND_SHIFT
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// Configure the optional shifter inside the command expander
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// 0x1f000000 [28:24] ENC_N_SHIFTS (0x01) Number of times to consume from the shift register...
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// 0x001f0000 [20:16] ENC_SHIFT (0x00) How many bits to right-rotate the shift register by each...
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// 0x00001f00 [12:8] RAW_N_SHIFTS (0x01) Number of times to consume from the shift register...
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// 0x0000001f [4:0] RAW_SHIFT (0x00) How many bits to right-rotate the shift register by each...
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io_rw_32 expand_shift;
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_REG_(HSTX_CTRL_EXPAND_TMDS_OFFSET) // HSTX_CTRL_EXPAND_TMDS
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// Configure the optional TMDS encoder inside the command expander
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// 0x00e00000 [23:21] L2_NBITS (0x0) Number of valid data bits for the lane 2 TMDS encoder,...
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// 0x001f0000 [20:16] L2_ROT (0x00) Right-rotate applied to the current shifter data before...
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// 0x0000e000 [15:13] L1_NBITS (0x0) Number of valid data bits for the lane 1 TMDS encoder,...
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// 0x00001f00 [12:8] L1_ROT (0x00) Right-rotate applied to the current shifter data before...
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// 0x000000e0 [7:5] L0_NBITS (0x0) Number of valid data bits for the lane 0 TMDS encoder,...
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// 0x0000001f [4:0] L0_ROT (0x00) Right-rotate applied to the current shifter data before...
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io_rw_32 expand_tmds;
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} hstx_ctrl_hw_t;
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#define hstx_ctrl_hw ((hstx_ctrl_hw_t *)HSTX_CTRL_BASE)
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static_assert(sizeof (hstx_ctrl_hw_t) == 0x002c, "");
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#endif // _HARDWARE_STRUCTS_HSTX_CTRL_H
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