mirror of
https://github.com/andreili/katapult.git
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c0014efc4a
Synchronize with the latest Klipper code. This pulls in the latest lib/ files (needed to use the pico-sdk v2.0.0 version). It updates to latest can2040 code (needed for pico-sdk v2.0.0 support). It implements USB double buffering (as is now done in Klipper). It adds in support for additional UART pins (as is now done in Klipper). It adds support for rp2350 chips. This replaces the execute in ram code previously implemented in Katapult with the execute in ram code that is now standard in Klipper. The CONFIG_RP2040_ADD_BOOT_SIGNATURE kconfig symbol was removed and the build now always produces a katapult.withclear.uf2 file. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
72 lines
3.1 KiB
C
72 lines
3.1 KiB
C
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_GLITCH_DETECTOR_H
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#define _HARDWARE_STRUCTS_GLITCH_DETECTOR_H
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/**
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* \file rp2350/glitch_detector.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/glitch_detector.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_glitch_detector
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/glitch_detector.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef struct {
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_REG_(GLITCH_DETECTOR_ARM_OFFSET) // GLITCH_DETECTOR_ARM
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// Forcibly arm the glitch detectors, if they are not already armed by OTP
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// 0x0000ffff [15:0] ARM (0x5bad)
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io_rw_32 arm;
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_REG_(GLITCH_DETECTOR_DISARM_OFFSET) // GLITCH_DETECTOR_DISARM
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// 0x0000ffff [15:0] DISARM (0x0000) Forcibly disarm the glitch detectors, if they are armed by OTP
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io_rw_32 disarm;
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_REG_(GLITCH_DETECTOR_SENSITIVITY_OFFSET) // GLITCH_DETECTOR_SENSITIVITY
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// Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults
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// 0xff000000 [31:24] DEFAULT (0x00)
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// 0x0000c000 [15:14] DET3_INV (0x0) Must be the inverse of DET3, else the default value is used
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// 0x00003000 [13:12] DET2_INV (0x0) Must be the inverse of DET2, else the default value is used
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// 0x00000c00 [11:10] DET1_INV (0x0) Must be the inverse of DET1, else the default value is used
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// 0x00000300 [9:8] DET0_INV (0x0) Must be the inverse of DET0, else the default value is used
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// 0x000000c0 [7:6] DET3 (0x0) Set sensitivity for detector 3
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// 0x00000030 [5:4] DET2 (0x0) Set sensitivity for detector 2
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// 0x0000000c [3:2] DET1 (0x0) Set sensitivity for detector 1
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// 0x00000003 [1:0] DET0 (0x0) Set sensitivity for detector 0
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io_rw_32 sensitivity;
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_REG_(GLITCH_DETECTOR_LOCK_OFFSET) // GLITCH_DETECTOR_LOCK
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// 0x000000ff [7:0] LOCK (0x00) Write any nonzero value to disable writes to ARM,...
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io_rw_32 lock;
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_REG_(GLITCH_DETECTOR_TRIG_STATUS_OFFSET) // GLITCH_DETECTOR_TRIG_STATUS
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// Set when a detector output triggers
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// 0x00000008 [3] DET3 (0)
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// 0x00000004 [2] DET2 (0)
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// 0x00000002 [1] DET1 (0)
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// 0x00000001 [0] DET0 (0)
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io_rw_32 trig_status;
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_REG_(GLITCH_DETECTOR_TRIG_FORCE_OFFSET) // GLITCH_DETECTOR_TRIG_FORCE
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// Simulate the firing of one or more detectors
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// 0x0000000f [3:0] TRIG_FORCE (0x0)
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io_wo_32 trig_force;
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} glitch_detector_hw_t;
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#define glitch_detector_hw ((glitch_detector_hw_t *)GLITCH_DETECTOR_BASE)
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static_assert(sizeof (glitch_detector_hw_t) == 0x0018, "");
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#endif // _HARDWARE_STRUCTS_GLITCH_DETECTOR_H
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